coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch merged into coreboot/master: 1af3663 baytrail: configure acpi SCI irq
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 1af366322e0330960d746e2875d61e202c8dd807 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 10:42:16 2013 -0600 baytrail: configure acpi SCI irq Baytrail has a configurable SCI irq. Add support for properly configuring SCI irq. Note that it is currently fixed to IRQ9, but the code supports setting it to the other supported values. The current mainboards using baytrail defer the madt IRQ override information to the chipset. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted 'SCI is IRQ9' message. Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176075 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4946 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4946 for details. -gerrit

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Patch merged into coreboot/master: 952d85e rambi: mirror bayleybay's eMMC gpio setup
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 952d85e5f2d951850551572b756a6518c734e069 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 08:15:07 2013 -0600 rambi: mirror bayleybay's eMMC gpio setup These changes to the eMMC pads allows the kernel to see the eMMC device. One is able to install onto the eMMC device, and the kernel is loaded and booted from eMMC device. Note, that it may not fully boot because of other issues such as not-completely working ACPI support. BUG=chrome-os-partner:22580 BRANCH=None TEST=booted off of usb drive. can see eMMC device. Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176073 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4945 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4945 for details. -gerrit

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Patch merged into coreboot/master: 8de0ca4 rambi: Fix eDP panel functionality
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 8de0ca435e7cee39cd5b7523aea4c7c59d1113d8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Nov 6 10:58:46 2013 -0800 rambi: Fix eDP panel functionality For some mysterious reason GPIO_S0_NC22 is making the eDP panel go entirely white when it is configured with internal pullup. Since these (supposedly XDP related) pins are unknown functionality lets set them to GPIO_DEFAULT instead of GPIO_NC. Additionally the VBIOS is being changed to issue int15 callback to determine the boot graphics device. If we list both LFP and EFP then the dev/rec screens will show on the panel when HDMI is not attached and otherwise will display on HDMI. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi, see firmware/kernel screens on the panel when HDMI is not attached, and firmware screens on the panel and kernel screens on both when HDMI is attached. Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175952 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4944 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4944 for details. -gerrit

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Patch merged into coreboot/master: 6e32893 baytrail: add support for S3 resume
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 6e3289372c598e3e0702f44e52c04d689172b156 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 6 12:04:50 2013 -0600 baytrail: add support for S3 resume Previously the only path through memory init and coreboot was hardcoding S5. Therefore all S3 paths would not be taken. Allow for S3 resume to work by enabling the proper control paths in romstage. BUG=chrome-os-partner:22867 BRANCH=None TEST=While in kernel 'echo mem > /sys/power/state'. Board went into S3. Power button press resumed back into kernel. Change-Id: I3cbae73223f0d71c74eb3d6b7c25d1b32318ab3e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175940 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4943 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4943 for details. -gerrit

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Patch set updated for coreboot: 2c40ea3 baytrail: add support for S3 resume
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4943 -gerrit commit 2c40ea33880a0f7be025a763a23e7596090f59d0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 6 12:04:50 2013 -0600 baytrail: add support for S3 resume Previously the only path through memory init and coreboot was hardcoding S5. Therefore all S3 paths would not be taken. Allow for S3 resume to work by enabling the proper control paths in romstage. BUG=chrome-os-partner:22867 BRANCH=None TEST=While in kernel 'echo mem > /sys/power/state'. Board went into S3. Power button press resumed back into kernel. Change-Id: I3cbae73223f0d71c74eb3d6b7c25d1b32318ab3e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175940 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/pmc.h | 7 +++-- src/soc/intel/baytrail/romstage/raminit.c | 27 ++++++++++++++-- src/soc/intel/baytrail/romstage/romstage.c | 49 ++++++++++++++++++++++++++++-- 3 files changed, 77 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index 92edb6e..1a7588c 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -24,9 +24,11 @@ #define IOCOM1 0x3f8 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ -#define GEN_PMCONF1 0x20 +#define GEN_PMCON1 0x20 # define AFTERG3_EN (1 << 0) # define UART_EN (1 << 24) +# define PWR_FLR (1 << 16) +# define SUS_PWR_FLR (1 << 14) #define ETR 0x48 # define CF9LOCK (1 << 31) # define LTR_DEF (1 << 22) @@ -86,7 +88,8 @@ #define TMROF_EN (1 << 0) #define PM1_CNT 0x04 #define SLP_EN (1 << 13) -#define SLP_TYP (7 << 10) +#define SLP_TYP_SHIFT 10 +#define SLP_TYP (7 << SLP_TYP_SHIFT) #define SLP_TYP_S0 0 #define SLP_TYP_S1 1 #define SLP_TYP_S3 5 diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 98d389e..017f37d 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -18,7 +18,9 @@ */ #include <stddef.h> +#include <arch/hlt.h> #include <arch/io.h> +#include <bootmode.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> @@ -28,8 +30,14 @@ #include <baytrail/iomap.h> #include <baytrail/iosf.h> #include <baytrail/pci_devs.h> +#include <baytrail/reset.h> #include <baytrail/romstage.h> +static void reset_system(void) +{ + warm_reset(); + while(1) { hlt(); } +} static void enable_smbus(void) { @@ -111,9 +119,16 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; - if (!mrc_cache_get_current(&cache)) { + if (recovery_mode_enabled()) { + printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); + } else if (!mrc_cache_get_current(&cache)) { mp->saved_data_size = cache->size; mp->saved_data = &cache->data[0]; + } else if (prev_sleep_state == 3) { + /* If waking from S3 and no cache then. */ + printk(BIOS_DEBUG, "No MRC cache found in S3 resume path.\n"); + post_code(POST_RESUME_FAILURE); + reset_system(); } else { printk(BIOS_DEBUG, "No MRC cache found.\n"); } @@ -132,7 +147,15 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) print_dram_info(); - cbmem_initialize_empty(); + if (prev_sleep_state != 3) { + cbmem_initialize_empty(); + } else if (cbmem_initialize()) { + #if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n"); + /* Failed S3 resume, reset to come up cleanly */ + reset_system(); + #endif + } printk(BIOS_DEBUG, "MRC Wrapper returned %d\n", ret); printk(BIOS_DEBUG, "MRC data at %p %d bytes\n", mp->data_to_save, diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 5af9bf4..969e848 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -36,6 +36,7 @@ #include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> +#include <baytrail/pmc.h> #include <baytrail/reset.h> #include <baytrail/romstage.h> #include <baytrail/smm.h> @@ -139,10 +140,50 @@ void * asmlinkage romstage_main(unsigned long bist, return setup_stack_and_mttrs(); } +/* Return 0, 3, or 5 to indicate the previous sleep state. */ +static int chipset_prev_sleep_state(void) +{ + uint16_t pm1_sts; + uint32_t pm1_cnt; + uint32_t gen_pmcon1; + /* Default to S0. */ + int prev_sleep_state = 0; + + pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + + if (pm1_sts & WAK_STS) { + switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + #if CONFIG_HAVE_ACPI_RESUME + case SLP_TYP_S3: + prev_sleep_state = 3; + break; + #endif + case SLP_TYP_S5: + prev_sleep_state = 5; + } + /* Clear SLP_TYP. */ + outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + } + + gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { + /* Clear power failure bits. */ + write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1); + prev_sleep_state = 5; + } + + printk(BIOS_DEBUG, "pm1_sts = %04x pm1_cnt = %08x gen_pmcon1 = %08x\n", + pm1_sts, pm1_cnt, gen_pmcon1); + + return prev_sleep_state; +} + /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { struct romstage_handoff *handoff; + int prev_sleep_state; mark_ts(params, timestamp_get()); @@ -150,14 +191,18 @@ void romstage_common(struct romstage_params *params) boot_count_increment(); #endif + prev_sleep_state = chipset_prev_sleep_state(); + + printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state); + /* Initialize RAM */ - raminit(params->mrc_params, 5); + raminit(params->mrc_params, prev_sleep_state); mark_ts(params, timestamp_get()); handoff = romstage_handoff_find_or_add(); if (handoff != NULL) - handoff->s3_resume = 0; + handoff->s3_resume = (prev_sleep_state == 3); else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n");

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Patch set updated for coreboot: e38adc9 baytrail: Enable Turbo/Burst and set some magic MSRs
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4952 -gerrit commit e38adc97e870fbd603b1064952965799f3abd3b9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Nov 5 12:59:50 2013 -0800 baytrail: Enable Turbo/Burst and set some magic MSRs As far as I can tell turbo enabling behaves like it did on haswell so use the standard code. There are also some magic values to set in some magic MSRs related to turbo and package power so they report correctly. The L2 cache shrink is enabled and a threshold is set that makes both dual and quad core happy. C1E is disabled to match the reference code. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175743 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/msr.h | 8 ++++++++ src/soc/intel/baytrail/cpu.c | 35 +++++++++++++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 4f3a202..81b2c24 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -6,6 +6,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo ramstage-y += memmap.c romstage-y += memmap.c diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h index 5094f96..462f249 100644 --- a/src/soc/intel/baytrail/baytrail/msr.h +++ b/src/soc/intel/baytrail/baytrail/msr.h @@ -23,9 +23,17 @@ #define MSR_IA32_PLATFORM_ID 0x17 #define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +#define MSR_POWER_MISC 0x120 #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 +#define MSR_POWER_CTL 0x1fc +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_PKG_POWER_LIMIT 0x610 #define MSR_IACORE_RATIOS 0x66a #define MSR_IACORE_VIDS 0x66b +#define MSR_PKG_TURBO_CFG1 0x670 +#define MSR_CPU_TURBO_WKLD_CFG1 0x671 +#define MSR_CPU_TURBO_WKLD_CFG2 0x672 #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index c550531..e3bdc42 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -21,13 +21,16 @@ #include <console/console.h> #include <cpu/cpu.h> #include <cpu/intel/microcode.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic.h> #include <cpu/x86/mp.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/smm.h> +#include <reg_script.h> +#include <baytrail/msr.h> #include <baytrail/pattrs.h> #include <baytrail/ramstage.h> #include <baytrail/smm.h> @@ -48,6 +51,26 @@ static int adjust_apic_id(int index, int apic_id) return 2 * index; } +/* Package level MSRs */ +const struct reg_script package_msr_script[] = { + /* Set Package TDP to ~7W */ + REG_MSR_WRITE(MSR_PKG_POWER_LIMIT, 0x3880fa), + REG_MSR_WRITE(MSR_PKG_TURBO_CFG1, 0x702), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG1, 0x200b), + REG_MSR_WRITE(MSR_CPU_TURBO_WKLD_CFG2, 0), + REG_SCRIPT_END +}; + +/* Core level MSRs */ +const struct reg_script core_msr_script[] = { + /* Dynamic L2 shrink enable and threshold */ + REG_MSR_RMW(MSR_PMG_CST_CONFIG_CONTROL, ~0x3f000f, 0xe0008), + /* Disable C1E */ + REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + REG_MSR_OR(MSR_POWER_MISC, 0x44), + REG_SCRIPT_END +}; + void baytrail_init_cpus(device_t dev) { struct bus *cpu_bus = dev->link_list; @@ -66,6 +89,12 @@ void baytrail_init_cpus(device_t dev) mp_params.num_records = ARRAY_SIZE(mp_steps); mp_params.microcode_pointer = pattrs->microcode_patch; + /* Set package MSRs */ + reg_script_run(package_msr_script); + + /* Enable Turbo/Burst Mode */ + enable_turbo(); + if (mp_init(cpu_bus, &mp_params)) { printk(BIOS_ERR, "MP initialization failure.\n"); } @@ -74,6 +103,12 @@ void baytrail_init_cpus(device_t dev) static void baytrail_core_init(device_t cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); + + /* Set core MSRs */ + reg_script_run(core_msr_script); + + /* Set this core to max frequency ratio */ + set_max_freq(); } static struct device_operations cpu_dev_ops = {

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Patch set updated for coreboot: 53bc929 baytrail: include mainboard's superio.asl
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4949 -gerrit commit 53bc9296436ef985a575885387bbcc46ae7613cf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 14:33:21 2013 -0600 baytrail: include mainboard's superio.asl The mainboard needs an opportunity to hang devices off of the LPC device. Therefore, provide this opportunity for the mainboard. BUG=chrome-os-partner:23505 BRANCH=None TEST=Buit and booted with keyboard. Keys work. Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176133 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/acpi/lpc.asl | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 24fa9c7..408d2b4 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -138,6 +138,9 @@ Device (LPCB) }) } + // Include mainboard's superio.asl file. + #include "acpi/superio.asl" + #ifdef ENABLE_TPM Device (TPM) // Trusted Platform Module {

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Patch set updated for coreboot: accf30c rambi: update EC support
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4948 -gerrit commit accf30c15daeb831972a3e30b99a0de8c0a35e2a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 11:19:34 2013 -0600 rambi: update EC support Fix the SMI and SCI gpios for Rambi. Also, add in the EC callbacks for the SMI handler. Note that the handler for GPI SMIs has not been tested yet as baytrail chipset code doesn't yet support setting up those configurations yet. BUG=chrome-os-partner:23505 BRANCH=None TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts for the EC's SCI GPI. Also was able to see Chrome EC messages with CONFIG_DEBUG_SMI and powering down at the dev screen. Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176077 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/ec.h | 7 ++- src/mainboard/google/rambi/mainboard_smi.c | 90 +++++++++++++++++++++++++++++- 2 files changed, 93 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/rambi/ec.h b/src/mainboard/google/rambi/ec.h index c55a504..bd98b2a 100644 --- a/src/mainboard/google/rambi/ec.h +++ b/src/mainboard/google/rambi/ec.h @@ -22,9 +22,10 @@ #include <ec/google/chromeec/ec_commands.h> -/* TODO(adurbin): Need to figure out how to handle 2 sets of GPIO banks. */ -#define EC_SCI_GPI 0 /* GPIO_SC_0 is EC_SCI# */ -#define EC_SMI_GPI 7 /* GPIO_SSUS_7 is EC_SMI# */ +/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */ +#define EC_SCI_GPI 24 +/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */ +#define EC_SMI_GPI 23 #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c index 0571baf..ac5c841 100644 --- a/src/mainboard/google/rambi/mainboard_smi.c +++ b/src/mainboard/google/rambi/mainboard_smi.c @@ -20,7 +20,13 @@ #include <arch/io.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <elog.h> + +#include <ec/google/chromeec/ec.h> +#include "ec.h" + #include <baytrail/nvs.h> +#include <baytrail/pmc.h> int mainboard_io_trap_handler(int smif) { @@ -43,11 +49,81 @@ int mainboard_io_trap_handler(int smif) return 1; } +static uint8_t mainboard_smi_ec(void) +{ + uint8_t cmd = google_chromeec_get_event(); + uint16_t pmbase = get_pmbase(); + uint32_t pm1_cnt; + +#if CONFIG_ELOG_GSMI + /* Log this event */ + if (cmd) + elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd); +#endif + + switch (cmd) { + case EC_HOST_EVENT_LID_CLOSED: + printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n"); + + /* Go to S5 */ + pm1_cnt = inl(pmbase + PM1_CNT); + pm1_cnt |= SLP_TYP | (SLP_TYP_S5 << SLP_TYP_SHIFT); + outl(pm1_cnt, pmbase + PM1_CNT); + break; + } + + return cmd; +} + +void mainboard_smi_gpi(uint32_t gpi_sts) +{ + if (gpi_sts & (1 << EC_SMI_GPI)) { + /* Process all pending events */ + while (mainboard_smi_ec() != 0); + } +} + +void mainboard_smi_sleep(uint8_t slp_typ) +{ + /* Disable USB charging if required */ + switch (slp_typ) { + case 3: + if (smm_get_gnvs()->s3u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s3u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS); + break; + case 5: + if (smm_get_gnvs()->s5u0 == 0) + google_chromeec_set_usb_charge_mode( + 0, USB_CHARGE_MODE_DISABLED); + if (smm_get_gnvs()->s5u1 == 0) + google_chromeec_set_usb_charge_mode( + 1, USB_CHARGE_MODE_DISABLED); + + /* Enable wake events */ + google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS); + break; + } + + /* Disable SCI and SMI events */ + google_chromeec_set_smi_mask(0); + google_chromeec_set_sci_mask(0); + + /* Clear pending events that may trigger immediate wake */ + while (google_chromeec_get_event() != 0); +} + #define APMC_FINALIZE 0xcb static int mainboard_finalized = 0; -int mainboard_smi_apmc(u8 apmc) +int mainboard_smi_apmc(uint8_t apmc) { switch (apmc) { case APMC_FINALIZE: @@ -58,6 +134,18 @@ int mainboard_smi_apmc(u8 apmc) mainboard_finalized = 1; break; + case APM_CNT_ACPI_ENABLE: + google_chromeec_set_smi_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS); + break; + case APM_CNT_ACPI_DISABLE: + google_chromeec_set_sci_mask(0); + /* Clear all pending events */ + while (google_chromeec_get_event() != 0); + google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);; + break; } return 0; }

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Patch set updated for coreboot: 285aaae regscript: Add support for MSR type
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4951 -gerrit commit 285aaae7d2d3f1275d1e1b2a26ce8e7bb8a4becb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 8 23:00:24 2013 -0800 regscript: Add support for MSR type This required changing value/mask types to uint64_t. Another option would be to use id field to select low or high 32 bits of the MSR and set them independently. BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi Change-Id: Ied9998058a8035bf3f003185236f3be3e0df7fc9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176304 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/reg_script.h | 26 ++++++++++- src/lib/reg_script.c | 116 +++++++++++++++++++++++++++++++---------------- 2 files changed, 102 insertions(+), 40 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 18eda0c..81a4648 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -59,12 +59,14 @@ enum { REG_SCRIPT_TYPE_MMIO, REG_SCRIPT_TYPE_RES, REG_SCRIPT_TYPE_IOSF, + REG_SCRIPT_TYPE_MSR, }; enum { REG_SCRIPT_SIZE_8, REG_SCRIPT_SIZE_16, REG_SCRIPT_SIZE_32, + REG_SCRIPT_SIZE_64, }; struct reg_script { @@ -72,8 +74,8 @@ struct reg_script { uint32_t type; uint32_t size; uint32_t reg; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; uint32_t timeout; union { uint32_t id; @@ -290,6 +292,26 @@ struct reg_script { REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) /* + * CPU Model Specific Register + */ + +#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_MSR, \ + REG_SCRIPT_SIZE_64, \ + reg_, mask_, value_, timeout_, 0) +#define REG_MSR_READ(reg_) \ + REG_SCRIPT_MSR(READ, reg_, 0, 0, 0) +#define REG_MSR_WRITE(reg_, value_) \ + REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) +#define REG_MSR_RMW(reg_, mask_, value_) \ + REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) +#define REG_MSR_OR(reg_, value_) \ + REG_MSR_RMW(reg_, -1ULL, value_) +#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) + +/* * Chain to another table. */ #define REG_SCRIPT_NEXT(next_) \ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 252aa12..3ca0b4a 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -26,6 +26,10 @@ #include <stdint.h> #include <reg_script.h> +#if CONFIG_ARCH_X86 +#include <cpu/x86/msr.h> +#endif + #if CONFIG_SOC_INTEL_BAYTRAIL #include <baytrail/iosf.h> #endif @@ -285,7 +289,31 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) #endif } -static uint32_t reg_script_read(struct reg_script_context *ctx) +static uint64_t reg_script_read_msr(struct reg_script_context *ctx) +{ +#if CONFIG_ARCH_X86 + const struct reg_script *step = reg_script_get_step(ctx); + msr_t msr = rdmsr(step->reg); + uint64_t value = msr.hi; + value = msr.hi; + value <<= 32; + value |= msr.lo; + return value; +#endif +} + +static void reg_script_write_msr(struct reg_script_context *ctx) +{ +#if CONFIG_ARCH_X86 + const struct reg_script *step = reg_script_get_step(ctx); + msr_t msr; + msr.hi = step->value >> 32; + msr.lo = step->value & 0xffffffff; + wrmsr(step->reg, msr); +#endif +} + +static uint64_t reg_script_read(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx); @@ -300,6 +328,8 @@ static uint32_t reg_script_read(struct reg_script_context *ctx) return reg_script_read_res(ctx); case REG_SCRIPT_TYPE_IOSF: return reg_script_read_iosf(ctx); + case REG_SCRIPT_TYPE_MSR: + return reg_script_read_msr(ctx); } return 0; } @@ -324,12 +354,15 @@ static void reg_script_write(struct reg_script_context *ctx) case REG_SCRIPT_TYPE_IOSF: reg_script_write_iosf(ctx); break; + case REG_SCRIPT_TYPE_MSR: + reg_script_write_msr(ctx); + break; } } static void reg_script_rmw(struct reg_script_context *ctx) { - uint32_t value; + uint64_t value; const struct reg_script *step = reg_script_get_step(ctx); struct reg_script write_step = *step; @@ -349,50 +382,57 @@ static void reg_script_rmw(struct reg_script_context *ctx) static void reg_script_run_next(struct reg_script_context *ctx, const struct reg_script *step); -static void reg_script_run_with_context(struct reg_script_context *ctx) + +static void reg_script_run_step(struct reg_script_context *ctx, + const struct reg_script *step) { - uint32_t value = 0, try; + uint64_t value = 0, try; + switch (step->command) { + case REG_SCRIPT_COMMAND_READ: + (void)reg_script_read(ctx); + break; + case REG_SCRIPT_COMMAND_WRITE: + reg_script_write(ctx); + break; + case REG_SCRIPT_COMMAND_RMW: + reg_script_rmw(ctx); + break; + case REG_SCRIPT_COMMAND_POLL: + for (try = 0; try < step->timeout; try += POLL_DELAY) { + value = reg_script_read(ctx) & step->mask; + if (value == step->value) + break; + udelay(POLL_DELAY); + } + if (try >= step->timeout) + printk(BIOS_WARNING, "%s: POLL timeout waiting for " + "0x%x to be 0x%lx, got 0x%lx\n", __func__, + step->reg, (unsigned long)step->value, + (unsigned long)value); + break; + case REG_SCRIPT_COMMAND_SET_DEV: + reg_script_set_dev(ctx, step->dev); + break; + case REG_SCRIPT_COMMAND_NEXT: + reg_script_run_next(ctx, step->next); + break; + default: + printk(BIOS_WARNING, "Invalid command: %08x\n", + step->command); + break; + } +} + +static void reg_script_run_with_context(struct reg_script_context *ctx) +{ while (1) { const struct reg_script *step = reg_script_get_step(ctx); if (step->command == REG_SCRIPT_COMMAND_END) break; - switch (step->command) { - case REG_SCRIPT_COMMAND_READ: - (void)reg_script_read(ctx); - break; - case REG_SCRIPT_COMMAND_WRITE: - reg_script_write(ctx); - break; - case REG_SCRIPT_COMMAND_RMW: - reg_script_rmw(ctx); - break; - case REG_SCRIPT_COMMAND_POLL: - for (try = 0; try < step->timeout; try += POLL_DELAY) { - value = reg_script_read(ctx) & step->mask; - if (value == step->value) - break; - udelay(POLL_DELAY); - } - if (try >= step->timeout) - printk(BIOS_WARNING, "%s: POLL timeout waiting " - "for 0x%08x to be 0x%08x, got 0x%08x\n", - __func__, step->reg, step->value, value); - break; - case REG_SCRIPT_COMMAND_SET_DEV: - reg_script_set_dev(ctx, step->dev); - break; - case REG_SCRIPT_COMMAND_NEXT: - reg_script_run_next(ctx, step->next); - break; - default: - printk(BIOS_WARNING, "Invalid command: %08x\n", - step->command); - break; - } - + reg_script_run_step(ctx, step); reg_script_set_step(ctx, step + 1); } }

1 0

Patch set updated for coreboot: 74c2353 rambi: include the EC devices normally on superio
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4950 -gerrit commit 74c2353e43b0c35a2eec90b7d640ba68a988788a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 08:13:58 2013 -0600 rambi: include the EC devices normally on superio The superio.asl file allows for the mainboard to hang devices off of the LPC bus in ACPI. Include the keyboard controller, EC memory map, and host interface's resources. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted resource reservations in dmesg. Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176134 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/acpi/superio.asl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl index 9092a6c..f40611c 100644 --- a/src/mainboard/google/rambi/acpi/superio.asl +++ b/src/mainboard/google/rambi/acpi/superio.asl @@ -17,4 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Values should match those defined in devicetree.cb */ +/* mainboard configuration */ +#include <mainboard/google/rambi/ec.h> + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl>

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coreboot-gerrit May 2014