coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 32b174b rambi: mirror bayleybay's eMMC gpio setup
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4945 -gerrit commit 32b174b577decbd1563399e38f0d0a438c9c7822 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 08:15:07 2013 -0600 rambi: mirror bayleybay's eMMC gpio setup These changes to the eMMC pads allows the kernel to see the eMMC device. One is able to install onto the eMMC device, and the kernel is loaded and booted from eMMC device. Note, that it may not fully boot because of other issues such as not-completely working ACPI support. BUG=chrome-os-partner:22580 BRANCH=None TEST=booted off of usb drive. can see eMMC device. Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176073 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 9919d30..ad1da09 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -71,17 +71,17 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC013 - NC */ GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ - GPIO_FUNC3, /* S0-SC016 - MMC1_CLK */ - GPIO_FUNC3, /* S0-SC017 - MMC1_D[0] */ - GPIO_FUNC3, /* S0-SC018 - MMC1_D[1] */ - GPIO_FUNC3, /* S0-SC019 - MMC1_D[2] */ - GPIO_FUNC3, /* S0-SC020 - MMC1_D[3] */ - GPIO_FUNC3, /* S0-SC021 - MMC1_D[4] */ - GPIO_FUNC3, /* S0-SC022 - MMC1_D[5] */ - GPIO_FUNC3, /* S0-SC023 - MMC1_D[6] */ - GPIO_FUNC3, /* S0-SC024 - MMC1_D[7] */ - GPIO_FUNC3, /* S0-SC025 - MMC1_CMD */ - GPIO_FUNC3, /* S0-SC026 - MMC1_RST */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC026 - MMC1_45_RST */ GPIO_NC, /* S0-SC027 - NC */ GPIO_NC, /* S0-SC028 - NC */ GPIO_NC, /* S0-SC029 - NC */

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Patch set updated for coreboot: 28bfc5d rambi: Fix eDP panel functionality
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4944 -gerrit commit 28bfc5defa0b6112055bef73f964fcc96e8f06d1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Nov 6 10:58:46 2013 -0800 rambi: Fix eDP panel functionality For some mysterious reason GPIO_S0_NC22 is making the eDP panel go entirely white when it is configured with internal pullup. Since these (supposedly XDP related) pins are unknown functionality lets set them to GPIO_DEFAULT instead of GPIO_NC. Additionally the VBIOS is being changed to issue int15 callback to determine the boot graphics device. If we list both LFP and EFP then the dev/rec screens will show on the panel when HDMI is not attached and otherwise will display on HDMI. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi, see firmware/kernel screens on the panel when HDMI is not attached, and firmware screens on the panel and kernel screens on both when HDMI is attached. Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175952 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 18 +++++++++--------- src/mainboard/google/rambi/mainboard.c | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index d7082be..9919d30 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -38,15 +38,15 @@ static const struct soc_gpio_map gpncore_gpio_map[] = { GPIO_NC, /* S0_NC12 - NC */ GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ GPIO_NC, /* S0_NC14 - NC */ - GPIO_NC, /* S0_NC15 - XDP_GPIO_S0_NC15 */ - GPIO_NC, /* S0_NC16 - XDP_GPIO_S0_NC16 */ - GPIO_NC, /* S0_NC17 - XDP_GPIO_S0_NC17 */ - GPIO_NC, /* S0_NC18 - XDP_GPIO_S0_NC18 */ - GPIO_NC, /* S0_NC19 - XDP_GPIO_S0_NC19 */ - GPIO_NC, /* S0_NC20 - XDP_GPIO_S0_NC20 */ - GPIO_NC, /* S0_NC21 - XDP_GPIO_S0_NC21 */ - GPIO_NC, /* S0_NC22 - XDP_GPIO_S0_NC22 */ - GPIO_NC, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ GPIO_NC, /* S0_NC24 - NC */ GPIO_NC, /* S0_NC25 - NC */ GPIO_NC, /* S0_NC26 - NC */ diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 8c5b666..4ef8a9f 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -75,7 +75,7 @@ static int int15_handler(void) * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0000; + X86_CX = 0x0006; res = 1; break; case 0x5f51:

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Patch set updated for coreboot: 75fa9ee baytrail: add more irq defintions
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4947 -gerrit commit 75fa9eea41996119adabb15dec3c30050c64e9b7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 10:47:01 2013 -0600 baytrail: add more irq defintions The IRQs used for devices that are in acpi mode are added as well as the IRQ defitions for the dedicated GPIO IRQ routing. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built. Change-Id: I2eed5a4584e2d908c32617c9289a2abeaa30bd44 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176120 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/irq.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h index 6461878..2359d21 100644 --- a/src/soc/intel/baytrail/baytrail/irq.h +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -28,7 +28,33 @@ #define PIRQF_APIC_IRQ 21 #define PIRQG_APIC_IRQ 22 #define PIRQH_APIC_IRQ 23 +/* The below IRQs are for when devices are in ACPI mode. Active low. */ +#define LPE_DMA0_IRQ 24 +#define LPE_DMA1_IRQ 25 +#define LPE_SSP0_IRQ 26 +#define LPE_SSP1_IRQ 27 +#define LPE_SSP2_IRQ 28 +#define LPE_IPC2HOST_IRQ 29 +#define LPSS_I2C1_IRQ 32 +#define LPSS_I2C2_IRQ 33 +#define LPSS_I2C3_IRQ 34 +#define LPSS_I2C4_IRQ 35 +#define LPSS_I2C5_IRQ 36 +#define LPSS_I2C6_IRQ 37 +#define LPSS_I2C7_IRQ 38 +#define LPSS_HSUART1_IRQ 39 +#define LPSS_HSUART2_IRQ 40 +#define LPSS_SPI_IRQ 41 +#define LPSS_DMA2_IRQ 42 +#define LPSS_DMA1_IRQ 43 +#define SCC_EMMC_IRQ 45 +#define SCC_SDIO_IRQ 46 +#define SCC_SD_IRQ 47 +/* The dedicated gpio irqs are active high. */ +#define GPIO_S0_DED_IRQ(slot) (51 + (slot)) +#define GPIO_S5_DED_IRQ(slot) (67 + (slot)) +/* PIC IRQ settings. */ #define PIRQ_PIC_IRQDISABLE 0x0 #define PIRQ_PIC_IRQ3 0x3 #define PIRQ_PIC_IRQ4 0x4

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Patch set updated for coreboot: a821285 baytrail: configure acpi SCI irq
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4946 -gerrit commit a821285152cc7a114ffbf7562a40fc35e864ac0f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 10:42:16 2013 -0600 baytrail: configure acpi SCI irq Baytrail has a configurable SCI irq. Add support for properly configuring SCI irq. Note that it is currently fixed to IRQ9, but the code supports setting it to the other supported values. The current mainboards using baytrail defer the madt IRQ override information to the chipset. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted 'SCI is IRQ9' message. Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176075 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/acpi_tables.c | 6 +--- src/soc/intel/baytrail/acpi.c | 61 +++++++++++++++++++++++++++++++- src/soc/intel/baytrail/baytrail/acpi.h | 1 + src/soc/intel/baytrail/baytrail/irq.h | 11 ++++++ src/soc/intel/baytrail/southcluster.c | 4 +++ 5 files changed, 77 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index f61db1d..a4754f1 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -78,11 +78,7 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + current = acpi_madt_irq_overrides(current); return current; } diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index e2e4937..ce7f5e4 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -20,14 +20,51 @@ #include <arch/acpi.h> #include <arch/acpigen.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <types.h> #include <string.h> #include <baytrail/acpi.h> #include <baytrail/iomap.h> +#include <baytrail/irq.h> #include <baytrail/pmc.h> +static int acpi_sci_irq(void) +{ + const unsigned long actl = ILB_BASE_ADDRESS + ACTL; + int scis; + static int sci_irq; + + if (sci_irq) + return sci_irq; + + /* Determine how SCI is routed. */ + scis = read32(actl) & SCIS_MASK; + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +} + void acpi_create_intel_hpet(acpi_hpet_t * hpet) { acpi_header_t *header = &(hpet->header); @@ -70,7 +107,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = 0x9; + fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; @@ -175,3 +212,25 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci_irq = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci_irq >= 20) + sci_flags |= MP_IRQ_POLARITY_LOW; + else + sci_flags |= MP_IRQ_POLARITY_HIGH; + + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, + sci_flags); + + return current; +} diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h index bfb7d40..da5f406 100644 --- a/src/soc/intel/baytrail/baytrail/acpi.h +++ b/src/soc/intel/baytrail/baytrail/acpi.h @@ -24,6 +24,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); +unsigned long acpi_madt_irq_overrides(unsigned long current); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h index d037b89..6461878 100644 --- a/src/soc/intel/baytrail/baytrail/irq.h +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -52,6 +52,17 @@ #define PIRQG 6 #define PIRQH 7 +/* These registers live behind the ILB_BASE_ADDRESS */ +#define ACTL 0x00 +# define SCIS_MASK 0x07 +# define SCIS_IRQ9 0x00 +# define SCIS_IRQ10 0x01 +# define SCIS_IRQ11 0x02 +# define SCIS_IRQ20 0x04 +# define SCIS_IRQ21 0x05 +# define SCIS_IRQ22 0x06 +# define SCIS_IRQ23 0x07 + /* In each mainbaord directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 10c0b89..b7cf4e5 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -122,6 +122,7 @@ static void sc_init(device_t dev) int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const unsigned long actl = ILB_BASE_ADDRESS + ACTL; const struct baytrail_irq_route *ir = &global_baytrail_irq_route; /* Set up the PIRQ PIC routing based on static config. */ @@ -132,6 +133,9 @@ static void sc_init(device_t dev) for (i = 0; i < NUM_IR_DEVS; i++) { write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); } + + /* Route SCI to IRQ9 */ + write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); } /*

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New patch to review for coreboot: 6b656a2 southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
by Edward O'Callaghan 06 May '14

06 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5669 -gerrit commit 6b656a2ffcba2ceae130d629bdae0a1a48c5def6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 23:53:09 2014 +1000 southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge NOTFORMERGE We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/romstage.c | 10 ---------- src/mainboard/amd/inagua/romstage.c | 10 ---------- src/mainboard/amd/olivehill/romstage.c | 9 --------- src/mainboard/amd/parmer/romstage.c | 10 ---------- src/mainboard/amd/persimmon/romstage.c | 10 ---------- src/mainboard/amd/thatcher/romstage.c | 10 ---------- src/mainboard/amd/torpedo/romstage.c | 13 ------------- src/mainboard/asrock/e350m1/romstage.c | 10 ---------- src/mainboard/asrock/imb-a180/romstage.c | 9 --------- src/mainboard/asus/f2a85-m/romstage.c | 10 ---------- src/mainboard/gizmosphere/gizmo/romstage.c | 10 ---------- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 11 ----------- src/mainboard/lippert/frontrunner-af/romstage.c | 10 ---------- src/mainboard/lippert/toucan-af/romstage.c | 10 ---------- src/mainboard/supermicro/h8scm/romstage.c | 10 ---------- src/mainboard/tyan/s8226/romstage.c | 4 ---- src/southbridge/amd/sb600/lpc.c | 5 +++++ src/southbridge/amd/sb700/lpc.c | 6 ++++++ src/southbridge/amd/sb800/lpc.c | 5 +++++ 19 files changed, 16 insertions(+), 156 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 776ecd5..8ed1398 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -32,8 +32,6 @@ #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "nb_cimx.h" #include <sb_cimx.h> #include "Platform.h" @@ -140,14 +138,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 98c74d6..a304d31 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -35,8 +35,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -112,14 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 6422393..73cd40a 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -160,13 +158,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index a5d041f..668dfc8 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -141,14 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 47c03ec..9ba34e7 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,8 +35,6 @@ #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -170,14 +168,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 9c3cf5b..1a7a399 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -35,8 +35,6 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "src/superio/smsc/lpc47n217/early_serial.c" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) @@ -158,14 +156,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 58b88d0..dcab52b 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -32,8 +32,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> @@ -112,17 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - printk(BIOS_DEBUG, "setup_i8259\n"); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - printk(BIOS_DEBUG, "setup_i8254\n"); - setup_i8254(); - - post_code(0x43); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index ba2e34d..2913c08 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -35,8 +35,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -115,14 +113,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 59d95f9..5b64cf9 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" #include "superio/winbond/w83627uhg/early_serial.c" @@ -184,13 +182,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 4aa4b04..ae26b32 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -37,8 +37,6 @@ #include <stdint.h> #include <string.h> /* TODO: remove .c includes */ -#include <drivers/pc80/i8254.c> -#include <drivers/pc80/i8259.c> #include <superio/ite/it8712f/early_serial.c> #define MMIO_NON_POSTED_START 0xfed00000 @@ -198,14 +196,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index f639d1f..11ae623 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,8 +33,6 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -178,14 +176,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 24751f4..2be2bc5 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -34,9 +34,6 @@ #include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -139,14 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 16fb8ab..cf5c566 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -173,14 +171,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 93ff521..accf381 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -35,8 +35,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -174,14 +172,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 0f5abdf..e7a1c4c 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -31,8 +31,6 @@ #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "superio/nuvoton/wpcm450/wpcm450.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -122,14 +120,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index fc239e4..f4befe6 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -33,8 +33,6 @@ #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -133,8 +131,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n"); post_code(0x51); - setup_i8259 (); - setup_i8254 (); copy_and_run(); /* We will not return, Should never see this message and post code. */ diff --git a/src/southbridge/amd/sb600/lpc.c b/src/southbridge/amd/sb600/lpc.c index 7ef49d1..baf6ceb 100644 --- a/src/southbridge/amd/sb600/lpc.c +++ b/src/southbridge/amd/sb600/lpc.c @@ -25,6 +25,8 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <arch/io.h> #include <arch/ioapic.h> #include "sb600.h" @@ -60,6 +62,9 @@ static void lpc_init(device_t dev) pci_write_config8(dev, 0x78, byte); rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ } static void sb600_lpc_read_resources(device_t dev) diff --git a/src/southbridge/amd/sb700/lpc.c b/src/southbridge/amd/sb700/lpc.c index a175210..5f3da2a 100644 --- a/src/southbridge/amd/sb700/lpc.c +++ b/src/southbridge/amd/sb700/lpc.c @@ -25,6 +25,8 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <arch/io.h> #include <arch/ioapic.h> #include <cbmem.h> @@ -82,6 +84,10 @@ static void lpc_init(device_t dev) #endif rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + } void backup_top_of_ram(uint64_t ramtop) diff --git a/src/southbridge/amd/sb800/lpc.c b/src/southbridge/amd/sb800/lpc.c index 12fd96f..b6d717c 100644 --- a/src/southbridge/amd/sb800/lpc.c +++ b/src/southbridge/amd/sb800/lpc.c @@ -25,6 +25,8 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <pc80/isa-dma.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <arch/io.h> #include "sb800.h" @@ -68,6 +70,9 @@ static void lpc_init(device_t dev) pci_write_config8(dev, 0xBB, byte); rtc_check_update_cmos_date(RTC_HAS_ALTCENTURY); + + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ } static void sb800_lpc_read_resources(device_t dev)

1 0

New patch to review for coreboot: e78960e superio/ite/it8728f: RAMstage PNP configuration component
by Edward O'Callaghan 06 May '14

06 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5668 -gerrit commit e78960e4db8771cef9f51acafd989623441f4a5d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 18:00:07 2014 +1000 superio/ite/it8728f: RAMstage PNP configuration component Provide devicetree.cb RAMstage configuration of this superio component. Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8728f/Makefile.inc | 2 + src/superio/ite/it8728f/chip.h | 34 +++++++++++++ src/superio/ite/it8728f/it8728f_hwm.c | 80 ++++++++++++++++++++++++++++++ src/superio/ite/it8728f/it8728f_internal.h | 28 +++++++++++ src/superio/ite/it8728f/superio.c | 69 ++++++++++++++++++++++++++ 5 files changed, 213 insertions(+) diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc index d8d4f6a..a146db8 100644 --- a/src/superio/ite/it8728f/Makefile.inc +++ b/src/superio/ite/it8728f/Makefile.inc @@ -19,3 +19,5 @@ ## romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += it8728f_hwm.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c diff --git a/src/superio/ite/it8728f/chip.h b/src/superio/ite/it8728f/chip.h new file mode 100644 index 0000000..998685f --- /dev/null +++ b/src/superio/ite/it8728f/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_CHIP_H +#define SUPERIO_ITE_IT8728F_CHIP_H + +struct superio_ite_it8728f_config { + /* HWM configuration registers */ + uint8_t hhwm_ctl_register; + uint8_t hhwm_main_ctl_register; + uint8_t hhwm_adc_temp_chan_en_reg; + uint8_t hhwm_fan1_ctl_pwm; + uint8_t hhwm_fan2_ctl_pwm; + uint8_t hhwm_fan3_ctl_pwm; +}; + +#endif /* SUPERIO_ITE_IT8728F_CHIP_H */ diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c new file mode 100644 index 0000000..01eae2a --- /dev/null +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "ite_internal.h" + +/* + * FAN controller configuration register index's + */ +#define HWM_MAIN_CTL_REG 0x13 /* default 0x07 */ +#define HWM_CTL_REG 0x14 /* default 0x40 */ +#define HWM_FAN1_CTL_PWM 0x15 /* default 0x00 */ +#define HWM_FAN2_CTL_PWM 0x16 /* default 0x00 */ +#define HWM_FAN3_CTL_PWM 0x17 /* default 0x00 */ +#define HWM_ADC_TEMP_CHAN_EN_REG 0x51 /* default 0x00 */ + +static void pnp_write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +void it8728f_ec_init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + u16 port = res->base; + + printk(BIOS_INFO, + "ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n"); + printk(BIOS_DEBUG, + "ITE IT8728F Super I/O HWM: Base Address at 0x%x\n", port); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + /* ITE IT8728F HWM (ordered) programming sequence. */ + + /* configure fan polarity */ + pnp_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register); + + /* enable fans 1-3 */ + pnp_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register); + + /* enable termistor temps for temp1-temp3 */ + pnp_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg); + + /* configure which fanX uses which tempY */ + pnp_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm); + pnp_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm); + pnp_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/ite/it8728f/it8728f_internal.h b/src/superio/ite/it8728f/it8728f_internal.h new file mode 100644 index 0000000..ece41b9 --- /dev/null +++ b/src/superio/ite/it8728f/it8728f_internal.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_INTERNAL_H +#define SUPERIO_ITE_IT8728F_INTERNAL_H + +#include <device/device.h> + +void hwm_init(device_t dev); + +#endif /* SUPERIO_ITE_IT8728F_INTERNAL_H */ diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c new file mode 100644 index 0000000..45aea0f --- /dev/null +++ b/src/superio/ite/it8728f/superio.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> + +#include "chip.h" +#include "it8728f.h" +#include "it8728f_internal.h" + +static void it8728f_init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case IT8728F_EC: + it8728f_ec_init(dev); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8728f_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +/* TODO: incomplete */ +static struct pnp_info pnp_dev_info[] = { + { &ops, IT8728F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8728f_ops = { + CHIP_NAME("ITE IT8728F Super I/O") + .enable_dev = enable_dev +};

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Patch set updated for coreboot: a0c5cc0 superio/common/conf_mode: Provide another common pnp entry/exit
by Edward O'Callaghan 06 May '14

06 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5666 -gerrit commit a0c5cc065c5a403e22354ec470e2dc1fb138b93c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 17:24:59 2014 +1000 superio/common/conf_mode: Provide another common pnp entry/exit ITE Super I/O's make use of this method to enter and exit in and out of their PNP configuration. Provide functions for use in ram stage component. Change-Id: I2b546c2b17eefc89aaab4982192f5e9a15a16c2f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/include/superio/conf_mode.h | 5 ++++- src/superio/common/conf_mode.c | 24 ++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/include/superio/conf_mode.h b/src/include/superio/conf_mode.h index b93b889..c49cae7 100644 --- a/src/include/superio/conf_mode.h +++ b/src/include/superio/conf_mode.h @@ -27,8 +27,11 @@ void pnp_enter_conf_mode_55(device_t dev); void pnp_enter_conf_mode_8787(device_t dev); void pnp_exit_conf_mode_aa(device_t dev); +void pnp_enter_conf_mode_870155aa(device_t dev); +void pnp_exit_conf_mode_0202(device_t dev); extern const struct pnp_mode_ops pnp_conf_mode_55_aa; extern const struct pnp_mode_ops pnp_conf_mode_8787_aa; +extern const struct pnp_mode_ops pnp_conf_mode_870155_aa; -#endif +#endif /* DEVICE_PNP_CONF_MODE_H */ diff --git a/src/superio/common/conf_mode.c b/src/superio/common/conf_mode.c index 40583ff..f3e6277 100644 --- a/src/superio/common/conf_mode.c +++ b/src/superio/common/conf_mode.c @@ -39,6 +39,25 @@ void pnp_exit_conf_mode_aa(device_t dev) outb(0xaa, dev->path.pnp.port); } +void pnp_enter_conf_mode_870155aa(device_t dev) +{ + outb(0x87, dev->path.pnp.port); + outb(0x01, dev->path.pnp.port); + outb(0x55, dev->path.pnp.port); + + if (dev->path.pnp.port == 0x4e) + outb(0xaa, dev->path.pnp.port); + else + outb(0x55, dev->path.pnp.port); +} + +void pnp_exit_conf_mode_0202(device_t dev) +{ + outb(0x02, dev->path.pnp.port); + outb(0x02, dev->path.pnp.port + 1); +} + + const struct pnp_mode_ops pnp_conf_mode_55_aa = { .enter_conf_mode = pnp_enter_conf_mode_55, .exit_conf_mode = pnp_exit_conf_mode_aa, @@ -48,3 +67,8 @@ const struct pnp_mode_ops pnp_conf_mode_8787_aa = { .enter_conf_mode = pnp_enter_conf_mode_8787, .exit_conf_mode = pnp_exit_conf_mode_aa, }; + +const struct pnp_mode_ops pnp_conf_mode_870155_aa = { + .enter_conf_mode = pnp_enter_conf_mode_870155aa, + .exit_conf_mode = pnp_exit_conf_mode_0202, +};

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Patch merged into coreboot/master: 2237324 lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 2237324e77a5e8ed30878609095c1592081f15e4 Author: Trevor Mosey <uberushaximus(a)gmail.com> Date: Fri May 2 20:07:03 2014 -0500 lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String linux/drivers/platform/x86/thinkpad_acpi.c looks for an EC version string before loading, this code copies the vendor BIOS by exposing this string. This was originally part of x60's mainboard.c Change-Id: I5e54ea2833252bc4dbba46ceb67d78c435b34845 Signed-off-by: Trevor Mosey <uberushaximus(a)gmail.com> Reviewed-on: http://review.coreboot.org/5638 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5638 for details. -gerrit

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Patch set updated for coreboot: 9aa65be cpu/samsung/exynos5250/cpu.c: Remove unused variable `ret`
by Paul Menzel 06 May '14

06 May '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4594 -gerrit commit 9aa65be0732b407b0b769fda8ca48a4681e6ce5e Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Jan 1 14:37:33 2014 +0100 cpu/samsung/exynos5250/cpu.c: Remove unused variable `ret` CC cpu/samsung/exynos5250/cpu.ramstage.o src/cpu/samsung/exynos5250/cpu.c: In function 'exynos_displayport_init': src/cpu/samsung/exynos5250/cpu.c:88:6: error: variable 'ret' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors Change-Id: I72a5a802aef0a75b0277eaac6ca6c24793812d98 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/samsung/exynos5250/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 2354be1..1b4e130 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -85,7 +85,6 @@ static void set_cpu_id(void) static void exynos_displayport_init(device_t dev, u32 lcdbase, unsigned long fb_size) { - int ret; struct cpu_samsung_exynos5250_config *conf = dev->chip_info; /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. @@ -131,7 +130,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase, printk(BIOS_DEBUG, "Initializing Exynos LCD.\n"); - ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); + lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_enable(device_t dev)

1 0

Patch merged into coreboot/master: 69634c3 northbridge/intel/sandybridge/pei_data.h: Fix typo in hig*h*est in comment
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 69634c316ed1056e734a129e7c28580c2772c074 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue May 6 12:45:25 2014 +0200 northbridge/intel/sandybridge/pei_data.h: Fix typo in hig*h*est in comment Change-Id: I0daf5d1d446de1f09b695f177b0491301613e278 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/5667 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5667 for details. -gerrit

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