coreboot-gerrit May 2014

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Patch set updated for coreboot: fb4f375 baytrail: Add ACPI CPU entries
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4954 -gerrit commit fb4f37562a8bc8b729361d9f1f189ea885a67e2b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Nov 5 13:02:30 2013 -0800 baytrail: Add ACPI CPU entries - C-state table based on static config MWAIT values are from ref code for non-S0ix config C6 substate 8 is ignored by the kernel as it violates the CPUID but it is left in as the other substate may not work. - P-state table generated with proper ratio and VID values relies on having the package power msr set to magic value as the power-on default is wrong - T-state table uses static table BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175742 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/acpi.c | 245 ++++++++++++++++++++++++++++++ src/soc/intel/baytrail/acpi/globalnvs.asl | 1 + src/soc/intel/baytrail/baytrail/nvs.h | 3 +- src/soc/intel/baytrail/placeholders.c | 2 - 4 files changed, 248 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index ce7f5e4..1f358f4 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -24,14 +24,56 @@ #include <arch/smp/mpspec.h> #include <console/console.h> #include <cpu/x86/smm.h> +#include <console/console.h> #include <types.h> #include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cpu/intel/turbo.h> #include <baytrail/acpi.h> #include <baytrail/iomap.h> #include <baytrail/irq.h> +#include <baytrail/msr.h> +#include <baytrail/pattrs.h> #include <baytrail/pmc.h> +#define MWAIT_RES(state, sub_state) \ + { \ + .addrl = (((state) << 4) | (sub_state)), \ + .space_id = ACPI_ADDRESS_SPACE_FIXED, \ + .bit_width = ACPI_FFIXEDHW_VENDOR_INTEL, \ + .bit_offset = ACPI_FFIXEDHW_CLASS_MWAIT, \ + .access_size = ACPI_FFIXEDHW_FLAG_HW_COORD, \ + } + +/* C-state map without S0ix */ +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = MWAIT_RES(0, 0), + }, + { + /* C6NS with no L2 shrink */ + /* NOTE: this substate is above CPUID limit */ + .ctype = 2, /* ACPI C2 */ + .latency = 500, + .power = 10, + .resource = MWAIT_RES(5, 8), + }, + { + /* C6FS with full L2 shrink */ + .ctype = 3, /* ACPI C3 */ + .latency = 1500, /* 1.5ms worst case */ + .power = 10, + .resource = MWAIT_RES(5, 2), + } +}; + static int acpi_sci_irq(void) { const unsigned long actl = ILB_BASE_ADDRESS + ACTL; @@ -210,7 +252,210 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.resv = 0; fadt->x_gpe1_blk.addrl = 0x0; fadt->x_gpe1_blk.addrh = 0x0; +} + +static acpi_tstate_t baytrail_tss_table[] = { + { 100, 1000, 0, 0x00, 0 }, + { 88, 875, 0, 0x1e, 0 }, + { 75, 750, 0, 0x1c, 0 }, + { 63, 625, 0, 0x1a, 0 }, + { 50, 500, 0, 0x18, 0 }, + { 38, 375, 0, 0x16, 0 }, + { 25, 250, 0, 0x14, 0 }, + { 13, 125, 0, 0x12, 0 }, +}; + +static int generate_T_state_entries(int core, int cores_per_package) +{ + int len; + + /* Indicate SW_ALL coordination for T-states */ + len = acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + len += acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + len += acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + len += acpigen_write_TSS_package( + ARRAY_SIZE(baytrail_tss_table), baytrail_tss_table); + + return len; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static int generate_P_state_entries(int core, int cores_per_package) +{ + int len, len_pss; + int ratio_min, ratio_max, ratio_turbo, ratio_step, ratio_range_2; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + int vid, vid_turbo, vid_min, vid_max, vid_range_2; + u32 control_status; + const struct pattrs *pattrs = pattrs_get(); + msr_t msr; + + /* Inputs from CPU attributes */ + ratio_max = pattrs->iacore_ratios[IACORE_MAX]; + ratio_min = pattrs->iacore_ratios[IACORE_LFM]; + vid_max = pattrs->iacore_vids[IACORE_MAX]; + vid_min = pattrs->iacore_vids[IACORE_LFM]; + + /* Hardware coordination of P-states */ + coord_type = HW_ALL; + + /* Max Non-Turbo Frequency */ + clock_max = (ratio_max * pattrs->bclk_khz) / 1000; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 1 << (msr.lo & 0xf); + msr = rdmsr(MSR_PKG_POWER_LIMIT); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + len = acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + len += acpigen_write_PPC(0); + + /* Write PSD indicating configured coordination type */ + len += acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + len += acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = 1; + num_entries = (ratio_max - ratio_min) / ratio_step; + while (num_entries > 15) { /* ACPI max is 15 ratios */ + ratio_step <<= 1; + num_entries >>= 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + len_pss = acpigen_write_package(num_entries + 2); + + ratio_turbo = pattrs->iacore_ratios[IACORE_TURBO]; + vid_turbo = pattrs->iacore_vids[IACORE_TURBO]; + control_status = (ratio_turbo << 8) | vid_turbo; + + /* Add entry for Turbo ratio */ + len_pss += acpigen_write_PSS_package( + clock_max + 1, /*MHz*/ + power_max, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control*/ + control_status); /*status*/ + } else { + /* _PSS package count without Turbo */ + len_pss = acpigen_write_package(num_entries + 1); + ratio_turbo = ratio_max; + vid_turbo = vid_max; + } + + /* First regular entry is max non-turbo ratio */ + control_status = (ratio_max << 8) | vid_max; + len_pss += acpigen_write_PSS_package( + clock_max, /*MHz*/ + power_max, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control */ + control_status); /*status*/ + + /* Set up ratio and vid ranges for VID calculation */ + ratio_range_2 = (ratio_turbo - ratio_min) * 2; + vid_range_2 = (vid_turbo - vid_min) * 2; + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate VID for this ratio */ + vid = ((ratio - ratio_min) * vid_range_2) / + ratio_range_2 + vid_min; + /* Round up if remainder */ + if (((ratio - ratio_min) * vid_range_2) % ratio_range_2) + vid++; + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = (ratio * pattrs->bclk_khz) / 1000; + control_status = (ratio << 8) | (vid & 0xff); + + len_pss += acpigen_write_PSS_package( + clock, /*MHz*/ + power, /*mW*/ + 10, /*lat1*/ + 10, /*lat2*/ + control_status, /*control*/ + control_status); /*status*/ + } + + /* Fix package length */ + len_pss--; + acpigen_patch_len(len_pss); + + return len + len_pss; +} + +void generate_cpu_entries(void) +{ + int len_pr, core; + int pcontrol_blk = get_pmbase(), plen = 6; + const struct pattrs *pattrs = pattrs_get(); + + for (core=0; core<pattrs->num_cpus; core++) { + if (core > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + len_pr = acpigen_write_processor( + core, pcontrol_blk, plen); + + /* Generate P-state tables */ + len_pr += generate_P_state_entries( + core, pattrs->num_cpus); + + /* Generate C-state tables */ + len_pr += acpigen_write_CST_package( + cstate_map, ARRAY_SIZE(cstate_map)); + + /* Generate T-state tables */ + len_pr += generate_T_state_entries( + core, pattrs->num_cpus); + + len_pr--; + acpigen_patch_len(len_pr); + } } unsigned long acpi_madt_irq_overrides(unsigned long current) diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 37a234c..2f614a9 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -50,6 +50,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PWRS, 8, // 0x10 - Power State (AC = 1) PCNT, 8, // 0x11 - Processor count TPMP, 8, // 0x12 - TPM Present and Enabled + TLVL, 8, // 0x13 - Throttle Level /* Device Config */ Offset (0x20), diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index e261e7c..aed0974 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -36,7 +36,8 @@ typedef struct { u8 pwrs; /* 0x10 - Power state (AC = 1) */ u8 pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ - u8 rsvd1[13]; + u8 tlvl; /* 0x13 - Throttle Level */ + u8 rsvd1[12]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ diff --git a/src/soc/intel/baytrail/placeholders.c b/src/soc/intel/baytrail/placeholders.c index b10b7e6..9e1413d 100644 --- a/src/soc/intel/baytrail/placeholders.c +++ b/src/soc/intel/baytrail/placeholders.c @@ -5,8 +5,6 @@ #include <baytrail/acpi.h> -void generate_cpu_entries(void) {} - void smm_init(void) {} /* Rmodules don't like weak symbols. */

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Patch set updated for coreboot: d28ad53 baytrail: gpio: Add support for direct / dedicated IRQs
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4962 -gerrit commit d28ad53078c3b21a0b43f17f421de15f7e498905 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Nov 8 16:43:34 2013 -0800 baytrail: gpio: Add support for direct / dedicated IRQs Add support for DirectIRQ / dedicated IRQs. This consists of up to 16 IRQs for both SCORE and SSUS banks. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ regwrites w/ GPIO_DEBUG look correct. Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c Reviewed-on: https://chromium-review.googlesource.com/176165 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 34 ++++++++++++++++++++++++++++ src/soc/intel/baytrail/baytrail/irq.h | 41 +++++++++++++++++++++++++++++++--- src/soc/intel/baytrail/gpio.c | 25 +++++++++++++++++++++ 3 files changed, 97 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index 8c90c89..154ac84 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -31,6 +31,9 @@ #define GPNCORE_PAD_BASE (IO_BASE_ADDRESS + 0x1000) #define GPSSUS_PAD_BASE (IO_BASE_ADDRESS + 0x2000) +/* DIRQ registers start at pad base + 0x980 */ +#define PAD_BASE_DIRQ_OFFSET 0x980 + /* Pad register offset */ #define PAD_CONF0_REG 0x0 #define PAD_CONF1_REG 0x4 @@ -77,6 +80,12 @@ /* config0[27] - Direct Irq En */ #define PAD_IRQ_EN (1 << 27) +/* config0[26] - gd_tne */ +#define PAD_TNE_IRQ (1 << 26) + +/* config0[25] - gd_tpe */ +#define PAD_TPE_IRQ (1 << 25) + /* config0[24] - Gd Level */ #define PAD_LEVEL_IRQ (1 << 24) #define PAD_EDGE_IRQ (0 << 24) @@ -169,6 +178,26 @@ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } +/* Direct / dedicated IRQ input - falling-edge triggered */ +#define GPIO_DIRQ \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = GPIO_NEDGE_ENABLE } + +/* Direct / dedicated IRQ input - rising-edge triggered */ +#define GPIO_DIRQ_INVERT \ + { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_INPUT_ENABLE, \ + .use_sel = GPIO_USE_LEGACY, \ + .io_sel = GPIO_DIR_INPUT, \ + .tne = GPIO_PEDGE_ENABLE } + #define GPIO_OUT_LOW \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ @@ -236,6 +265,9 @@ #define GPIO_NC GPIO_INPUT_PU_10K #define GPIO_DEFAULT GPIO_FUNC0 +/* 16 DirectIRQs per supported bank */ +#define GPIO_MAX_DIRQS 16 + struct soc_gpio_map { u32 pad_conf0; u32 pad_conf1; @@ -253,6 +285,8 @@ struct soc_gpio_config { const struct soc_gpio_map *ncore; const struct soc_gpio_map *score; const struct soc_gpio_map *ssus; + const u8 (*core_dirq)[GPIO_MAX_DIRQS]; + const u8 (*sus_dirq)[GPIO_MAX_DIRQS]; }; /* Description of GPIO 'bank' ex. {ncore, score. ssus} */ diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h index 2359d21..f1abae7 100644 --- a/src/soc/intel/baytrail/baytrail/irq.h +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -50,9 +50,44 @@ #define SCC_EMMC_IRQ 45 #define SCC_SDIO_IRQ 46 #define SCC_SD_IRQ 47 -/* The dedicated gpio irqs are active high. */ -#define GPIO_S0_DED_IRQ(slot) (51 + (slot)) -#define GPIO_S5_DED_IRQ(slot) (67 + (slot)) +/* GPIO direct / dedicated IRQs. */ +#define GPIO_S0_DED_IRQ_0 51 +#define GPIO_S0_DED_IRQ_1 52 +#define GPIO_S0_DED_IRQ_2 53 +#define GPIO_S0_DED_IRQ_3 54 +#define GPIO_S0_DED_IRQ_4 55 +#define GPIO_S0_DED_IRQ_5 56 +#define GPIO_S0_DED_IRQ_6 57 +#define GPIO_S0_DED_IRQ_7 58 +#define GPIO_S0_DED_IRQ_8 59 +#define GPIO_S0_DED_IRQ_9 60 +#define GPIO_S0_DED_IRQ_10 61 +#define GPIO_S0_DED_IRQ_11 62 +#define GPIO_S0_DED_IRQ_12 63 +#define GPIO_S0_DED_IRQ_13 64 +#define GPIO_S0_DED_IRQ_14 65 +#define GPIO_S0_DED_IRQ_15 66 +#define GPIO_S5_DED_IRQ_0 67 +#define GPIO_S5_DED_IRQ_1 68 +#define GPIO_S5_DED_IRQ_2 69 +#define GPIO_S5_DED_IRQ_3 70 +#define GPIO_S5_DED_IRQ_4 71 +#define GPIO_S5_DED_IRQ_5 72 +#define GPIO_S5_DED_IRQ_6 73 +#define GPIO_S5_DED_IRQ_7 74 +#define GPIO_S5_DED_IRQ_8 75 +#define GPIO_S5_DED_IRQ_9 76 +#define GPIO_S5_DED_IRQ_10 77 +#define GPIO_S5_DED_IRQ_11 78 +#define GPIO_S5_DED_IRQ_12 79 +#define GPIO_S5_DED_IRQ_13 80 +#define GPIO_S5_DED_IRQ_14 81 +#define GPIO_S5_DED_IRQ_15 82 +/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL. */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) /* PIC IRQ settings. */ #define PIRQ_PIC_IRQDISABLE 0x0 diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 824ed65..8cc7cc0 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -179,6 +179,25 @@ static void setup_gpio_route(const struct soc_gpio_map *sus, southcluster_smm_save_gpio_route(route_reg); } +static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS], + const struct gpio_bank *bank) +{ + u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET; + u32 val; + int i; + + /* Write all four DIRQ registers */ + for (i=0; i<4; ++i) { + val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 | + dirq[i * 4 + 1] << 8 | dirq[i * 4]; + write32(reg + i * 4, val); +#ifdef GPIO_DEBUG + printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n", + reg + i * 4, val); +#endif + } +} + void setup_soc_gpios(struct soc_gpio_config *config) { if (config) { @@ -186,7 +205,13 @@ void setup_soc_gpios(struct soc_gpio_config *config) setup_gpios(config->score, &gpscore_bank); setup_gpios(config->ssus, &gpssus_bank); setup_gpio_route(config->ssus, config->score); + + if (config->core_dirq) + setup_dirqs(*config->core_dirq, &gpscore_bank); + if (config->sus_dirq) + setup_dirqs(*config->sus_dirq, &gpssus_bank); } + } struct soc_gpio_config* __attribute__((weak)) mainboard_get_gpios(void)

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Patch set updated for coreboot: c054421 rambi: enable SCI and SMI gpios
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4960 -gerrit commit c054421c677f26288b431d22f6be2fdf9b34b9a3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 11 14:58:06 2013 -0600 rambi: enable SCI and SMI gpios Rambi has 3 pins that need to be configured for SCI and SMI: 1. GPIO_CORE[0] - runtime SCI pin 2. GPIO_SUS[7] - SMI for firmware lid events 3. GPIO_SUS[0] - wake pin for S3 wakes from EC. Configure these pins now that the rest of the infrastructure is in place. The one thing that is yet to work is runtime SCI for lid events once booted. BUG=chrome-os-partner:23505 BRANCH=None TEST=built and booted. lid close at rec screen works. And wake from S3 with a keyboard press works. Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176393 --- src/mainboard/google/rambi/gpio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index ad1da09..9bcafad 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -55,7 +55,7 @@ static const struct soc_gpio_map gpncore_gpio_map[] = { /* SCORE GPIOs */ static const struct soc_gpio_map gpscore_gpio_map[] = { - GPIO_INPUT, /* S0_SC000 - SOC_KBC_SCI - INT */ + GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */ GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */ GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */ GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */ @@ -105,7 +105,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ - GPIO_FUNC1, /* S0-SC050 - IRQ_SERIRQ */ + GPIO_FUNC(1, PULL_UP, 10K), /* S0-SC050 - IRQ_SERIRQ */ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ @@ -162,14 +162,14 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { /* SSUS GPIOs */ static const struct soc_gpio_map gpssus_gpio_map[] = { - GPIO_NC, /* S500 - PCH_WAKE# (NC) */ + GPIO_ACPI_SCI, /* S500 - PCH_WAKE# */ GPIO_FUNC6, /* S501 - TRACKPAD_INT# - INT */ GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ - GPIO_INPUT, /* S507 - SOC_KBC_SMI - INT */ + GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */ GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */

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Patch set updated for coreboot: edfdae1 rambi: disable HDA device
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4961 -gerrit commit edfdae1b94d6cbb44b3c724735f8902651a6e0c6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 11 15:01:39 2013 -0600 rambi: disable HDA device For some reason HDA can now be disabled. It's unclear what changes in the baytrail code allowed this to happen, sadly. BUG=chrome-os-partner:22871 BRANCH=None TEST=Noted hda is not in lspci. Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176394 --- src/mainboard/google/rambi/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index a5fe37e..88785c0 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -44,7 +44,7 @@ chip soc/intel/baytrail device pci 18.6 on end # I2C6 device pci 18.7 off end # I2C7 device pci 1a.0 on end # TXE - device pci 1b.0 on end # HDA + device pci 1b.0 off end # HDA device pci 1c.0 on end # PCIE_PORT1 device pci 1c.1 on end # PCIE_PORT2 device pci 1c.2 off end # PCIE_PORT3

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Patch merged into coreboot/master: 05a3393 baytrail: Enable Turbo/Burst and set some magic MSRs
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 05a3393a2c089d0c7ad7443e2298dacd129fadb3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Nov 5 12:59:50 2013 -0800 baytrail: Enable Turbo/Burst and set some magic MSRs As far as I can tell turbo enabling behaves like it did on haswell so use the standard code. There are also some magic values to set in some magic MSRs related to turbo and package power so they report correctly. The L2 cache shrink is enabled and a threshold is set that makes both dual and quad core happy. C1E is disabled to match the reference code. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: Ic6d4283d480a44d85a9b96571baf83928615665c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175743 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4952 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4952 for details. -gerrit

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Patch merged into coreboot/master: fd461e3 regscript: Add support for MSR type
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit fd461e396b482cd5d0cd81cb11c4973f4ebfa94c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 8 23:00:24 2013 -0800 regscript: Add support for MSR type This required changing value/mask types to uint64_t. Another option would be to use id field to select low or high 32 bits of the MSR and set them independently. BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi Change-Id: Ied9998058a8035bf3f003185236f3be3e0df7fc9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176304 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4951 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4951 for details. -gerrit

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Patch merged into coreboot/master: 9e68fe6 rambi: include the EC devices normally on superio
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 9e68fe68ff272619ead17d8497fc6050e28caac6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 08:13:58 2013 -0600 rambi: include the EC devices normally on superio The superio.asl file allows for the mainboard to hang devices off of the LPC bus in ACPI. Include the keyboard controller, EC memory map, and host interface's resources. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted resource reservations in dmesg. Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176134 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4950 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4950 for details. -gerrit

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Patch merged into coreboot/master: ab7ed05 baytrail: include mainboard's superio.asl
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit ab7ed054bee3ede51c06053adf53d455fda6065a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 14:33:21 2013 -0600 baytrail: include mainboard's superio.asl The mainboard needs an opportunity to hang devices off of the LPC device. Therefore, provide this opportunity for the mainboard. BUG=chrome-os-partner:23505 BRANCH=None TEST=Buit and booted with keyboard. Keys work. Change-Id: Ie2b660ad43e86d9237b0b0bb0720b069670bc537 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176133 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4949 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4949 for details. -gerrit

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Patch merged into coreboot/master: 84da959 rambi: update EC support
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 84da959c691a1efa87ff47edd03d5427eaf6e093 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 11:19:34 2013 -0600 rambi: update EC support Fix the SMI and SCI gpios for Rambi. Also, add in the EC callbacks for the SMI handler. Note that the handler for GPI SMIs has not been tested yet as baytrail chipset code doesn't yet support setting up those configurations yet. BUG=chrome-os-partner:23505 BRANCH=None TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts for the EC's SCI GPI. Also was able to see Chrome EC messages with CONFIG_DEBUG_SMI and powering down at the dev screen. Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176077 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4948 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4948 for details. -gerrit

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Patch merged into coreboot/master: fa91e02 baytrail: add more irq defintions
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit fa91e02a15ff45f70886b969a9587468afec10ac Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 10:47:01 2013 -0600 baytrail: add more irq defintions The IRQs used for devices that are in acpi mode are added as well as the IRQ defitions for the dedicated GPIO IRQ routing. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built. Change-Id: I2eed5a4584e2d908c32617c9289a2abeaa30bd44 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176120 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4947 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4947 for details. -gerrit

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coreboot-gerrit May 2014