coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 99ac98f Introduce stage-specific architecture for coreboot
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 99ac98f7e1fa30d3fb33cc5486e6af46b4bef56e Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Apr 23 10:18:48 2014 -0700 Introduce stage-specific architecture for coreboot Make all three coreboot stages (bootblock, romstage and ramstage) aware of the architecture specific to that stage i.e. we will have CONFIG_ARCH variables for each of the three stages. This allows us to have an SOC with any combination of architectures and thus every stage can be made to run on a completely different architecture independent of others. Thus, bootblock can have an x86 arch whereas romstage and ramstage can have arm32 and arm64 arch respectively. These stage specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain and compiler flags for every stage. These options can be considered as either arch or modes eg: x86 running in different modes or ARM having different arch types (v4, v7, v8). We have got rid of the original CONFIG_ARCH option completely as every stage can have any architecture of its own. Thus, almost all the components of coreboot are identified as being part of one of the three stages (bootblock, romstage or ramstage). The components which cannot be classified as such e.g. smm, rmodules can have their own compiler toolset which is for now set to *_i386. Hence, all special classes are treated in a similar way and the compiler toolset is defined using create_class_compiler defined in Makefile. In order to meet these requirements, changes have been made to CC, LD, OBJCOPY and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others. Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the toolsets are defined using create_class_compiler. Few additional macros have been introduced to identify the class to be used at various points, e.g.: CC_$(class) derives the $(class) part from the name of the stage being compiled. We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER as they do not make any sense for coreboot as a whole. All these attributes are associated with each of the stages. Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: http://review.coreboot.org/5577 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)gmail.com> See http://review.coreboot.org/5577 for details. -gerrit

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Patch set updated for coreboot: 7afb088 baytrail: don't allow PCIE wake ups
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4972 -gerrit commit 7afb088cd94dd538dc77fbe66b327addf627096d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 14 11:06:17 2013 -0600 baytrail: don't allow PCIE wake ups The PCIe subsystem was constantly waking up boards from S3 and S5. Completely disable PCIe wake ups. It can be made mainboard-configurable later if needed. BUG=chrome-os-partner:24004 BRANCH=None TEST=Both S3 and EC RW->RW update (trip through S5) don't cause wakeups. Change-Id: I922e2947c4b6e29277d913f06192601a2954f8fe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176791 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/smm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index c654c85..e10c70b 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -93,8 +93,8 @@ void southcluster_smm_enable_smi(void) { printk(BIOS_DEBUG, "Enabling SMIs.\n"); - /* Configure events */ - enable_pm1(PWRBTN_EN | GBL_EN); + /* Configure events Disable pcie wake. */ + enable_pm1(PWRBTN_EN | GBL_EN | PCIEXPWAK_DIS); disable_gpe(PME_B0_EN); /* Set up the GPIO route. */

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Patch set updated for coreboot: b8859cd rambi: fixup settings so trackpad can be found in kernel
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4970 -gerrit commit b8859cda06178bc86e8406824c1d78ad572057bb Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 13 14:31:16 2013 -0600 rambi: fixup settings so trackpad can be found in kernel The kernel chromeos_laptop driver nomenclature expects the board name to not be in all caps. Fix this as well as the i2c address for the trackpad. BUG=chrome-os-partner:24307 BRANCH=None TEST=Built and booted. trackpad device is found. IRQs still not working yet. Change-Id: Id6be8ee4bce2835e303ea4fe63944be80d2d7ec2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176680 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/rambi/Kconfig | 2 +- src/mainboard/google/rambi/onboard.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index c0cb8ca..dc31541 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -23,7 +23,7 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER string - default "RAMBI" + default "Rambi" config VGA_BIOS_FILE string diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h index 290f58c..6a8e751 100644 --- a/src/mainboard/google/rambi/onboard.h +++ b/src/mainboard/google/rambi/onboard.h @@ -25,13 +25,13 @@ #define BOARD_TRACKPAD_NAME "trackpad" #define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) #define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ -#define BOARD_TRACKPAD_I2C_BUS 1 /* TODO(shawnn): Check this */ -#define BOARD_TRACKPAD_I2C_ADDR 0x67 /* TODO(shawnn): Check this */ +#define BOARD_TRACKPAD_I2C_BUS 0 +#define BOARD_TRACKPAD_I2C_ADDR 0x4b #define BOARD_TOUCHSCREEN_NAME "touchscreen" #define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) #define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ -#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* TODO(shawnn): Check this */ +#define BOARD_TOUCHSCREEN_I2C_BUS 5 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ #endif

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Patch set updated for coreboot: 6b6c99c baytrail: gpio: Make pad input/output state mutually exclusive
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4971 -gerrit commit 6b6c99cf21da741167b7a8112ff42fb3dd37d37b Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Wed Nov 13 15:37:11 2013 -0800 baytrail: gpio: Make pad input/output state mutually exclusive Previously pads were being configured as both input and output simultaneously due to the config bits being active low. Create new defines that only enable either input or output, and use them in our GPIO configs. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Verify system boots and peripherals still function. BRANCH=None. Change-Id: If386682a3d810864b7b9f5d2aecdb2e6cfceea86 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176725 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index 154ac84..bdb33f1 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -143,13 +143,17 @@ #define PAD_VAL_OUTPUT_DISABLE (1 << 1) #define PAD_VAL_OUTPUT_ENABLE (0 << 1) +/* Input / Output state should usually be mutually exclusive */ +#define PAD_VAL_INPUT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) +#define PAD_VAL_OUTPUT (PAD_VAL_OUTPUT_ENABLE | PAD_VAL_INPUT_DISABLE) + /* pad_val[0] - Value */ #define PAD_VAL_HIGH (1 << 0) #define PAD_VAL_LOW (0 << 0) /* pad_val reg power-on default varies by pad, and apparently can cause issues * if not set correctly, even if the pin isn't configured as GPIO. */ -#define PAD_VAL_DEFAULT (PAD_VAL_INPUT_ENABLE | PAD_VAL_OUTPUT_DISABLE) +#define PAD_VAL_DEFAULT PAD_VAL_INPUT /* Configure GPIOs as legacy by default. GPNCORE doesn't support * legacy config -- so also configure the pad regs as GPIO. We rely upon @@ -158,7 +162,7 @@ { .pad_conf0 = PAD_PU_10K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT_ENABLE, \ + .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } @@ -166,7 +170,7 @@ { .pad_conf0 = PAD_PU_10K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT_ENABLE, \ + .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } @@ -174,7 +178,7 @@ { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT_ENABLE, \ + .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } @@ -183,7 +187,7 @@ { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT_ENABLE, \ + .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT, \ .tne = GPIO_NEDGE_ENABLE } @@ -193,7 +197,7 @@ { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT_ENABLE, \ + .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT, \ .tne = GPIO_PEDGE_ENABLE } @@ -202,7 +206,7 @@ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_LOW, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_LOW } @@ -211,7 +215,7 @@ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_OUTPUT_ENABLE | PAD_VAL_HIGH, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_OUTPUT, \ .gp_lvl = GPIO_LEVEL_HIGH } @@ -238,7 +242,7 @@ #define GPIO_ACPI_SCI \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT_ENABLE, \ + .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT, \ .tne = 1, \ @@ -246,7 +250,7 @@ #define GPIO_ACPI_SMI \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT | PAD_FUNC0, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT_ENABLE, \ + .pad_val = PAD_VAL_INPUT, \ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT, \ .tne = 1, \

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Patch set updated for coreboot: b8a124b reg_script: add iosf lpss port access
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4968 -gerrit commit b8a124bf267971982e712c90216bfb2a25d8bb99 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 12 20:20:10 2013 -0600 reg_script: add iosf lpss port access Add the LPSS IOSF port access to reg_script. This is going to be used by baytrail. BUG=chrome-os-partner:23790 BRANCH=None TEST=Buit. Change-Id: I0367acdb584f2de0bb871b136042b57fe6b7ec90 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176423 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/lib/reg_script.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index e03a8e4..d7c4577 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -263,6 +263,8 @@ static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_ushphy_read(step->reg); case IOSF_PORT_SCC: return iosf_scc_read(step->reg); + case IOSF_PORT_LPSS: + return iosf_lpss_read(step->reg); case IOSF_PORT_CCU: return iosf_ccu_read(step->reg); } @@ -297,6 +299,9 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_SCC: iosf_scc_write(step->reg, step->value); break; + case IOSF_PORT_LPSS: + iosf_lpss_write(step->reg, step->value); + break; case IOSF_PORT_CCU: iosf_ccu_write(step->reg, step->value); break;

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Patch set updated for coreboot: 8c53098 baytrail: first pass at lpss device initialization
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4969 -gerrit commit 8c530984c97e09557e3b5c1878f73b05cfd31088 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 12 20:21:53 2013 -0600 baytrail: first pass at lpss device initialization This commit does the common parts for all LPSS devices that are enabled: enable snoop in IOSF and enable power management. Additionally, the i2c devices are taken out of reset. BUG=chrome-os-partner:23790 BRANCH=None TEST=Built and booted with modified kernel-next. I2C bus devices show up and I see 0x10 on one of the buses. Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176424 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/lpss.c | 162 ++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index a6560ff..1f643f9 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += acpi.c ramstage-y += lpe.c ramstage-y += scc.c ramstage-y += emmc.c +ramstage-y += lpss.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c new file mode 100644 index 0000000..ccfab38 --- /dev/null +++ b/src/soc/intel/baytrail/lpss.c @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> + + +static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) +{ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, + ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), + LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), + REG_SCRIPT_END, + }; + + reg_script_run(ops); +} + +static int dev_ctl_reg(device_t dev) +{ + int iosf_reg = -1; +#define SET_IOSF_REG(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + iosf_reg = LPSS_ ## name_ ## _CTL + + switch (dev->path.pci.devfn) { + SET_IOSF_REG(SIO_DMA1); + break; + SET_IOSF_REG(I2C1); + break; + SET_IOSF_REG(I2C2); + break; + SET_IOSF_REG(I2C3); + break; + SET_IOSF_REG(I2C4); + break; + SET_IOSF_REG(I2C5); + break; + SET_IOSF_REG(I2C6); + break; + SET_IOSF_REG(I2C7); + break; + SET_IOSF_REG(SIO_DMA2); + break; + SET_IOSF_REG(PWM1); + break; + SET_IOSF_REG(PWM2); + break; + SET_IOSF_REG(HSUART1); + break; + SET_IOSF_REG(HSUART2); + break; + SET_IOSF_REG(SPI); + break; + } + return iosf_reg; +} + +static void i2c_disable_resets(device_t dev) +{ + /* Release the I2C devices from reset. */ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), + REG_SCRIPT_END, + }; + +#define CASE_I2C(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) + + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1): + CASE_I2C(I2C2): + CASE_I2C(I2C3): + CASE_I2C(I2C4): + CASE_I2C(I2C5): + CASE_I2C(I2C6): + CASE_I2C(I2C7): + printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); + reg_script_run(ops); + break; + default: + return; + } +} + +static void lpss_init(device_t dev) +{ + int iosf_reg = dev_ctl_reg(dev); + + if (iosf_reg < 0) { + int slot = PCI_SLOT(dev->path.pci.devfn); + int func = PCI_FUNC(dev->path.pci.devfn); + printk(BIOS_DEBUG, "Could not find iosf_reg for %02x.%01x\n", + slot, func); + return; + } + dev_enable_snoop_and_pm(dev, iosf_reg); + + i2c_disable_resets(dev); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = lpss_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + SIO_DMA1_DEVID, + I2C1_DEVID, + I2C2_DEVID, + I2C3_DEVID, + I2C4_DEVID, + I2C5_DEVID, + I2C6_DEVID, + I2C7_DEVID, + SIO_DMA2_DEVID, + PWM1_DEVID, + PWM2_DEVID, + HSUART1_DEVID, + HSUART2_DEVID, + SPI_DEVID, + 0, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: b76f17a baytrail: initialize common SSC functionality
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4966 -gerrit commit b76f17ad99f0d0510d79a1bc5a2c2a73edd6d787 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 12 16:40:33 2013 -0600 baytrail: initialize common SSC functionality The SSC (storage control cluster) houses the SD, SDIO, and eMMC interfaces. The scc cofniguration function, baytrail_init_scc(), is ran in the pre device stage to initialize the SCC. The eMMC is expected to be configured for version 4.5. BUG=chrome-os-partner:23966 BRANCH=None TEST=Built and booted with some other eMMC changes into login screen off of eMMC device. Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176535 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/ramstage.c | 2 + src/soc/intel/baytrail/scc.c | 83 ++++++++++++++++++++++++++++++ 4 files changed, 87 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 81b2c24..c7e3843 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -39,6 +39,7 @@ ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c ramstage-y += acpi.c ramstage-y += lpe.c +ramstage-y += scc.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index 4fa6ddd..217c67b 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -33,6 +33,7 @@ void baytrail_run_reference_code(void); #else static inline void baytrail_run_reference_code(void) {} #endif +void baytrail_init_scc(void); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index 0c2bed8..b0b48b0 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -166,6 +166,8 @@ void baytrail_init_pre_device(void) config = mainboard_get_gpios(); setup_soc_gpios(config); + baytrail_init_scc(); + /* Indicate S3 resume to rest of ramstage. */ s3_resume_prepare(); } diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c new file mode 100644 index 0000000..af941fa --- /dev/null +++ b/src/soc/intel/baytrail/scc.c @@ -0,0 +1,83 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <reg_script.h> + +#include <baytrail/iosf.h> +#include <baytrail/ramstage.h> + +static const struct reg_script scc_start_dll[] = { + /* Configure master DLL. */ + REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4964, 0x00078000), + /* Configure Swing,FSM for Master DLL */ + REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00000133), + /* Run+Local Reset on Master DLL */ + REG_IOSF_WRITE(IOSF_PORT_SCORE, 0x4970, 0x00001933), + REG_SCRIPT_END, +}; + +static const struct reg_script scc_after_dll[] = { + /* Configure Write Path */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4954, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4958, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x495c, ~0x7fff, 0x35ad), + /* Configure Read Path */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x43e4, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x4324, ~0x7fff, 0x35ad), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x42b4, ~0x7fff, 0x35ad), + /* eMMC 4.5 TX and RX DLL */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a4, ~0x1f001f, 0xa000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49a8, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49ac, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b0, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b4, ~0x1f001f, 0xd000d), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x49b8, ~0x1, 0x0), + /* cfio_regs_mmc1_ELECTRICAL.nslew/pslew */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x0), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x0), + /* + * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_ocp = 01 + * iosf2ocp_private.GENREGRW1.cr_clock_enable_clk_xin = 01 + */ + REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0xf, 0x5), + /* Enable IOSF Snoop */ + REG_IOSF_OR(IOSF_PORT_SCC, 0x00, (1 << 7)), + /* SDIO 3V Support. */ + REG_IOSF_RMW(IOSF_PORT_SCC, 0x600, ~0x30, 0x30), + REG_SCRIPT_END, +}; + +void baytrail_init_scc(void) +{ + uint32_t dll_values; + + printk(BIOS_DEBUG, "Initializing sideband SCC registers.\n"); + + /* Common Sideband Initialization for SCC */ + reg_script_run(scc_start_dll); + + /* Override Slave Path - populate DLL settings. */ + dll_values = iosf_score_read(0x496c) & 0x7ffff; + dll_values |= iosf_score_read(0x4950) & ~0xfffff; + iosf_score_write(0x4950, dll_values | (1 << 19)); + + reg_script_run(scc_after_dll); +}

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Patch set updated for coreboot: 190fe8b baytrail: initialize eMMC device
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4967 -gerrit commit 190fe8b6771531d3ff8319771003f7b128c82f87 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 12 16:44:18 2013 -0600 baytrail: initialize eMMC device The eMMC device is initialized as version 4.5 with HS200 speeds. BUG=chrome-os-partner:23966 BRANCH=None TEST=Built and booted rambi to login screen off of eMMC device. Change-Id: I686c6136005fcb2587b939ddea293f4398df9868 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176536 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/emmc.c | 75 +++++++++++++++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index c7e3843..a6560ff 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -40,6 +40,7 @@ ramstage-y += sata.c ramstage-y += acpi.c ramstage-y += lpe.c ramstage-y += scc.c +ramstage-y += emmc.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c new file mode 100644 index 0000000..18c16e8 --- /dev/null +++ b/src/soc/intel/baytrail/emmc.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <baytrail/iosf.h> +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> + +static const struct reg_script emmc_ops[] = { + /* Enable 2ms card stable feature. */ + REG_PCI_OR32(0xa8, (1 << 24)), + /* Enable HS200 */ + REG_PCI_WRITE32(0xa0, 0x446cc801), + REG_PCI_WRITE32(0xa4, 0x80000807), + /* cfio_regs_score_special_bits.sdio1_dummy_loopback_en=1 */ + REG_IOSF_OR(IOSF_PORT_SCORE, 0x49c0, (1 << 3)), + /* CLKGATE_EN_1 . cr_scc_mipihsi_clkgate_en = 1 */ + REG_IOSF_RMW(IOSF_PORT_CCU, 0x1c, ~(3 << 26), (1 << 26)), + /* Set slew for HS200 */ + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c0, ~0x3c, 0x3c), + REG_IOSF_RMW(IOSF_PORT_SCORE, 0x48c4, ~0x3c, 0x3c), + /* Max timeout */ + REG_RES_WRITE8(PCI_BASE_ADDRESS_0, 0x002e, 0x0e), + REG_SCRIPT_END, +}; + +static void emmc_init(device_t dev) +{ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + REG_SCRIPT_NEXT(emmc_ops), + REG_SCRIPT_END, + }; + printk(BIOS_DEBUG, "eMMC init\n"); + reg_script_run(ops); +} + +static struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = emmc_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = MMC_DEVID, +};

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Patch set updated for coreboot: 6ddef52 baytrail: add score and ssc iosf access functions
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4964 -gerrit commit 6ddef528c1f1b8a7441e821b3b1bef1512f115d7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 12 16:37:05 2013 -0600 baytrail: add score and ssc iosf access functions The SCORE allows controlling the pad configuration while the SSC handles the configuration for the storage control cluster. BUG=chrome-os-partner:23966 BRANCH=None TEST=Built. Change-Id: Ifd9f67a4e88d5bb99faec6ceeb3e263001a87c41 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176533 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 10 ++++++++++ src/soc/intel/baytrail/iosf.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 48d89b7..3a63d4a 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -72,6 +72,10 @@ uint32_t iosf_lpss_read(int reg); void iosf_lpss_write(int reg, uint32_t val); uint32_t iosf_ccu_read(int reg); void iosf_ccu_write(int reg, uint32_t val); +uint32_t iosf_score_read(int reg); +void iosf_score_write(int reg, uint32_t val); +uint32_t iosf_scc_read(int reg); +void iosf_scc_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -84,7 +88,9 @@ void iosf_ccu_write(int reg, uint32_t val); #define IOSF_PORT_DUNIT_CH1 0x07 /* DUNIT Channel 1 */ #define IOSF_PORT_SYSMEMIO 0x0c /* System Memory IO */ #define IOSF_PORT_USBPHY 0x43 /* USB PHY */ +#define IOSF_PORT_SCORE 0x48 /* SCORE */ #define IOSF_PORT_USHPHY 0x61 /* USB XHCI PHY */ +#define IOSF_PORT_SCC 0x63 /* Storage Control Cluster */ #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ @@ -107,8 +113,12 @@ void iosf_ccu_write(int reg, uint32_t val); #define IOSF_OP_WRITE_SYSMEMIO (IOSF_OP_READ_SYSMEMIO | 1) #define IOSF_OP_READ_USBPHY 0x06 #define IOSF_OP_WRITE_USBPHY (IOSF_OP_READ_USBPHY | 1) +#define IOSF_OP_READ_SCORE 0x06 +#define IOSF_OP_WRITE_SCORE (IOSF_OP_READ_SCORE | 1) #define IOSF_OP_READ_USHPHY 0x06 #define IOSF_OP_WRITE_USHPHY (IOSF_OP_READ_USHPHY | 1) +#define IOSF_OP_READ_SCC 0x06 +#define IOSF_OP_WRITE_SCC (IOSF_OP_READ_SCC | 1) #define IOSF_OP_READ_LPSS 0x06 #define IOSF_OP_WRITE_LPSS (IOSF_OP_READ_LPSS | 1) #define IOSF_OP_READ_SATAPHY 0x00 diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index 7e0dacb..4840dea 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -168,3 +168,31 @@ void iosf_ccu_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_CCU); return iosf_write_port(cr, reg, val); } + +uint32_t iosf_score_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SCORE) | + IOSF_PORT(IOSF_PORT_SCORE); + return iosf_read_port(cr, reg); +} + +void iosf_score_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SCORE) | + IOSF_PORT(IOSF_PORT_SCORE); + return iosf_write_port(cr, reg, val); +} + +uint32_t iosf_scc_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_SCC) | + IOSF_PORT(IOSF_PORT_SCC); + return iosf_read_port(cr, reg); +} + +void iosf_scc_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_SCC) | + IOSF_PORT(IOSF_PORT_SCC); + return iosf_write_port(cr, reg, val); +}

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Patch set updated for coreboot: 5466ab2 reg_script: add iosf paths for score, ccu, and ssc
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4965 -gerrit commit 5466ab2ffcb23de700b3281fdcf6d5e77cfc31e6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 12 16:38:54 2013 -0600 reg_script: add iosf paths for score, ccu, and ssc Handle SCORE, CCU, and SSC IOSF accesses. BUG=chrome-os-partner:23966 BRANCH=None TEST=Built. Change-Id: I6e678eb79bd1451f156bdd14cf46d3378dc527c9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176534 Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/lib/reg_script.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 3ca0b4a..e03a8e4 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -257,8 +257,14 @@ static uint32_t reg_script_read_iosf(struct reg_script_context *ctx) return iosf_punit_read(step->reg); case IOSF_PORT_USBPHY: return iosf_usbphy_read(step->reg); + case IOSF_PORT_SCORE: + return iosf_score_read(step->reg); case IOSF_PORT_USHPHY: return iosf_ushphy_read(step->reg); + case IOSF_PORT_SCC: + return iosf_scc_read(step->reg); + case IOSF_PORT_CCU: + return iosf_ccu_read(step->reg); } #endif return 0; @@ -282,9 +288,18 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) case IOSF_PORT_USBPHY: iosf_usbphy_write(step->reg, step->value); break; + case IOSF_PORT_SCORE: + iosf_score_write(step->reg, step->value); + break; case IOSF_PORT_USHPHY: iosf_ushphy_write(step->reg, step->value); break; + case IOSF_PORT_SCC: + iosf_scc_write(step->reg, step->value); + break; + case IOSF_PORT_CCU: + iosf_ccu_write(step->reg, step->value); + break; } #endif }

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coreboot-gerrit May 2014