the following patch was just integrated into master:
commit dc866cff31e26de7cf95bbd0675037d8066f7dc8
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Nov 12 20:21:53 2013 -0600
baytrail: first pass at lpss device initialization
This commit does the common parts for all LPSS devices
that are enabled: enable snoop in IOSF and enable power
management. Additionally, the i2c devices are taken out of
reset.
BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted with modified kernel-next. I2C bus devices
show up and I see 0x10 on one of the buses.
Change-Id: I540caea6a8666f5684dc5cee683a6b085dfac6de
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176424
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4969
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/4969 for details.
-gerrit
the following patch was just integrated into master:
commit 64b902b57a035c31043cb0c6690e221a25287ff3
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Nov 12 20:20:10 2013 -0600
reg_script: add iosf lpss port access
Add the LPSS IOSF port access to reg_script. This is
going to be used by baytrail.
BUG=chrome-os-partner:23790
BRANCH=None
TEST=Buit.
Change-Id: I0367acdb584f2de0bb871b136042b57fe6b7ec90
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176423
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4968
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/4968 for details.
-gerrit
the following patch was just integrated into master:
commit 159216949597cb68a477af1b3723705f5e87cbb1
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Nov 12 16:44:18 2013 -0600
baytrail: initialize eMMC device
The eMMC device is initialized as version 4.5 with HS200 speeds.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted rambi to login screen off of eMMC device.
Change-Id: I686c6136005fcb2587b939ddea293f4398df9868
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176536
Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4967
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/4967 for details.
-gerrit
the following patch was just integrated into master:
commit c626b74c1d5e1faaa6a23e3d658b0e097e6404f9
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Nov 12 16:40:33 2013 -0600
baytrail: initialize common SSC functionality
The SSC (storage control cluster) houses the SD, SDIO, and eMMC
interfaces. The scc cofniguration function, baytrail_init_scc(),
is ran in the pre device stage to initialize the SCC. The eMMC
is expected to be configured for version 4.5.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built and booted with some other eMMC changes into login screen off
of eMMC device.
Change-Id: I81cc755a790b7e43ad234a8201dae480277202c8
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176535
Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4966
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/4966 for details.
-gerrit
the following patch was just integrated into master:
commit d7f0f3de10bb2aa4e41c8d87b364feaab7c1f704
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Tue Nov 12 16:37:05 2013 -0600
baytrail: add score and ssc iosf access functions
The SCORE allows controlling the pad configuration while
the SSC handles the configuration for the storage control
cluster.
BUG=chrome-os-partner:23966
BRANCH=None
TEST=Built.
Change-Id: Ifd9f67a4e88d5bb99faec6ceeb3e263001a87c41
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176533
Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/4964 for details.
-gerrit
the following patch was just integrated into master:
commit 9547f8d799829ddab9196c4e0cad644a06db49e9
Author: Shawn Nematbakhsh <shawnn(a)chromium.org>
Date: Fri Nov 8 17:23:26 2013 -0800
rambi: Add DIRQs for trackpad and touchscreen
Also add the relevant info about these pins to the ASL tables + add
SMBIOS type 41 data for these parts.
BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.
Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8
Reviewed-on: https://chromium-review.googlesource.com/176299
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/4963 for details.
-gerrit