coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch merged into coreboot/master: ebf7ec5 baytrail: ensure init_chromeos() is called in romstage
by gerrit＠coreboot.org 07 May '14

07 May '14

the following patch was just integrated into master: commit ebf7ec5dab9198a0a84174e72b8eaf1af68d7b73 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 14 13:47:08 2013 -0600 baytrail: ensure init_chromeos() is called in romstage The TPM needs to have the TPM_Startup command sent to it on all boot paths. The call init_chromeos() in romstage_common() fulfills this requirement. BUG=chrome-os-partner:24057 BRANCH=None TEST=Built and booted. Was able to suspend to ram multiple times in a row. Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176803 Reviewed-by: Todd Broch <tbroch(a)chromium.org> Tested-by: Todd Broch <tbroch(a)chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/4974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4974 for details. -gerrit

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Patch merged into coreboot/master: ee3ec72 rambi: distribute IRQs away from PIRQA on pci devices
by gerrit＠coreboot.org 07 May '14

07 May '14

the following patch was just integrated into master: commit ee3ec728d86c83fbbaaa84bb72137dca7cd511a2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 14 11:15:43 2013 -0600 rambi: distribute IRQs away from PIRQA on pci devices Some of the drivers in the kernel were not so happy about having shared IRQs. Also, sharing IRQs means more code needs to be run in interrupt context to determine if the IRQ was meant for a particular device. Fix this. No more 'mmc1: got irq while runtime suspended' messages. BUG=chrome-os-partner:24056 BRANCH=None TEST=Built and booted. Looked at /proc/interrupts and noted no more sharing between pci devices. Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176792 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: http://review.coreboot.org/4973 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/4973 for details. -gerrit

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Patch merged into coreboot/master: bf9f243 superio/common/conf_mode: Provide another common pnp entry/exit
by gerrit＠coreboot.org 07 May '14

07 May '14

the following patch was just integrated into master: commit bf9f24385739d29dd5ccea82dec06e1cdd2c10fe Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 17:24:59 2014 +1000 superio/common/conf_mode: Provide another common pnp entry/exit ITE Super I/O's make use of this method to enter and exit in and out of their PNP configuration. Provide functions for use in ram stage component. Change-Id: I2b546c2b17eefc89aaab4982192f5e9a15a16c2f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5666 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek(a)assembler.cz> See http://review.coreboot.org/5666 for details. -gerrit

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New patch to review for coreboot: 0b57cca baytrail: minor style
by Patrick Georgi 07 May '14

07 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5692 -gerrit commit 0b57ccaf13daa4b3c8d8b6a511da398bfe094abe Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 7 20:20:10 2014 +0200 baytrail: minor style use IS_ENABLED() over #if brackets Change-Id: I101f99971c0f7b5311ef19cc9832713ab0696935 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/soc/intel/baytrail/romstage/raminit.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index dc840b0..352b86f 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -118,9 +118,7 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->version = MRC_PARAMS_VER; mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; -#if CONFIG_MRC_RMT - mp->rmt_enabled = 1; -#endif + mp->rmt_enabled = IS_ENABLED(CONFIG_MRC_RMT); if (recovery_mode_enabled()) { printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (!mrc_cache_get_current(&cache)) {

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New patch to review for coreboot: bd47e97 rambi: Remove outdated comment
by Patrick Georgi 07 May '14

07 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5691 -gerrit commit bd47e97bee0d7d90ae3696d19a1a4ab0c965f54b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 7 20:19:50 2014 +0200 rambi: Remove outdated comment Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/mainboard/google/rambi/romstage.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index efe1343..48fe387 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -92,7 +92,6 @@ void mainboard_romstage_entry(struct romstage_params *rp) if (!spd_file) die("SPD data not found."); - /* Both channels are always present. */ spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), ntohl(spd_file->len) / SPD_SIZE, &dual_channel);

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Patch merged into coreboot/master: d520840 kconfig: update to follow upstream more closely
by gerrit＠coreboot.org 07 May '14

07 May '14

the following patch was just integrated into master: commit d520840d4ca7d8fbd9c64946ee5f2d7ea44b8557 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Apr 11 20:24:06 2014 +0200 kconfig: update to follow upstream more closely This might break a bunch of stuff (eg. win32 support), but otherwise introduces nconfig (ncurses based configuration frontend), partial configuration headers for improved dependency tracking (which requires some more build system support) and various bug fixes. Change-Id: I5d8a280810c6a26fc3fd056d5d94cb9e591a0ff5 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/5487 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5487 for details. -gerrit

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Patch set updated for coreboot: fde132b baytrail: ensure init_chromeos() is called in romstage
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4974 -gerrit commit fde132b4623ba0352e4bbcdf4590aefc04c5c887 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 14 13:47:08 2013 -0600 baytrail: ensure init_chromeos() is called in romstage The TPM needs to have the TPM_Startup command sent to it on all boot paths. The call init_chromeos() in romstage_common() fulfills this requirement. BUG=chrome-os-partner:24057 BRANCH=None TEST=Built and booted. Was able to suspend to ram multiple times in a row. Change-Id: Id0339a9d82897249d20ff5f62d2dcb8b535310fa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176803 Reviewed-by: Todd Broch <tbroch(a)chromium.org> Tested-by: Todd Broch <tbroch(a)chromium.org> Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/romstage/romstage.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 969e848..91637d5 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -32,6 +32,7 @@ #include <ramstage_cache.h> #include <romstage_handoff.h> #include <timestamp.h> +#include <vendorcode/google/chromeos/chromeos.h> #include <baytrail/gpio.h> #include <baytrail/iomap.h> #include <baytrail/lpc.h> @@ -179,6 +180,16 @@ static int chipset_prev_sleep_state(void) return prev_sleep_state; } +#if CONFIG_CHROMEOS +static inline void chromeos_init(int prev_sleep_state) +{ + /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ + init_chromeos(prev_sleep_state == 3 ? 2 : 0); +} +#else +static inline void chromeos_init(int prev_sleep_state) {} +#endif + /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { @@ -206,6 +217,8 @@ void romstage_common(struct romstage_params *params) else printk(BIOS_DEBUG, "Romstage handoff structure not added!\n"); + chromeos_init(prev_sleep_state); + /* Save timestamp information. */ timestamp_init(ts64_to_tsc(params->ts.times[0])); timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));

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Patch set updated for coreboot: 5937400 baytrail: fix direct irq pad configuration
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4975 -gerrit commit 5937400385e8c21c2641a7d74df2835b79952142 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 14 17:39:04 2013 -0600 baytrail: fix direct irq pad configuration When a pad is configured for direct IRQ it needs to be in non-legacy. Additionally, the signal is passed directly to the APIC by setting the LEVEL and TPE bits in the pad config register. The APIC can then be configured for level, edge, and rising/falling. BUG=chrome-os-partner:24037 BUG=chrome-os-partner:22863 BRANCH=None TEST=Built and booted with this config. Trackpad is firing interrupts more than it should, but it appears to be a trackpad firmware and/or configuration issue. Change-Id: I00042b2ddba67d6bf23f0e7468d0719196e6f865 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176793 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gpio.h | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/gpio.h b/src/soc/intel/baytrail/baytrail/gpio.h index bdb33f1..1b5eacf 100644 --- a/src/soc/intel/baytrail/baytrail/gpio.h +++ b/src/soc/intel/baytrail/baytrail/gpio.h @@ -182,25 +182,13 @@ .use_sel = GPIO_USE_LEGACY, \ .io_sel = GPIO_DIR_INPUT } -/* Direct / dedicated IRQ input - falling-edge triggered */ +/* Direct / dedicated IRQ input - pass signal directly to apic */ #define GPIO_DIRQ \ { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ, \ + | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = GPIO_NEDGE_ENABLE } + .pad_val = PAD_VAL_INPUT, } -/* Direct / dedicated IRQ input - rising-edge triggered */ -#define GPIO_DIRQ_INVERT \ - { .pad_conf0 = PAD_PU_10K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \ - | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ, \ - .pad_conf1 = PAD_CONFIG1_DEFAULT, \ - .pad_val = PAD_VAL_INPUT, \ - .use_sel = GPIO_USE_LEGACY, \ - .io_sel = GPIO_DIR_INPUT, \ - .tne = GPIO_PEDGE_ENABLE } #define GPIO_OUT_LOW \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \

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Patch set updated for coreboot: 29ed6d4 rambi: distribute IRQs away from PIRQA on pci devices
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4973 -gerrit commit 29ed6d4e5e79fb9a38041875efe0efeb09b8f87a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 14 11:15:43 2013 -0600 rambi: distribute IRQs away from PIRQA on pci devices Some of the drivers in the kernel were not so happy about having shared IRQs. Also, sharing IRQs means more code needs to be run in interrupt context to determine if the IRQ was meant for a particular device. Fix this. No more 'mmc1: got irq while runtime suspended' messages. BUG=chrome-os-partner:24056 BRANCH=None TEST=Built and booted. Looked at /proc/interrupts and noted no more sharing between pci devices. Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176792 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/rambi/irqroute.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index fa7a6c3..eaafff9 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -23,17 +23,17 @@ #define PCI_DEV_PIRQ_ROUTES \ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SD_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(MMC_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \ - PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) #define PIRQ_PIC_ROUTES \

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Patch set updated for coreboot: d85c1f0 rambi: handle single channel configs
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4983 -gerrit commit d85c1f015626a719e571d62bc1c9caaccfa00dd4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 27 16:51:26 2013 -0600 rambi: handle single channel configs Some 1.5 boards have a single channel ram configuration. Accomodate such configs. BUG=chrome-os-partner:22865 BRANCH=None TEST=Built and booted ChromeOS. Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178340 Reviewed-by: Nick Sanders <nsanders(a)chromium.org> Tested-by: Bernie Thompson <bhthompson(a)chromium.org> Tested-by: Nick Sanders <nsanders(a)chromium.org> --- src/mainboard/google/rambi/romstage.c | 18 +++++++++++++++--- src/mainboard/google/rambi/spd/Makefile.inc | 4 ++++ 2 files changed, 19 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/romstage.c b/src/mainboard/google/rambi/romstage.c index 369ebad..efe1343 100644 --- a/src/mainboard/google/rambi/romstage.c +++ b/src/mainboard/google/rambi/romstage.c @@ -31,7 +31,12 @@ * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz * 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz * 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz + * 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz + * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz */ +static const uint32_t dual_channel_config = + (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3); + #define SPD_SIZE 256 #define GPIO_SSUS_37_PAD 57 #define GPIO_SSUS_38_PAD 50 @@ -43,7 +48,7 @@ static inline void disable_internal_pull(int pad) write32(ssus_pconf0(pad), read32(ssus_pconf0(pad)) & pull_mask); } -static void *get_spd_pointer(char *spd_file_content, int total_spds) +static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual) { int ram_id = 0; @@ -63,6 +68,10 @@ static void *get_spd_pointer(char *spd_file_content, int total_spds) if (ram_id >= total_spds) return NULL; + /* Single channel configs */ + if (dual_channel_config & (1 << ram_id)) + *dual = 1; + return &spd_file_content[SPD_SIZE * ram_id]; } @@ -70,6 +79,7 @@ void mainboard_romstage_entry(struct romstage_params *rp) { struct cbfs_file *spd_file; void *spd_content; + int dual_channel = 0; struct mrc_params mp = { .mainboard = { @@ -84,9 +94,11 @@ void mainboard_romstage_entry(struct romstage_params *rp) /* Both channels are always present. */ spd_content = get_spd_pointer(CBFS_SUBHEADER(spd_file), - ntohl(spd_file->len) / SPD_SIZE); + ntohl(spd_file->len) / SPD_SIZE, + &dual_channel); mp.mainboard.dram_data[0] = spd_content; - mp.mainboard.dram_data[1] = spd_content; + if (dual_channel) + mp.mainboard.dram_data[1] = spd_content; rp->mrc_params = &mp; romstage_common(rp); diff --git a/src/mainboard/google/rambi/spd/Makefile.inc b/src/mainboard/google/rambi/spd/Makefile.inc index 36f4b66..fb0335f 100644 --- a/src/mainboard/google/rambi/spd/Makefile.inc +++ b/src/mainboard/google/rambi/spd/Makefile.inc @@ -25,10 +25,14 @@ SPD_BIN = $(obj)/spd.bin # 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz # 0b010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz # 0b011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz +# 0b100 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz +# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125 SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125 SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 +SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)

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coreboot-gerrit May 2014