coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

1 participants
1066 discussions

Patch set updated for coreboot: dcf3752 baytrail: romstage: Add config option to enable RMT
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4982 -gerrit commit dcf37526d6623f644634271d8a72ba9007888951 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Nov 26 15:37:43 2013 -0800 baytrail: romstage: Add config option to enable RMT Add config option to enable RMT in the MRC. BUG=chrome-os-partner:21807 TEST=Manual. Build w/ "USE=rmt", verify RMT print seen on FW console. Build w/o USE flag, verify no RMT print. BRANCH=None. CQ-DEPEND=CL:*148655 Change-Id: Ibd3da87317a3359e797d9b43bc437e7227a85048 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178095 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 4 ++++ src/soc/intel/baytrail/baytrail/mrc_wrapper.h | 3 ++- src/soc/intel/baytrail/romstage/raminit.c | 4 +++- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index e0e6c2a..969fa15 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -80,6 +80,10 @@ config MRC_BIN_ADDRESS hex default 0xfffa0000 +config MRC_RMT + bool "Enable MRC RMT training + debug prints" + default n + config CACHE_MRC_SETTINGS bool "Save cached MRC settings" default n diff --git a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h b/src/soc/intel/baytrail/baytrail/mrc_wrapper.h index 858aab8..2074100 100644 --- a/src/soc/intel/baytrail/baytrail/mrc_wrapper.h +++ b/src/soc/intel/baytrail/baytrail/mrc_wrapper.h @@ -28,7 +28,7 @@ #ifndef _MRC_WRAPPER_H_ #define _MRC_WRAPPER_H_ -#define MRC_PARAMS_VER 1 +#define MRC_PARAMS_VER 2 #define NUM_CHANNELS 2 @@ -78,6 +78,7 @@ struct mrc_params { const void *saved_data; int txe_size_mb; /* TXE memory size in megabytes. */ + int rmt_enabled; /* Enable RMT training + prints. */ /* Outputs */ void *txe_base_address; diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 017f37d..dc840b0 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -118,7 +118,9 @@ void raminit(struct mrc_params *mp, int prev_sleep_state) mp->version = MRC_PARAMS_VER; mp->console_out = &send_to_console; mp->prev_sleep_state = prev_sleep_state; - +#if CONFIG_MRC_RMT + mp->rmt_enabled = 1; +#endif if (recovery_mode_enabled()) { printk(BIOS_DEBUG, "Recovery mode: not using MRC cache.\n"); } else if (!mrc_cache_get_current(&cache)) {

1 0

Patch set updated for coreboot: 322ab9f baytrail: pcie: Root port initialization
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4981 -gerrit commit 322ab9ffa9db7283a7dc318685365e559d842527 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 22 14:16:49 2013 -0600 baytrail: pcie: Root port initialization Add PCIe driver to initialize root ports. BUG=chrome-os-partner:24111 TEST=Manual on Rambi. Verify that PCIe Wifi card is detected and able to detect networks. BRANCH=None. Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Change-Id: I3c68da5f27cd162e112add488bdf5ced192b7d12 Reviewed-on: https://chromium-review.googlesource.com/177652 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/pcie.h | 102 +++++++++++++++ src/soc/intel/baytrail/chip.h | 1 + src/soc/intel/baytrail/pcie.c | 230 +++++++++++++++++++++++++++++++++ 4 files changed, 334 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 1f643f9..6485cc0 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -42,6 +42,7 @@ ramstage-y += lpe.c ramstage-y += scc.c ramstage-y += emmc.c ramstage-y += lpss.c +ramstage-y += pcie.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/baytrail/pcie.h b/src/soc/intel/baytrail/baytrail/pcie.h new file mode 100644 index 0000000..98effea --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/pcie.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied wacbmem_entryanty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_PCIE_H_ +#define _BAYTRAIL_PCIE_H_ + +/* PCIe root port config space registers. */ +#define XCAP 0x40 +# define SI (1 << 24) +#define DCAP 0x44 +# define MPS_MASK 0x7 +#define DCTL_DSTS 0x48 +# define URE (1 << 3) +# define FEE (1 << 2) +# define NFE (1 << 1) +# define CEE (1 << 0) +#define LCAP 0x4c +# define L1EXIT_SHIFT 15 +# define L1EXIT_MASK (0x7 << L1EXIT_SHIFT) +#define LCTL 0x50 +# define CCC (1 << 6) +# define RL (1 << 5) +# define LD (1 << 4) +#define LSTS 0x52 +#define SLCAP 0x54 +# define SLN_SHIFT 19 +# define SLS_SHIFT 15 +# define SLV_SHIFT 7 +# define HPC (1 << 6) +# define HPS (1 << 5) +#define SLCTL_SLSTS 0x58 +# define PDS (1 << 22) +#define DCAP2 0x64 +# define OBFFS (0x3 << 18) +# define LTRMS (1 << 11) +#define DSTS2 0x68 +# define OBFFEN (3 << 13) +# define LTRME (1 << 10) +# define CTD (1 << 4) +#define CHCFG 0xd0 +# define UPSD (1 << 24) +# define UNRS (1 << 15) +# define UPRS (1 << 14) +#define MPC2 0xd4 +# define IPF (1 << 11) +# define LSTP (1 << 6) +# define EOIFD (1 << 1) +#define MPC 0xd8 +# define CCEL_SHIFT 15 +# define CCEL_MASK (0x7 << CCEL_SHIFT) +#define RPPGEN 0xe0 +# define RPSCGEN (1 << 15) +# define LCLKREQEN (1 << 13) +# define BBCLKREQEN (1 << 12) +# define SRDLCGEN (1 << 11) +# define SRDBCGEN (1 << 10) +# define RPDLCGEN (1 << 9) +# define RPDBCGEN (1 << 8) +#define PWRCTL 0xe8 +# define RPL1SQPOL (1 << 1) +# define RPDTSQPOL (1 << 0) +#define PHYCTL2_IOSFBCTL 0xf4 +# define PLL_OFF_EN (1 << 8) +# define TDFT (3 << 14) +# define TXCFGCHWAIT (3 << 12) +# define SIID (3 << 26) +#define STRPFUSECFG 0xfc +# define LANECFG_SHIFT 14 +# define LANECFG_MASK (0x3 << LANECFG_SHIFT) +#define AERCH 0x100 +#define NFTS 0x314 +#define L0SC 0x318 +#define CFG2 0x320 +# define CSREN (1 << 22) +# define LATGC_SHIFT 6 +# define LATGC_MASK (0x7 << LATGC_SHIFT) +#define PCIEDBG 0x324 +# define SPCE (1 << 5) +#define PCIESTS1 0x328 +#define PCIEALC 0x338 +#define RTP 0x33c +#define PHYCTL4 0x408 +# define SQDIS (1 << 27) + + +#endif /* _BAYTRAIL_PCIE_H_ */ diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 72ef10d..4c8897c 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -29,6 +29,7 @@ struct soc_intel_baytrail_config { uint8_t sata_port_map; uint8_t sata_ahci; uint8_t ide_legacy_combined; + uint8_t clkreq_enable; /* USB Port Disable mask */ uint16_t usb2_port_disable_mask; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c new file mode 100644 index 0000000..f68304d --- /dev/null +++ b/src/soc/intel/baytrail/pcie.c @@ -0,0 +1,230 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pciexp.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <baytrail/pci_devs.h> +#include <baytrail/pcie.h> +#include <baytrail/ramstage.h> + +#include "chip.h" + +static int pll_en_off; +static uint32_t strpfusecfg; + +static inline int root_port_offset(device_t dev) +{ + return PCI_FUNC(dev->path.pci.devfn); +} + +static inline int is_first_port(device_t dev) +{ + return root_port_offset(dev) == PCIE_PORT1_FUNC; +} + +static const struct reg_script init_static_before_exit_latency[] = { + /* Disable optimized buffer flush fill and latency tolerant reporting */ + REG_PCI_RMW32(DCAP2, ~(OBFFS | LTRMS), 0), + REG_PCI_RMW32(DSTS2, ~(OBFFEN| LTRME), 0), + /* Set maximum payload size. */ + REG_PCI_RMW32(DCAP, ~MPS_MASK, 0), + /* Disable transmit datapath flush timer, clear transmit config change + * wait time, clear sideband interface idle counter. */ + REG_PCI_RMW32(PHYCTL2_IOSFBCTL, ~(TDFT | TXCFGCHWAIT | SIID), 0), + REG_SCRIPT_END, +}; + +static const struct reg_script init_static_after_exit_latency[] = { + /* Set common clock configuration. */ + REG_PCI_OR16(LCTL, CCC), + /* Set NFTS to 0x743a361b */ + REG_PCI_WRITE32(NFTS, 0x743a361b), + /* Set common clock latency to 0x3 */ + REG_PCI_RMW32(MPC, ~CCEL_MASK, (0x3 << CCEL_SHIFT)), + /* Set relay timer policy. */ + REG_PCI_RMW32(RTP, 0xff000000, 0x854c74), + /* Set IOSF packet fast transmit mode and link speed training policy. */ + REG_PCI_OR16(MPC2, IPF | LSTP), + /* Channel configuration - enable upstream posted split, set non-posted + * and posted request size */ + REG_PCI_RMW32(CHCFG, ~UPSD, UNRS | UPRS), + /* Completion status replay enable and set TLP grant count */ + REG_PCI_RMW32(CFG2, ~(LATGC_MASK), CSREN | (3 << LATGC_SHIFT)), + /* Assume no IOAPIC behind root port -- disable EOI forwarding. */ + REG_PCI_OR16(MPC2, EOIFD), + /* Expose AER */ + REG_PCI_RMW32(AERCH, ~0, (1 << 16) | (1 << 0)), + /* set completion timeout to 160ms to 170ms */ + REG_PCI_RMW16(DSTS2, ~CTD, 0x6), + /* Enable AER */ + REG_PCI_OR16(DCTL_DSTS, URE | FEE | NFE | CEE), + /* Read and write back capabaility registers. */ + REG_PCI_OR32(0x34, 0), + REG_PCI_OR32(0x80, 0), + /* Retrain the link. */ + REG_PCI_OR16(LCTL, RL), + REG_SCRIPT_END, +}; + +static void byt_pcie_init(device_t dev) +{ + struct reg_script init_script[] = { + REG_SCRIPT_SET_DEV(dev), + REG_SCRIPT_NEXT(init_static_before_exit_latency), + /* Exit latency configuration based on + * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ + REG_PCI_RMW32(LCAP, ~L1EXIT_MASK, + 2 << (L1EXIT_MASK + pll_en_off)), + REG_SCRIPT_NEXT(init_static_after_exit_latency), + /* Disable hot plug, set power to 10W, set slot number. */ + REG_PCI_RMW32(SLCAP, ~(HPC | HPS), + (1 << SLS_SHIFT) | (100 << SLV_SHIFT) | + (root_port_offset(dev) << SLN_SHIFT)), + /* Dynamic clock gating. */ + REG_PCI_OR32(RPPGEN, RPDLCGEN | RPDBCGEN | RPSCGEN), + REG_PCI_OR32(PWRCTL, RPL1SQPOL | RPDTSQPOL), + REG_PCI_OR32(PCIEDBG, SPCE), + REG_SCRIPT_END, + }; + + reg_script_run(init_script); + + if (is_first_port(dev)) { + struct soc_intel_baytrail_config *config = dev->chip_info; + uint32_t reg = pci_read_config32(dev, RPPGEN); + reg |= SRDLCGEN | SRDBCGEN; + + if (config && config->clkreq_enable) + reg |= LCLKREQEN | BBCLKREQEN; + + pci_write_config32(dev, RPPGEN, reg); + } +} + +static const struct reg_script no_dev_behind_port[] = { + REG_PCI_OR32(PCIEALC, (1 << 26)), + REG_PCI_POLL32(PCIESTS1, 0x1f000000, (1 << 24), 50000), + REG_PCI_OR32(PHYCTL4, SQDIS), + REG_SCRIPT_END, +}; + +static void check_port_enabled(device_t dev) +{ + int rp_config = (strpfusecfg & LANECFG_MASK) >> LANECFG_SHIFT; + + switch (root_port_offset(dev)) { + case PCIE_PORT1_FUNC: + /* Port 1 cannot be disabled from strapping config. */ + break; + case PCIE_PORT2_FUNC: + /* Port 2 disabled in all configs but 4x1. */ + if (rp_config != 0x0) + dev->enabled = 0; + break; + case PCIE_PORT3_FUNC: + /* Port 3 disabled only in 1x4 config. */ + if (rp_config == 0x3) + dev->enabled = 0; + break; + case PCIE_PORT4_FUNC: + /* Port 4 disabled in 1x4 and 2x2 config. */ + if (rp_config >= 0x2) + dev->enabled = 0; + break; + } +} + +static void check_device_present(device_t dev) +{ + struct reg_script no_dev[] = { + REG_SCRIPT_SET_DEV(dev), + REG_SCRIPT_NEXT(no_dev_behind_port), + REG_SCRIPT_END, + }; + + /* Set slot implemented. */ + pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); + + /* No device present. */ + if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { + printk(BIOS_DEBUG, "No PCIe device present.\n"); + reg_script_run(no_dev); + dev->enabled = 0; + } else if(!dev->enabled) { + /* Port is disabled, but device present. Disable link. */ + pci_write_config32(dev, LCTL, + pci_read_config32(dev, LCTL) | LD); + } +} + +static void byt_pcie_enable(device_t dev) +{ + if (is_first_port(dev)) { + uint32_t reg = pci_read_config32(dev, PHYCTL2_IOSFBCTL); + pll_en_off = !!(reg & PLL_OFF_EN); + + strpfusecfg = pci_read_config32(dev, STRPFUSECFG); + } + + /* Check if device is enabled in strapping. */ + check_port_enabled(dev); + /* Determine if device is behind port. */ + check_device_present(dev); + + southcluster_enable_dev(dev); +} + +static void pcie_root_set_subsystem(device_t dev, unsigned vid, unsigned did) +{ + uint32_t didvid = ((did & 0xffff) << 16) | (vid & 0xffff); + + if (!didvid) + didvid = pci_read_config32(dev, PCI_VENDOR_ID); + pci_write_config32(dev, 0x94, didvid); +} + +static struct pci_operations pcie_root_ops = { + .set_subsystem = &pcie_root_set_subsystem, +}; + +static struct device_operations device_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = byt_pcie_init, + .scan_bus = pciexp_scan_bridge, + .enable = byt_pcie_enable, + .ops_pci = &pcie_root_ops, +}; + +static const unsigned short pci_device_ids[] = { + PCIE_PORT1_DEVID, PCIE_PORT2_DEVID, PCIE_PORT3_DEVID, PCIE_PORT4_DEVID, + 0 +}; + +static const struct pci_driver pcie_root_ports __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

1 0

Patch set updated for coreboot: e433a96 baytrail: gpio: Fix NCORE gpio-to-pad LUT
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4980 -gerrit commit e433a9637c7001118ae62b2a152937177a72ba9d Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Nov 21 11:00:53 2013 -0800 baytrail: gpio: Fix NCORE gpio-to-pad LUT NCORE pad addresses were wildly wrong due to documentation bugs. BUG=chrome-os-partner:24179 TEST=Manual on Rambi. Verify display isn't always on. Verify brightness control now works in Chrome OS. BRANCH=None. Change-Id: I464436a58baa4957329c11231c5a866dafd97ce8 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177597 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/gpio.c b/src/soc/intel/baytrail/gpio.c index 8cc7cc0..a3c2faa 100644 --- a/src/soc/intel/baytrail/gpio.c +++ b/src/soc/intel/baytrail/gpio.c @@ -25,9 +25,9 @@ /* GPIO-to-Pad LUTs */ static const u8 gpncore_gpio_to_pad[GPNCORE_COUNT] = - { 25, 24, 23, 32, 33, 34, 36, 37, /* [ 0: 7] */ - 35, 22, 20, 21, 18, 38, 39, 1, /* [ 8:15] */ - 4, 8, 17, 0, 3, 6, 16, 19, /* [16:23] */ + { 19, 18, 17, 20, 21, 22, 24, 25, /* [ 0: 7] */ + 23, 16, 14, 15, 12, 26, 27, 1, /* [ 8:15] */ + 4, 8, 11, 0, 3, 6, 10, 13, /* [16:23] */ 2, 5, 9 }; /* [24:26] */ static const u8 gpscore_gpio_to_pad[GPSCORE_COUNT] =

1 0

Patch set updated for coreboot: 47dfd5d rambi: use SERIRQ pad as keyboard irq in gpio mode
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4979 -gerrit commit 47dfd5df8b2c406f95ee7e2dc53f18705c9cfaa6 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Nov 20 15:21:40 2013 -0600 rambi: use SERIRQ pad as keyboard irq in gpio mode The level shifting between 3.3V and 1.8V for the SERIRQ signal is not working. Instead use the SERIRQ pad as a gpio which is used as a direct IRQ signal for the keyboard interupt. BUG=chrome-os-partner:23965 BRANCH=None TEST=Built and booted rambi. Keyboard works with associated EC change. CQ-DEPEND=CL:177189 Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177223 Tested-by: Bernie Thompson <bhthompson(a)chromium.org> --- src/mainboard/google/rambi/acpi/superio.asl | 3 +++ src/mainboard/google/rambi/gpio.c | 3 ++- src/mainboard/google/rambi/irqroute.h | 2 ++ src/mainboard/google/rambi/onboard.h | 2 ++ 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl index f40611c..3199ed5 100644 --- a/src/mainboard/google/rambi/acpi/superio.asl +++ b/src/mainboard/google/rambi/acpi/superio.asl @@ -19,10 +19,13 @@ /* mainboard configuration */ #include <mainboard/google/rambi/ec.h> +#include <mainboard/google/rambi/onboard.h> #define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources #define SIO_EC_HOST_ENABLE // EC Host Interface Resources #define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard +// Override default IRQ settings +#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ} /* ACPI code for EC SuperIO functions */ #include <ec/google/chromeec/acpi/superio.asl> diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index dfe880a..76002cf 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -106,7 +106,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ - GPIO_FUNC(1, PULL_UP, 10K), /* S0-SC050 - IRQ_SERIRQ */ + GPIO_DIRQ, /* S0-SC050 - IRQ_SERIRQ -- using for keyboard irq */ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ @@ -213,6 +213,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, + [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, }; static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index eaafff9..ddf6a76 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -49,6 +49,8 @@ /* CORE bank DIRQs - up to 16 supported */ #define TPAD_IRQ_OFFSET 0 #define TOUCH_IRQ_OFFSET 1 +#define I8042_IRQ_OFFSET 2 /* Corresponding SCORE GPIO pins */ #define TPAD_IRQ_GPIO 55 #define TOUCH_IRQ_GPIO 72 +#define I8042_IRQ_GPIO 50 diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h index 6a8e751..7f5d885 100644 --- a/src/mainboard/google/rambi/onboard.h +++ b/src/mainboard/google/rambi/onboard.h @@ -34,4 +34,6 @@ #define BOARD_TOUCHSCREEN_I2C_BUS 5 #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ +#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) + #endif

1 0

Patch set updated for coreboot: a8406ea rambi: make ramids non-legacy gpio inputs
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4977 -gerrit commit a8406ea3f8bf67fbea0675c07f8f3cc545f320af Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 18 13:50:02 2013 -0600 rambi: make ramids non-legacy gpio inputs The romstage code for rambi uses the mmio way of reading inputs. However, this is a problem is the GPIOs are set up as legacy mode. Subsequent warm resets mean the ram_id is read incorrectly. Ensure the ram_id is read consistently by keeping the GPIOs for ram_id in mmio mode. BUG=chrome-os-partner:24085 BRANCH=None TEST=Built and booted. And rebooted. Now seeing consistent ram_id values on warm resets. Change-Id: Ieff98c000be80998854f325754f1e819975d2be5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177230 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 7d44968..dfe880a 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -200,9 +200,9 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_NC, /* S534 - NC */ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */ GPIO_NC, /* S536 - NC */ - GPIO_INPUT, /* S537 - RAM_ID0 */ - GPIO_INPUT, /* S538 - RAM_ID1 */ - GPIO_INPUT, /* S539 - RAM_ID2 */ + GPIO_FUNC0, /* S537 - RAM_ID0 */ + GPIO_FUNC0, /* S538 - RAM_ID1 */ + GPIO_FUNC0, /* S539 - RAM_ID2 */ GPIO_NC, /* S540 - NC */ GPIO_NC, /* S541 - NC */ GPIO_NC, /* S542 - NC */

1 0

Patch set updated for coreboot: 2e583d1 baytrail: enable caching and prefetching in spi controller
by Aaron Durbin 07 May '14

07 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4976 -gerrit commit 2e583d1c4614c062e043a93412f341998d4382be Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 18 11:16:20 2013 -0600 baytrail: enable caching and prefetching in spi controller The default mode of the SPI controller has prefetching disabled. That obviously has a performance impact. Enable both caching and prefetching to make booting faster. This has a significant impact on streaming data out of SPI. BUG=chrome-os-partner:24085 BRANCH=None TEST=Built and booted rambi. Payload loading step went from ~285ms to ~54ms. Change-Id: I065cf44e1de7dcefc49aa9ea9ad0204929ab26f4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177220 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/baytrail/spi.h | 31 ++++++++++++++++++++++++++++++ src/soc/intel/baytrail/romstage/romstage.c | 10 ++++++++++ 2 files changed, 41 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/spi.h b/src/soc/intel/baytrail/baytrail/spi.h new file mode 100644 index 0000000..abe9e14 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/spi.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef _BAYTRAIL_SPI_H_ +#define _BAYTRAIL_SPI_H_ + +/* These registers live behind SPI_BASE_ADDRESS. */ +#define BCR 0xfc +# define SRC_MASK (0x3 << 2) +# define SRC_CACHE_NO_PREFETCH (0x0 << 2) +# define SRC_NO_CACHE_NO_PREFETCH (0x1 << 2) +# define SRC_CACHE_PREFETCH (0x2 << 2) + +#endif /* _BAYTRAIL_SPI_H_ */ + diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 91637d5..8436c65 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -41,6 +41,7 @@ #include <baytrail/reset.h> #include <baytrail/romstage.h> #include <baytrail/smm.h> +#include <baytrail/spi.h> static inline uint64_t timestamp_get(void) { @@ -94,6 +95,13 @@ static void program_base_addresses(void) pci_write_config32(lpc_dev, GBASE, reg); } +static void spi_init(void) +{ + const unsigned long bcr = SPI_BASE_ADDRESS + BCR; + /* Enable caching and prefetching in the SPI controller. */ + write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH); +} + static inline void mark_ts(struct romstage_params *rp, uint64_t ts) { struct romstage_timestamps *rt = &rp->ts; @@ -124,6 +132,8 @@ void * asmlinkage romstage_main(unsigned long bist, console_init(); + spi_init(); + set_max_freq(); punit_init();

1 0

Patch set updated for coreboot: 1855e4c gizmoboard: Move support of SPD data in CBFS
by Kyösti Mälkki 07 May '14

07 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5690 -gerrit commit 1855e4c4b32ba27b038da6abe917f8109d049424 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 16:40:15 2014 +0300 gizmoboard: Move support of SPD data in CBFS This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/dram/spd_cache.c | 69 ++++++++++++++++++++++ src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 60 +------------------ src/mainboard/gizmosphere/gizmo/Makefile.inc | 1 + src/northbridge/amd/agesa/def_callouts.c | 30 +++++++++- src/northbridge/amd/agesa/def_callouts.h | 2 + .../amd/agesa/family14/fam14_callouts.h | 2 - 6 files changed, 101 insertions(+), 63 deletions(-) diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c new file mode 100644 index 0000000..cc1c0a0 --- /dev/null +++ b/src/device/dram/spd_cache.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/dram/ddr3.h> +#include <cbfs.h> +#include <string.h> +#include <stdint.h> + +#define SPD_SIZE 128 +#define SPD_CRC_HI 127 +#define SPD_CRC_LO 126 + +/* FIXME: find right header */ +int read_spd_from_cbfs(u8 *buf, int idx); + +int read_spd_from_cbfs(u8 *buf, int idx) +{ + const char *spd_file; + size_t spd_file_len = 0; + size_t min_len = (idx+1) * SPD_SIZE; + + printk(BIOS_DEBUG, "read SPD\n"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); + if (!spd_file) + printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); + if (spd_file_len < min_len) + printk(BIOS_EMERG, "Missing SPD data."); + if (!spd_file || spd_file_len < min_len) + return -1; + + memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + + u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + + if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) + || (buf[SPD_CRC_LO] != (crc & 0xff)) + || (buf[SPD_CRC_HI] != (crc >> 8))) { + printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); + buf[SPD_CRC_LO] = crc & 0xff; + buf[SPD_CRC_HI] = crc >> 8; + u16 i; + printk(BIOS_WARNING, "\nDisplay the SPD"); + for (i = 0; i < SPD_SIZE; i++) { + if((i % 16) == 0x00) + printk(BIOS_WARNING, "\n%02x: ",i); + printk(BIOS_WARNING, "%02x ", buf[i]); + } + printk(BIOS_WARNING, "\n"); + } + return 0; +} diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 2efc459..da21f57 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,13 +23,6 @@ #include "heapManager.h" #include "SB800.h" #include <stdlib.h> -#include <cbfs.h> -#include <string.h> -#include <device/dram/ddr3.h> - -#define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -40,7 +32,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd_from_cbfs }, + {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -51,56 +43,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; -#ifdef __PRE_RAM__ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - char *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, - &spd_file_len); - if (!spd_file) - die("file [spd.bin] not found in CBFS"); - if (spd_file_len < SPD_SIZE) - die("Missing SPD data."); - - memcpy((char*)info->Buffer, spd_file, SPD_SIZE); - - u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE); - - if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0)) - || (info->Buffer[SPD_CRC_LO] != (crc & 0xff)) - || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); - info->Buffer[SPD_CRC_LO] = crc & 0xff; - info->Buffer[SPD_CRC_HI] = crc >> 8; - u16 i; - printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { - if((i % 16) == 0x00) - printk(BIOS_WARNING, "\n%02x: ",i); - printk(BIOS_WARNING, "%02x ", info->Buffer[i]); - } - printk(BIOS_WARNING, "\n"); - } - Status = AGESA_SUCCESS; -#else - Status = AGESA_UNSUPPORTED; -#endif - - return Status; -} - /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index 3f4224b..a6fb2e6 100755 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c romstage-y += ../../../device/dram/ddr3.c +romstage-y += ../../../device/dram/spd_cache.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 3dd77d2..3517d37 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,8 +40,6 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); } - - AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { return AGESA_UNSUPPORTED; @@ -59,6 +58,7 @@ AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } + AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; @@ -115,3 +115,29 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } #endif + +/* FIXME: find right header and Kconfig */ +#if CONFIG_BOARD_GIZMOSPHERE_GIZMO +int read_spd_from_cbfs(u8 *buf, int idx); + +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ + if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} +#endif diff --git a/src/northbridge/amd/agesa/def_callouts.h b/src/northbridge/amd/agesa/def_callouts.h index 033abc3..b679bae 100644 --- a/src/northbridge/amd/agesa/def_callouts.h +++ b/src/northbridge/amd/agesa/def_callouts.h @@ -65,6 +65,8 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); + AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); typedef struct { diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.h b/src/northbridge/amd/agesa/family14/fam14_callouts.h index c885761..f58441a 100755 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.h +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.h @@ -26,7 +26,5 @@ /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); - #endif /* CALLOUTS_AMD_AGESA_FAM14_H */

1 0

Patch set updated for coreboot: 9a3556b gizmoboard: Move support of SPD data in CBFS
by Kyösti Mälkki 07 May '14

07 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5690 -gerrit commit 9a3556b58efd2fe957ec0d412dd358abdd603f08 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 16:40:15 2014 +0300 gizmoboard: Move support of SPD data in CBFS This code is not specific to any board or AGESA family. Change-Id: I26c32fbe8e45018e239762b072dfe3da05271697 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/dram/spd_cache.c | 69 ++++++++++++++++++++++ src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 60 +------------------ src/mainboard/gizmosphere/gizmo/Makefile.inc | 1 + src/northbridge/amd/agesa/def_callouts.c | 30 +++++++++- src/northbridge/amd/agesa/def_callouts.h | 2 + .../amd/agesa/family14/fam14_callouts.h | 2 - 6 files changed, 101 insertions(+), 63 deletions(-) diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c new file mode 100644 index 0000000..cc1c0a0 --- /dev/null +++ b/src/device/dram/spd_cache.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/dram/ddr3.h> +#include <cbfs.h> +#include <string.h> +#include <stdint.h> + +#define SPD_SIZE 128 +#define SPD_CRC_HI 127 +#define SPD_CRC_LO 126 + +/* FIXME: find right header */ +int read_spd_from_cbfs(u8 *buf, int idx); + +int read_spd_from_cbfs(u8 *buf, int idx) +{ + const char *spd_file; + size_t spd_file_len = 0; + size_t min_len = (idx+1) * SPD_SIZE; + + printk(BIOS_DEBUG, "read SPD\n"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); + if (!spd_file) + printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); + if (spd_file_len < min_len) + printk(BIOS_EMERG, "Missing SPD data."); + if (!spd_file || spd_file_len < min_len) + return -1; + + memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + + u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + + if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) + || (buf[SPD_CRC_LO] != (crc & 0xff)) + || (buf[SPD_CRC_HI] != (crc >> 8))) { + printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); + buf[SPD_CRC_LO] = crc & 0xff; + buf[SPD_CRC_HI] = crc >> 8; + u16 i; + printk(BIOS_WARNING, "\nDisplay the SPD"); + for (i = 0; i < SPD_SIZE; i++) { + if((i % 16) == 0x00) + printk(BIOS_WARNING, "\n%02x: ",i); + printk(BIOS_WARNING, "%02x ", buf[i]); + } + printk(BIOS_WARNING, "\n"); + } + return 0; +} diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index 2efc459..da21f57 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -2,7 +2,6 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -24,13 +23,6 @@ #include "heapManager.h" #include "SB800.h" #include <stdlib.h> -#include <cbfs.h> -#include <string.h> -#include <device/dram/ddr3.h> - -#define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr); @@ -40,7 +32,7 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DEALLOCATE_BUFFER, agesa_DeallocateBuffer }, {AGESA_LOCATE_BUFFER, agesa_LocateBuffer }, {AGESA_DO_RESET, agesa_Reset }, - {AGESA_READ_SPD, BiosReadSpd_from_cbfs }, + {AGESA_READ_SPD, agesa_ReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, @@ -51,56 +43,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; -#ifdef __PRE_RAM__ - AGESA_READ_SPD_PARAMS *info = ConfigPtr; - if (info->MemChannelId > 0) - return AGESA_UNSUPPORTED; - if (info->SocketId != 0) - return AGESA_UNSUPPORTED; - if (info->DimmId != 0) - return AGESA_UNSUPPORTED; - - char *spd_file; - size_t spd_file_len; - - printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, - &spd_file_len); - if (!spd_file) - die("file [spd.bin] not found in CBFS"); - if (spd_file_len < SPD_SIZE) - die("Missing SPD data."); - - memcpy((char*)info->Buffer, spd_file, SPD_SIZE); - - u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE); - - if (((info->Buffer[SPD_CRC_LO] == 0) && (info->Buffer[SPD_CRC_HI] == 0)) - || (info->Buffer[SPD_CRC_LO] != (crc & 0xff)) - || (info->Buffer[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD has a invalid or zero-valued CRC\n"); - info->Buffer[SPD_CRC_LO] = crc & 0xff; - info->Buffer[SPD_CRC_HI] = crc >> 8; - u16 i; - printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { - if((i % 16) == 0x00) - printk(BIOS_WARNING, "\n%02x: ",i); - printk(BIOS_WARNING, "%02x ", info->Buffer[i]); - } - printk(BIOS_WARNING, "\n"); - } - Status = AGESA_SUCCESS; -#else - Status = AGESA_UNSUPPORTED; -#endif - - return Status; -} - /* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { diff --git a/src/mainboard/gizmosphere/gizmo/Makefile.inc b/src/mainboard/gizmosphere/gizmo/Makefile.inc index 3f4224b..a6fb2e6 100755 --- a/src/mainboard/gizmosphere/gizmo/Makefile.inc +++ b/src/mainboard/gizmosphere/gizmo/Makefile.inc @@ -30,6 +30,7 @@ romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c romstage-y += ../../../device/dram/ddr3.c +romstage-y += ../../../device/dram/spd_cache.c ramstage-y += buildOpts.c ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 3dd77d2..1a790fe 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -39,8 +40,6 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return BiosCallouts[i].CalloutPtr (Func, Data, ConfigPtr); } - - AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { return AGESA_UNSUPPORTED; @@ -59,6 +58,7 @@ AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_SUCCESS; } + AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { AGESA_STATUS Status; @@ -115,3 +115,29 @@ AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } #endif + +/* FIXME: find right header and Kconfig */ +#if CONFIG_BOARD_GIZMOSPHERE_GIZMO +int read_spd_from_cbfs(u8 *buf, int idx); + +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status = AGESA_UNSUPPORTED; +#ifdef __PRE_RAM__ + AGESA_READ_SPD_PARAMS *info = ConfigPtr; + if (info->MemChannelId > 0) + return AGESA_UNSUPPORTED; + if (info->SocketId != 0) + return AGESA_UNSUPPORTED; + if (info->DimmId != 0) + return AGESA_UNSUPPORTED; + + /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ + if (read_spd_from_cbfs((char*)info->Buffer, 0) < 0) + die("No SPD data\n"); + + Status = AGESA_SUCCESS; +#endif + return Status; +} +#endif diff --git a/src/northbridge/amd/agesa/def_callouts.h b/src/northbridge/amd/agesa/def_callouts.h index 033abc3..b679bae 100644 --- a/src/northbridge/amd/agesa/def_callouts.h +++ b/src/northbridge/amd/agesa/def_callouts.h @@ -65,6 +65,8 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_GfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *ConfigPrt); +AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); + AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr); typedef struct { diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.h b/src/northbridge/amd/agesa/family14/fam14_callouts.h index c885761..f58441a 100755 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.h +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.h @@ -26,7 +26,5 @@ /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); -AGESA_STATUS BiosReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr); - #endif /* CALLOUTS_AMD_AGESA_FAM14_H */

1 0

Patch set updated for coreboot: 3f71fa5 amd/dinar: Handle empty HOOKBEFORE_DRAM_INIT
by Kyösti Mälkki 07 May '14

07 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5683 -gerrit commit 3f71fa5ed05b5a0593ddbf72ad42ff4518fa2fc9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 6 14:10:04 2014 +0300 amd/dinar: Handle empty HOOKBEFORE_DRAM_INIT Removed function only read ACPI MMIO base address from a couple of registers in IO space. Change-Id: I25a31b7ac1706b9eebc5db0b9604039928328b0a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/BiosCallOuts.c | 30 +----------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index b869e3b..e9715ba 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -97,7 +97,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, - {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, + {AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, @@ -146,31 +146,3 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) return Status; } - -/* Call the host environment interface to provide a user hook opportunity. */ -AGESA_STATUS BiosHookBeforeDramInit (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - - FcnData = Data; - MemData = ConfigPtr; - - Status = AGESA_SUCCESS; - /* Get SB MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8<<8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - Status = AGESA_SUCCESS; - return Status; -}

1 0

Patch set updated for coreboot: 00d39b4 AGESA fam12 fam14 fam15: Common handler for AGESA_RUNFUNC_ONAP
by Kyösti Mälkki 07 May '14

07 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5682 -gerrit commit 00d39b4e33620acf8af520d9ccc8a631a581ce05 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 5 12:05:53 2014 +0300 AGESA fam12 fam14 fam15: Common handler for AGESA_RUNFUNC_ONAP Change-Id: I9f27e1e814a80864d8ca315fe816a083c55708c6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/BiosCallOuts.c | 2 +- src/mainboard/amd/inagua/BiosCallOuts.c | 2 +- src/mainboard/amd/persimmon/BiosCallOuts.c | 2 +- src/mainboard/amd/south_station/BiosCallOuts.c | 2 +- src/mainboard/amd/torpedo/BiosCallOuts.c | 2 +- src/mainboard/amd/union_station/BiosCallOuts.c | 2 +- src/mainboard/asrock/e350m1/BiosCallOuts.c | 2 +- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 2 +- src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c | 2 +- src/mainboard/lippert/frontrunner-af/BiosCallOuts.c | 2 +- src/mainboard/lippert/toucan-af/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8qgi/BiosCallOuts.c | 2 +- src/mainboard/supermicro/h8scm/BiosCallOuts.c | 2 +- src/mainboard/tyan/s8226/BiosCallOuts.c | 2 +- src/northbridge/amd/agesa/def_callouts.c | 10 ++++++++++ src/northbridge/amd/agesa/def_callouts.h | 1 + src/northbridge/amd/agesa/family12/fam12_callouts.c | 8 -------- src/northbridge/amd/agesa/family12/fam12_callouts.h | 1 - src/northbridge/amd/agesa/family14/fam14_callouts.c | 7 ------- src/northbridge/amd/agesa/family14/fam14_callouts.h | 1 - src/northbridge/amd/agesa/family15/fam15_callouts.c | 8 -------- src/northbridge/amd/agesa/family15/fam15_callouts.h | 1 - 22 files changed, 25 insertions(+), 40 deletions(-) diff --git a/src/mainboard/amd/dinar/BiosCallOuts.c b/src/mainboard/amd/dinar/BiosCallOuts.c index 90e0dc8..b869e3b 100644 --- a/src/mainboard/amd/dinar/BiosCallOuts.c +++ b/src/mainboard/amd/dinar/BiosCallOuts.c @@ -94,7 +94,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, diff --git a/src/mainboard/amd/inagua/BiosCallOuts.c b/src/mainboard/amd/inagua/BiosCallOuts.c index c370491..adb3b27 100644 --- a/src/mainboard/amd/inagua/BiosCallOuts.c +++ b/src/mainboard/amd/inagua/BiosCallOuts.c @@ -32,7 +32,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/amd/persimmon/BiosCallOuts.c b/src/mainboard/amd/persimmon/BiosCallOuts.c index aac5d11..153c939 100644 --- a/src/mainboard/amd/persimmon/BiosCallOuts.c +++ b/src/mainboard/amd/persimmon/BiosCallOuts.c @@ -32,7 +32,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/amd/south_station/BiosCallOuts.c b/src/mainboard/amd/south_station/BiosCallOuts.c index 33a409b..345d0d3 100644 --- a/src/mainboard/amd/south_station/BiosCallOuts.c +++ b/src/mainboard/amd/south_station/BiosCallOuts.c @@ -32,7 +32,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/amd/torpedo/BiosCallOuts.c b/src/mainboard/amd/torpedo/BiosCallOuts.c index dcd32e0..889f75b 100644 --- a/src/mainboard/amd/torpedo/BiosCallOuts.c +++ b/src/mainboard/amd/torpedo/BiosCallOuts.c @@ -45,7 +45,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, diff --git a/src/mainboard/amd/union_station/BiosCallOuts.c b/src/mainboard/amd/union_station/BiosCallOuts.c index 33a409b..345d0d3 100644 --- a/src/mainboard/amd/union_station/BiosCallOuts.c +++ b/src/mainboard/amd/union_station/BiosCallOuts.c @@ -32,7 +32,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index b20a045..a199152 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -38,7 +38,7 @@ CONST BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index ba953f8..1f8fb68 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -39,7 +39,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd_from_cbfs }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c index 97c9cc6..f4b8586 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/BiosCallOuts.c @@ -34,7 +34,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, BiosGnbPcieSlotReset }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c index dd6b33c..751a26a 100644 --- a/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c +++ b/src/mainboard/lippert/frontrunner-af/BiosCallOuts.c @@ -36,7 +36,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit }, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/lippert/toucan-af/BiosCallOuts.c b/src/mainboard/lippert/toucan-af/BiosCallOuts.c index 682fda0..9329837 100644 --- a/src/mainboard/lippert/toucan-af/BiosCallOuts.c +++ b/src/mainboard/lippert/toucan-af/BiosCallOuts.c @@ -37,7 +37,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GNB_PCIE_SLOT_RESET, agesa_NoopUnsupported }, {AGESA_HOOKBEFORE_DRAM_INIT, BiosHookBeforeDramInit}, {AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, agesa_NoopSuccess }, diff --git a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c index 90c0a18..0251b29 100644 --- a/src/mainboard/supermicro/h8qgi/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8qgi/BiosCallOuts.c @@ -79,7 +79,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopSuccess }, diff --git a/src/mainboard/supermicro/h8scm/BiosCallOuts.c b/src/mainboard/supermicro/h8scm/BiosCallOuts.c index 22dd07b..8e9aff5 100644 --- a/src/mainboard/supermicro/h8scm/BiosCallOuts.c +++ b/src/mainboard/supermicro/h8scm/BiosCallOuts.c @@ -33,7 +33,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopSuccess }, diff --git a/src/mainboard/tyan/s8226/BiosCallOuts.c b/src/mainboard/tyan/s8226/BiosCallOuts.c index 1d66f6d..5a711d7 100644 --- a/src/mainboard/tyan/s8226/BiosCallOuts.c +++ b/src/mainboard/tyan/s8226/BiosCallOuts.c @@ -87,7 +87,7 @@ STATIC BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_DO_RESET, agesa_Reset }, {AGESA_READ_SPD, BiosReadSpd }, {AGESA_READ_SPD_RECOVERY, agesa_NoopUnsupported }, - {AGESA_RUNFUNC_ONAP, BiosRunFuncOnAp }, + {AGESA_RUNFUNC_ONAP, agesa_RunFuncOnAp }, {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_DRAM_INIT, agesa_NoopSuccess }, diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index f0baca5..ec323b3 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -20,6 +20,7 @@ #include "AGESA.h" #include "amdlib.h" #include "Ids.h" +#include "agesawrapper.h" #include "def_callouts.h" AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr) @@ -75,3 +76,12 @@ AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr) Status = 0; return Status; } + +AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) +{ + AGESA_STATUS Status; + + Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); + return Status; +} + diff --git a/src/northbridge/amd/agesa/def_callouts.h b/src/northbridge/amd/agesa/def_callouts.h index a759adb..0fd0fbe 100644 --- a/src/northbridge/amd/agesa/def_callouts.h +++ b/src/northbridge/amd/agesa/def_callouts.h @@ -29,5 +29,6 @@ AGESA_STATUS agesa_NoopUnsupported (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_NoopSuccess (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_EmptyIdsInitData (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS agesa_Reset (UINT32 Func, UINT32 Data, VOID *ConfigPtr); +AGESA_STATUS agesa_RunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); #endif /* CALLOUTS_AMD_AGESA_H */ diff --git a/src/northbridge/amd/agesa/family12/fam12_callouts.c b/src/northbridge/amd/agesa/family12/fam12_callouts.c index 1deb094..2f8406c 100644 --- a/src/northbridge/amd/agesa/family12/fam12_callouts.c +++ b/src/northbridge/amd/agesa/family12/fam12_callouts.c @@ -332,14 +332,6 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - - Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); - return Status; -} - AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) { diff --git a/src/northbridge/amd/agesa/family12/fam12_callouts.h b/src/northbridge/amd/agesa/family12/fam12_callouts.h index 5ceac83..90a262b 100644 --- a/src/northbridge/amd/agesa/family12/fam12_callouts.h +++ b/src/northbridge/amd/agesa/family12/fam12_callouts.h @@ -47,7 +47,6 @@ void EmptyHeap(void); AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.c b/src/northbridge/amd/agesa/family14/fam14_callouts.c index 2677a47..ac309c5 100644 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.c +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.c @@ -332,13 +332,6 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - - Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); - return Status; -} AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) diff --git a/src/northbridge/amd/agesa/family14/fam14_callouts.h b/src/northbridge/amd/agesa/family14/fam14_callouts.h index 606752c..304d88c 100755 --- a/src/northbridge/amd/agesa/family14/fam14_callouts.h +++ b/src/northbridge/amd/agesa/family14/fam14_callouts.h @@ -48,7 +48,6 @@ void EmptyHeap(void); AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr); diff --git a/src/northbridge/amd/agesa/family15/fam15_callouts.c b/src/northbridge/amd/agesa/family15/fam15_callouts.c index 36491e3..74876fb 100644 --- a/src/northbridge/amd/agesa/family15/fam15_callouts.c +++ b/src/northbridge/amd/agesa/family15/fam15_callouts.c @@ -332,11 +332,3 @@ AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) } -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr) -{ - AGESA_STATUS Status; - - Status = agesawrapper_amdlaterunaptask (Func, Data, ConfigPtr); - return Status; -} - diff --git a/src/northbridge/amd/agesa/family15/fam15_callouts.h b/src/northbridge/amd/agesa/family15/fam15_callouts.h index d92c3de..8f74878 100644 --- a/src/northbridge/amd/agesa/family15/fam15_callouts.h +++ b/src/northbridge/amd/agesa/family15/fam15_callouts.h @@ -48,7 +48,6 @@ void EmptyHeap(void); AGESA_STATUS BiosAllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosDeallocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); AGESA_STATUS BiosLocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr); -AGESA_STATUS BiosRunFuncOnAp (UINT32 Func, UINT32 Data, VOID *ConfigPtr); /* AGESA ADVANCED CALLOUTS - MEMORY */ AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2014