coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 8d42bcf rambi: Add DIRQs for trackpad and touchscreen
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4963 -gerrit commit 8d42bcf1c95be30a783f563b078ee4983245337f Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Nov 8 17:23:26 2013 -0800 rambi: Add DIRQs for trackpad and touchscreen Also add the relevant info about these pins to the ASL tables + add SMBIOS type 41 data for these parts. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ regwrites w/ GPIO_DEBUG look correct. Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8 Reviewed-on: https://chromium-review.googlesource.com/176299 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/acpi/mainboard.asl | 72 +++++++++++++++++++++++++++ src/mainboard/google/rambi/gpio.c | 17 +++++-- src/mainboard/google/rambi/irqroute.h | 7 +++ src/mainboard/google/rambi/mainboard.c | 31 +++++++++++- src/mainboard/google/rambi/onboard.h | 37 ++++++++++++++ 5 files changed, 160 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 948d7df..696d1aa 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -19,6 +19,8 @@ * MA 02110-1301 USA */ +#include <mainboard/google/rambi/onboard.h> + Scope (\_SB) { Device (LID0) @@ -35,4 +37,74 @@ Scope (\_SB) { Name(_HID, EisaId("PNP0C0C")) } + + Device (TPAD) + { + Name (_ADR, 0x0) + Name (_UID, 1) + + // Report as a Sleep Button device so Linux will + // automatically enable it as a wake source + Name (_HID, EisaId("PNP0C0E")) + + Name (_CRS, ResourceTemplate() + { + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + + VendorShort (ADDR) + { + BOARD_TRACKPAD_I2C_ADDR + } + }) + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + // \_SB.PCI0.LPCB.GWAK (Local0) + } + } + } + + Device (TSCR) + { + Name (_ADR, 0x0) + Name (_UID, 2) + + // Report as a Sleep Button device so Linux will + // automatically enable it as a wake source + Name (_HID, EisaId("PNP0C0E")) + + Name (_CRS, ResourceTemplate() + { + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + + VendorShort (ADDR) + { + BOARD_TOUCHSCREEN_I2C_ADDR + } + }) + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + + Method (_DSW, 3, NotSerialized) + { + Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) + + If (LEqual (Arg0, 1)) { + // Enable GPIO as wake source + // \_SB.PCI0.LPCB.GWAK (Local0) + } + } + } } diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 9bcafad..7d44968 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -19,6 +19,7 @@ #include <stdlib.h> #include <baytrail/gpio.h> +#include "irqroute.h" /* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */ /* NCORE GPIOs */ @@ -110,7 +111,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ GPIO_DEFAULT, /* S0-SC054 - NC */ - GPIO_INPUT, /* S0-SC055 - TRACKPAD_INT_DX - INT */ + GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */ GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */ GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */ GPIO_INPUT, /* S0-SC058 - SIM_DET_C */ @@ -127,7 +128,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */ GPIO_NC, /* S0-SC071 - NC */ - GPIO_INPUT, /* S0-SC072 - TOUCH_INT_L_DX - INT */ + GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ GPIO_NC, /* S0-SC073 - NC */ GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */ GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */ @@ -209,10 +210,20 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_END }; +static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { + [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, + [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, +}; + +static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { +}; + static struct soc_gpio_config gpio_config = { .ncore = gpncore_gpio_map, .score = gpscore_gpio_map, - .ssus = gpssus_gpio_map + .ssus = gpssus_gpio_map, + .core_dirq = &core_dedicated_irq, + .sus_dirq = &sus_dedicated_irq, }; struct soc_gpio_config* mainboard_get_gpios(void) diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index 20f421b..fa7a6c3 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -45,3 +45,10 @@ PIRQ_PIC(F, DISABLE), \ PIRQ_PIC(G, DISABLE), \ PIRQ_PIC(H, DISABLE) + +/* CORE bank DIRQs - up to 16 supported */ +#define TPAD_IRQ_OFFSET 0 +#define TOUCH_IRQ_OFFSET 1 +/* Corresponding SCORE GPIO pins */ +#define TPAD_IRQ_GPIO 55 +#define TOUCH_IRQ_GPIO 72 diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 4ef8a9f..2e0652f 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -33,7 +33,9 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> +#include <smbios.h> #include "ec.h" +#include "onboard.h" void mainboard_suspend_resume(void) { @@ -119,7 +121,7 @@ static int int15_handler(void) } break; - default: + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); break; } @@ -132,12 +134,39 @@ static void mainboard_init(device_t dev) mainboard_ec_init(); } +static int mainboard_smbios_data(device_t dev, int *handle, + unsigned long *current) +{ + int len = 0; + + len += smbios_write_type41( + current, handle, + BOARD_TRACKPAD_NAME, /* name */ + BOARD_TRACKPAD_IRQ, /* instance */ + BOARD_TRACKPAD_I2C_BUS, /* segment */ + BOARD_TRACKPAD_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + len += smbios_write_type41( + current, handle, + BOARD_TOUCHSCREEN_NAME, /* name */ + BOARD_TOUCHSCREEN_IRQ, /* instance */ + BOARD_TOUCHSCREEN_I2C_BUS, /* segment */ + BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */ + 0, /* device */ + 0); /* function */ + + return len; +} + // mainboard_enable is executed as first thing after // enumerate_buses(). static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; + dev->ops->get_smbios_data = mainboard_smbios_data; #if CONFIG_VGA_ROM_RUN /* Install custom int15 handler for VGA OPROM */ mainboard_interrupt_handlers(0x15, &int15_handler); diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h new file mode 100644 index 0000000..290f58c --- /dev/null +++ b/src/mainboard/google/rambi/onboard.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef ONBOARD_H +#define ONBOARD_H + +#include "irqroute.h" + +#define BOARD_TRACKPAD_NAME "trackpad" +#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET) +#define BOARD_TRACKPAD_WAKE_GPIO 1 /* GPSSUS1 */ +#define BOARD_TRACKPAD_I2C_BUS 1 /* TODO(shawnn): Check this */ +#define BOARD_TRACKPAD_I2C_ADDR 0x67 /* TODO(shawnn): Check this */ + +#define BOARD_TOUCHSCREEN_NAME "touchscreen" +#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET) +#define BOARD_TOUCHSCREEN_WAKE_GPIO 2 /* GPSSUS2 */ +#define BOARD_TOUCHSCREEN_I2C_BUS 2 /* TODO(shawnn): Check this */ +#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ + +#endif

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Patch merged into coreboot/master: fb494d6 baytrail: gpio: Add support for direct / dedicated IRQs
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit fb494d68ff92d036adf10fb7eacf97ed9f1a4391 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Nov 8 16:43:34 2013 -0800 baytrail: gpio: Add support for direct / dedicated IRQs Add support for DirectIRQ / dedicated IRQs. This consists of up to 16 IRQs for both SCORE and SSUS banks. BUG=chrome-os-partner:22863 TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ regwrites w/ GPIO_DEBUG look correct. Change-Id: I4b0dc6e7ae86c9f554b6e78792239234f702764c Reviewed-on: https://chromium-review.googlesource.com/176165 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Tested-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4962 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4962 for details. -gerrit

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Patch merged into coreboot/master: 7e9634f rambi: disable HDA device
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 7e9634ffc0d48e471cb4c2ff521c6f4361207303 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 11 15:01:39 2013 -0600 rambi: disable HDA device For some reason HDA can now be disabled. It's unclear what changes in the baytrail code allowed this to happen, sadly. BUG=chrome-os-partner:22871 BRANCH=None TEST=Noted hda is not in lspci. Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176394 Reviewed-on: http://review.coreboot.org/4961 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4961 for details. -gerrit

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Patch merged into coreboot/master: 59cd621 rambi: enable SCI and SMI gpios
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 59cd6216dd430db7488448b0c68aa7024690e179 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 11 14:58:06 2013 -0600 rambi: enable SCI and SMI gpios Rambi has 3 pins that need to be configured for SCI and SMI: 1. GPIO_CORE[0] - runtime SCI pin 2. GPIO_SUS[7] - SMI for firmware lid events 3. GPIO_SUS[0] - wake pin for S3 wakes from EC. Configure these pins now that the rest of the infrastructure is in place. The one thing that is yet to work is runtime SCI for lid events once booted. BUG=chrome-os-partner:23505 BRANCH=None TEST=built and booted. lid close at rec screen works. And wake from S3 with a keyboard press works. Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176393 Reviewed-on: http://review.coreboot.org/4960 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4960 for details. -gerrit

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Patch merged into coreboot/master: 3fbf671 rambi: mainboard EC - SCI and SMI fixes
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 3fbf671194a8f1469bf0e122fed8e8da23893ac9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 11 14:55:47 2013 -0600 rambi: mainboard EC - SCI and SMI fixes As rambi is a baytrail board it doesn't have a dedicated wake pin. Therefore, one needs to enable the proper GPIO to wake up the sytem before going into S3. BUG=chrome-os-partner:23505 BRANCH=None TEST=Put system into S3. Keyboard press created wake event. Also, typed 'lidclose' on EC console while at recovery screen. Machine properly shutdown. Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176392 Reviewed-on: http://review.coreboot.org/4959 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4959 for details. -gerrit

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Patch merged into coreboot/master: 9f83e87 baytrail: add GPIO SMI support
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 9f83e873f4f0a06a68f68414720e837a69f54184 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 11 14:45:27 2013 -0600 baytrail: add GPIO SMI support GPIOs which trigger SMIs only set the status bits in the ALT_GPIO_SMI regier. No bits in the SMI_STS register are set. Therefore, the ALT_GPIO_SMI register needs to be read and cleared on every SMI. Additionally, the mainboard_gpi_smi() handler needs to be called as well on every SMI because of this property. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted to recovery screen. Typed 'lidclose' on EC console. SMI occurred which caused the board to be shutdown. Change-Id: Ic204d8b928a0cb4f51f108a649f374d9f94e4f47 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176391 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4958 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4958 for details. -gerrit

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Patch merged into coreboot/master: 59a4cd5 baytrail: add support for routing gpio pins to smi/sci
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 59a4cd55782f1148d37f0c2408657ba93deefc86 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 11 12:09:28 2013 -0600 baytrail: add support for routing gpio pins to smi/sci In order for gpio pins to trigger an smi/sci the GPIO_ROUT register needs to be set accordingly. For SMI, the ALT_GPIO_SMI register needs to be enabled for each gpio as well. The first 8 gpios from the suspend and core well are the only gpios that can trigger an SMI or SCI. The settings for the GPIO_ROUT and ALT_GPIO_SMI register are not commited until the SMM settings are enabled in the southcluster. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Manually triggered SCI by changing GPE0a_EN and toggling PCH_WAKE_L on the EC console. Change-Id: Id79b70084edc39fc047475e984494c224bd75d6d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176390 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4957 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4957 for details. -gerrit

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Patch merged into coreboot/master: 997d252 baytrail: fix fadt structure for gpe0 block
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 997d25219b67704ba497a3d67f392a8a743a1782 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 8 17:37:48 2013 -0600 baytrail: fix fadt structure for gpe0 block The gpe0 block's size was being misreported. Correct the gpe0 size and use make the FADT fields be more robust instead instead of hand calculating fields that are the based on the same size. This change correctly enables GPE events in the kernel. Confirmed this by using iotools read the gpe_cnt register. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Confirmed EC's GPE event is enabled (but still not working). Change-Id: I415710f7fec2e95cecee3bf679ee673dacc27480 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176271 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4956 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4956 for details. -gerrit

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Patch merged into coreboot/master: ea7d4e0 baytrail: Add microcode/punit release 31a
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit ea7d4e0901e8ebfb2fe520ba3814c41138aaeb26 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 8 23:02:20 2013 -0800 baytrail: Add microcode/punit release 31a BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi Change-Id: I89c25142245cd268f755210784fd9d0c60dc5661 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176305 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4955 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4955 for details. -gerrit

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Patch merged into coreboot/master: 8923be5 baytrail: Add ACPI CPU entries
by gerrit＠coreboot.org 06 May '14

06 May '14

the following patch was just integrated into master: commit 8923be58b87cbf55f5765eca6ce29d7b6827be97 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Nov 5 13:02:30 2013 -0800 baytrail: Add ACPI CPU entries - C-state table based on static config MWAIT values are from ref code for non-S0ix config C6 substate 8 is ignored by the kernel as it violates the CPUID but it is left in as the other substate may not work. - P-state table generated with proper ratio and VID values relies on having the package power msr set to magic value as the power-on default is wrong - T-state table uses static table BUG=chrome-os-partner:23505 BRANCH=rambi TEST=build and boot on rambi Change-Id: I7c997e58cb3a71d0ec413b17f0c5467bef4bf62c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175742 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4954 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/4954 for details. -gerrit

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coreboot-gerrit May 2014