the following patch was just integrated into master:
commit 6aa9f1f0eb97e315ab4db8e6da1d13db7ee7858f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Thu Nov 7 12:47:35 2013 -0800
baytrail: Add BCLK and IACORE to pattrs
The bus clock speed is needed when building ACPI P-state tables
so extract that function and have the value be saved in pattrs.
The various IACORE values are also needed, but rather than have
the ACPI code to the bit manipulation have the pattrs store an
array of the possible values for it to use directly.
BUG=chrome-os-partner:23505
BRANCH=none
TEST=build and boot on rambi
Change-Id: I5ac06ccf66e9109186dd01342dbb6ccdd334ca69
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176140
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Commit-Queue: Aaron Durbin <adurbin(a)chromium.org>
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/4953
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/4953 for details.
-gerrit
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5576
-gerrit
commit 259c23dda4b45d29626595134a45f41558841a0d
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Thu Apr 24 02:58:11 2014 +1000
superio/fintek/f71869ad: Configure multi-func reg in devicetree
Facilitate for the configuration of so called "Multi-function Select
Registers" with devicetree.cb in ramstage.
Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
mode. This allows the Fintek to correctly talk to the Southbridge over
the SMBus for CPU temperature data as to control fans and so on.
Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/devicetree.cb | 5 ++
src/superio/fintek/f71869ad/Makefile.inc | 1 +
src/superio/fintek/f71869ad/chip.h | 8 ++++
src/superio/fintek/f71869ad/f71869ad_multifunc.c | 60 ++++++++++++++++++++++++
src/superio/fintek/f71869ad/fintek_internal.h | 29 ++++++++++++
src/superio/fintek/f71869ad/superio.c | 4 ++
6 files changed, 107 insertions(+)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
index 6c26f75..1c8853d 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
+++ b/src/mainboard/jetway/nf81-t56n-lf/devicetree.cb
@@ -56,6 +56,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.2 on end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
chip superio/fintek/f71869ad
+ register "multi_function_register_1" = "0x01"
+ register "multi_function_register_2" = "0x6f"
+ register "multi_function_register_3" = "0x24"
+ register "multi_function_register_4" = "0x00"
+ register "multi_function_register_5" = "0x60"
# XXX: 4e is the default index port and .xy is the
# LDN indexing the pnp_info array found in the superio.c
# NB: Jetway board changes the default (0x4e) index port to (0x2e) by pin 124,
diff --git a/src/superio/fintek/f71869ad/Makefile.inc b/src/superio/fintek/f71869ad/Makefile.inc
index 117239a..87d96e4 100644
--- a/src/superio/fintek/f71869ad/Makefile.inc
+++ b/src/superio/fintek/f71869ad/Makefile.inc
@@ -18,4 +18,5 @@
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
+ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += f71869ad_multifunc.c
ramstage-$(CONFIG_SUPERIO_FINTEK_F71869AD) += superio.c
diff --git a/src/superio/fintek/f71869ad/chip.h b/src/superio/fintek/f71869ad/chip.h
index ea2ee6e..5011383 100644
--- a/src/superio/fintek/f71869ad/chip.h
+++ b/src/superio/fintek/f71869ad/chip.h
@@ -22,9 +22,17 @@
#define SUPERIO_FINTEK_F71869AD_CHIP_H
#include <pc80/keyboard.h>
+#include <stdint.h>
struct superio_fintek_f71869ad_config {
struct pc_keyboard keyboard;
+
+ /* Member variables are defined in devicetree.cb. */
+ uint8_t multi_function_register_1;
+ uint8_t multi_function_register_2;
+ uint8_t multi_function_register_3;
+ uint8_t multi_function_register_4;
+ uint8_t multi_function_register_5;
};
#endif /* SUPERIO_FINTEK_F71869AD_CHIP_H */
diff --git a/src/superio/fintek/f71869ad/f71869ad_multifunc.c b/src/superio/fintek/f71869ad/f71869ad_multifunc.c
new file mode 100644
index 0000000..46c4d2c
--- /dev/null
+++ b/src/superio/fintek/f71869ad/f71869ad_multifunc.c
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include "chip.h"
+#include "fintek_internal.h"
+
+#define MULTI_FUNC_SEL_REG1 0x28
+#define MULTI_FUNC_SEL_REG2 0x29
+#define MULTI_FUNC_SEL_REG3 0x2A
+#define MULTI_FUNC_SEL_REG4 0x2B
+#define MULTI_FUNC_SEL_REG5 0x2C
+
+void f71869ad_multifunc_init(device_t dev)
+{
+ struct superio_fintek_f71869ad_config *conf = dev->chip_info;
+
+ pnp_enter_conf_mode(dev);
+
+ /* multi-func select reg1 */
+ pnp_write_config(dev, MULTI_FUNC_SEL_REG1,
+ conf->multi_function_register_1);
+
+ /* multi-func select reg2 (CLK_TUNE_EN=0) */
+ pnp_write_config(dev, MULTI_FUNC_SEL_REG2,
+ conf->multi_function_register_2);
+
+ /* multi-func select reg3 (CLK_TUNE_EN=0) */
+ pnp_write_config(dev, MULTI_FUNC_SEL_REG3,
+ conf->multi_function_register_3);
+
+ /* multi-func select reg4 (CLK_TUNE_EN=0) */
+ pnp_write_config(dev, MULTI_FUNC_SEL_REG4,
+ conf->multi_function_register_4);
+
+ /* multi-func select reg5 (CLK_TUNE_EN=0) */
+ pnp_write_config(dev, MULTI_FUNC_SEL_REG5,
+ conf->multi_function_register_5);
+
+ pnp_exit_conf_mode(dev);
+}
diff --git a/src/superio/fintek/f71869ad/fintek_internal.h b/src/superio/fintek/f71869ad/fintek_internal.h
new file mode 100644
index 0000000..86f5669
--- /dev/null
+++ b/src/superio/fintek/f71869ad/fintek_internal.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef SUPERIO_FINTEK_F71869AD_INTERNAL_H
+#define SUPERIO_FINTEK_F71869AD_INTERNAL_H
+
+#include <arch/io.h>
+#include <device/pnp.h>
+
+void f71869ad_multifunc_init(device_t dev);
+
+#endif /* SUPERIO_FINTEK_F71869AD_INTERNAL_H */
diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c
index 11ad6f8..770a712 100644
--- a/src/superio/fintek/f71869ad/superio.c
+++ b/src/superio/fintek/f71869ad/superio.c
@@ -25,6 +25,7 @@
#include <console/console.h>
#include <stdlib.h>
+#include "fintek_internal.h"
#include "chip.h"
#include "f71869ad.h"
@@ -40,6 +41,9 @@ static void f71869ad_init(device_t dev)
case F71869AD_KBC:
pc_keyboard_init(&conf->keyboard);
break;
+ case F71869AD_HWM:
+ f71869ad_multifunc_init(dev);
+ break;
}
}
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4959
-gerrit
commit 6d00943c56e0c6ea07cce15611646d7857d1a5d5
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Mon Nov 11 14:55:47 2013 -0600
rambi: mainboard EC - SCI and SMI fixes
As rambi is a baytrail board it doesn't have a dedicated wake pin.
Therefore, one needs to enable the proper GPIO to wake up the sytem
before going into S3.
BUG=chrome-os-partner:23505
BRANCH=None
TEST=Put system into S3. Keyboard press created wake event. Also, typed
'lidclose' on EC console while at recovery screen. Machine properly
shutdown.
Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176392
---
src/mainboard/google/rambi/ec.c | 1 +
src/mainboard/google/rambi/mainboard_smi.c | 13 ++++++++++---
2 files changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/mainboard/google/rambi/ec.c b/src/mainboard/google/rambi/ec.c
index 04a9931..a6d2161 100644
--- a/src/mainboard/google/rambi/ec.c
+++ b/src/mainboard/google/rambi/ec.c
@@ -42,6 +42,7 @@ void mainboard_ec_init(void)
} else {
google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
MAINBOARD_EC_S5_WAKE_EVENTS);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
}
/* Clear wake events, these are enabled on entry to sleep */
diff --git a/src/mainboard/google/rambi/mainboard_smi.c b/src/mainboard/google/rambi/mainboard_smi.c
index ac5c841..09a8580 100644
--- a/src/mainboard/google/rambi/mainboard_smi.c
+++ b/src/mainboard/google/rambi/mainboard_smi.c
@@ -28,6 +28,9 @@
#include <baytrail/nvs.h>
#include <baytrail/pmc.h>
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
int mainboard_io_trap_handler(int smif)
{
switch (smif) {
@@ -67,7 +70,7 @@ static uint8_t mainboard_smi_ec(void)
/* Go to S5 */
pm1_cnt = inl(pmbase + PM1_CNT);
- pm1_cnt |= SLP_TYP | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+ pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
outl(pm1_cnt, pmbase + PM1_CNT);
break;
}
@@ -75,9 +78,11 @@ static uint8_t mainboard_smi_ec(void)
return cmd;
}
-void mainboard_smi_gpi(uint32_t gpi_sts)
+/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits. */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
{
- if (gpi_sts & (1 << EC_SMI_GPI)) {
+ if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
/* Process all pending events */
while (mainboard_smi_ec() != 0);
}
@@ -97,6 +102,8 @@ void mainboard_smi_sleep(uint8_t slp_typ)
/* Enable wake events */
google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+ /* Enable wake pin in GPE block. */
+ enable_gpe(WAKE_GPIO_EN);
break;
case 5:
if (smm_get_gnvs()->s5u0 == 0)