coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: c8938ab regscript: Add support for MSR type
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4951 -gerrit commit c8938abe7009eab73560c2d7c8d14b1ec9d0b641 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Nov 8 23:00:24 2013 -0800 regscript: Add support for MSR type This required changing value/mask types to uint64_t. Another option would be to use id field to select low or high 32 bits of the MSR and set them independently. BUG=chrome-os-partner:23505 BRANCH=none TEST=build and boot on rambi Change-Id: Ied9998058a8035bf3f003185236f3be3e0df7fc9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176304 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/reg_script.h | 26 ++++++++++- src/lib/reg_script.c | 116 +++++++++++++++++++++++++++++++---------------- 2 files changed, 102 insertions(+), 40 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 18eda0c..81a4648 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -59,12 +59,14 @@ enum { REG_SCRIPT_TYPE_MMIO, REG_SCRIPT_TYPE_RES, REG_SCRIPT_TYPE_IOSF, + REG_SCRIPT_TYPE_MSR, }; enum { REG_SCRIPT_SIZE_8, REG_SCRIPT_SIZE_16, REG_SCRIPT_SIZE_32, + REG_SCRIPT_SIZE_64, }; struct reg_script { @@ -72,8 +74,8 @@ struct reg_script { uint32_t type; uint32_t size; uint32_t reg; - uint32_t mask; - uint32_t value; + uint64_t mask; + uint64_t value; uint32_t timeout; union { uint32_t id; @@ -290,6 +292,26 @@ struct reg_script { REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_) /* + * CPU Model Specific Register + */ + +#define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \ + _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, \ + REG_SCRIPT_TYPE_MSR, \ + REG_SCRIPT_SIZE_64, \ + reg_, mask_, value_, timeout_, 0) +#define REG_MSR_READ(reg_) \ + REG_SCRIPT_MSR(READ, reg_, 0, 0, 0) +#define REG_MSR_WRITE(reg_, value_) \ + REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0) +#define REG_MSR_RMW(reg_, mask_, value_) \ + REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0) +#define REG_MSR_OR(reg_, value_) \ + REG_MSR_RMW(reg_, -1ULL, value_) +#define REG_MSR_POLL(reg_, mask_, value_, timeout_) \ + REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_) + +/* * Chain to another table. */ #define REG_SCRIPT_NEXT(next_) \ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index 252aa12..3ca0b4a 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -26,6 +26,10 @@ #include <stdint.h> #include <reg_script.h> +#if CONFIG_ARCH_X86 +#include <cpu/x86/msr.h> +#endif + #if CONFIG_SOC_INTEL_BAYTRAIL #include <baytrail/iosf.h> #endif @@ -285,7 +289,31 @@ static void reg_script_write_iosf(struct reg_script_context *ctx) #endif } -static uint32_t reg_script_read(struct reg_script_context *ctx) +static uint64_t reg_script_read_msr(struct reg_script_context *ctx) +{ +#if CONFIG_ARCH_X86 + const struct reg_script *step = reg_script_get_step(ctx); + msr_t msr = rdmsr(step->reg); + uint64_t value = msr.hi; + value = msr.hi; + value <<= 32; + value |= msr.lo; + return value; +#endif +} + +static void reg_script_write_msr(struct reg_script_context *ctx) +{ +#if CONFIG_ARCH_X86 + const struct reg_script *step = reg_script_get_step(ctx); + msr_t msr; + msr.hi = step->value >> 32; + msr.lo = step->value & 0xffffffff; + wrmsr(step->reg, msr); +#endif +} + +static uint64_t reg_script_read(struct reg_script_context *ctx) { const struct reg_script *step = reg_script_get_step(ctx); @@ -300,6 +328,8 @@ static uint32_t reg_script_read(struct reg_script_context *ctx) return reg_script_read_res(ctx); case REG_SCRIPT_TYPE_IOSF: return reg_script_read_iosf(ctx); + case REG_SCRIPT_TYPE_MSR: + return reg_script_read_msr(ctx); } return 0; } @@ -324,12 +354,15 @@ static void reg_script_write(struct reg_script_context *ctx) case REG_SCRIPT_TYPE_IOSF: reg_script_write_iosf(ctx); break; + case REG_SCRIPT_TYPE_MSR: + reg_script_write_msr(ctx); + break; } } static void reg_script_rmw(struct reg_script_context *ctx) { - uint32_t value; + uint64_t value; const struct reg_script *step = reg_script_get_step(ctx); struct reg_script write_step = *step; @@ -349,50 +382,57 @@ static void reg_script_rmw(struct reg_script_context *ctx) static void reg_script_run_next(struct reg_script_context *ctx, const struct reg_script *step); -static void reg_script_run_with_context(struct reg_script_context *ctx) + +static void reg_script_run_step(struct reg_script_context *ctx, + const struct reg_script *step) { - uint32_t value = 0, try; + uint64_t value = 0, try; + switch (step->command) { + case REG_SCRIPT_COMMAND_READ: + (void)reg_script_read(ctx); + break; + case REG_SCRIPT_COMMAND_WRITE: + reg_script_write(ctx); + break; + case REG_SCRIPT_COMMAND_RMW: + reg_script_rmw(ctx); + break; + case REG_SCRIPT_COMMAND_POLL: + for (try = 0; try < step->timeout; try += POLL_DELAY) { + value = reg_script_read(ctx) & step->mask; + if (value == step->value) + break; + udelay(POLL_DELAY); + } + if (try >= step->timeout) + printk(BIOS_WARNING, "%s: POLL timeout waiting for " + "0x%x to be 0x%lx, got 0x%lx\n", __func__, + step->reg, (unsigned long)step->value, + (unsigned long)value); + break; + case REG_SCRIPT_COMMAND_SET_DEV: + reg_script_set_dev(ctx, step->dev); + break; + case REG_SCRIPT_COMMAND_NEXT: + reg_script_run_next(ctx, step->next); + break; + default: + printk(BIOS_WARNING, "Invalid command: %08x\n", + step->command); + break; + } +} + +static void reg_script_run_with_context(struct reg_script_context *ctx) +{ while (1) { const struct reg_script *step = reg_script_get_step(ctx); if (step->command == REG_SCRIPT_COMMAND_END) break; - switch (step->command) { - case REG_SCRIPT_COMMAND_READ: - (void)reg_script_read(ctx); - break; - case REG_SCRIPT_COMMAND_WRITE: - reg_script_write(ctx); - break; - case REG_SCRIPT_COMMAND_RMW: - reg_script_rmw(ctx); - break; - case REG_SCRIPT_COMMAND_POLL: - for (try = 0; try < step->timeout; try += POLL_DELAY) { - value = reg_script_read(ctx) & step->mask; - if (value == step->value) - break; - udelay(POLL_DELAY); - } - if (try >= step->timeout) - printk(BIOS_WARNING, "%s: POLL timeout waiting " - "for 0x%08x to be 0x%08x, got 0x%08x\n", - __func__, step->reg, step->value, value); - break; - case REG_SCRIPT_COMMAND_SET_DEV: - reg_script_set_dev(ctx, step->dev); - break; - case REG_SCRIPT_COMMAND_NEXT: - reg_script_run_next(ctx, step->next); - break; - default: - printk(BIOS_WARNING, "Invalid command: %08x\n", - step->command); - break; - } - + reg_script_run_step(ctx, step); reg_script_set_step(ctx, step + 1); } }

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Patch set updated for coreboot: c9217fb rambi: include the EC devices normally on superio
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4950 -gerrit commit c9217fbc26ba70dde12dcd535f0cdf7afc4f03e0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 08:13:58 2013 -0600 rambi: include the EC devices normally on superio The superio.asl file allows for the mainboard to hang devices off of the LPC bus in ACPI. Include the keyboard controller, EC memory map, and host interface's resources. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted resource reservations in dmesg. Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176134 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/acpi/superio.asl | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/acpi/superio.asl b/src/mainboard/google/rambi/acpi/superio.asl index 9092a6c..f40611c 100644 --- a/src/mainboard/google/rambi/acpi/superio.asl +++ b/src/mainboard/google/rambi/acpi/superio.asl @@ -17,4 +17,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Values should match those defined in devicetree.cb */ +/* mainboard configuration */ +#include <mainboard/google/rambi/ec.h> + +#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources +#define SIO_EC_HOST_ENABLE // EC Host Interface Resources +#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard + +/* ACPI code for EC SuperIO functions */ +#include <ec/google/chromeec/acpi/superio.asl>

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Patch set updated for coreboot: f43d009 rambi: mirror bayleybay's eMMC gpio setup
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4945 -gerrit commit f43d009afba9fde5c1f5882ab60c5dbbfc92a887 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 08:15:07 2013 -0600 rambi: mirror bayleybay's eMMC gpio setup These changes to the eMMC pads allows the kernel to see the eMMC device. One is able to install onto the eMMC device, and the kernel is loaded and booted from eMMC device. Note, that it may not fully boot because of other issues such as not-completely working ACPI support. BUG=chrome-os-partner:22580 BRANCH=None TEST=booted off of usb drive. can see eMMC device. Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176073 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 9919d30..ad1da09 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -71,17 +71,17 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC013 - NC */ GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ - GPIO_FUNC3, /* S0-SC016 - MMC1_CLK */ - GPIO_FUNC3, /* S0-SC017 - MMC1_D[0] */ - GPIO_FUNC3, /* S0-SC018 - MMC1_D[1] */ - GPIO_FUNC3, /* S0-SC019 - MMC1_D[2] */ - GPIO_FUNC3, /* S0-SC020 - MMC1_D[3] */ - GPIO_FUNC3, /* S0-SC021 - MMC1_D[4] */ - GPIO_FUNC3, /* S0-SC022 - MMC1_D[5] */ - GPIO_FUNC3, /* S0-SC023 - MMC1_D[6] */ - GPIO_FUNC3, /* S0-SC024 - MMC1_D[7] */ - GPIO_FUNC3, /* S0-SC025 - MMC1_CMD */ - GPIO_FUNC3, /* S0-SC026 - MMC1_RST */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 10K), /* S0-SC026 - MMC1_45_RST */ GPIO_NC, /* S0-SC027 - NC */ GPIO_NC, /* S0-SC028 - NC */ GPIO_NC, /* S0-SC029 - NC */

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Patch set updated for coreboot: 5ca3aaa rambi: Fix eDP panel functionality
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4944 -gerrit commit 5ca3aaad97355851d0420775afb9095428bd4142 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Nov 6 10:58:46 2013 -0800 rambi: Fix eDP panel functionality For some mysterious reason GPIO_S0_NC22 is making the eDP panel go entirely white when it is configured with internal pullup. Since these (supposedly XDP related) pins are unknown functionality lets set them to GPIO_DEFAULT instead of GPIO_NC. Additionally the VBIOS is being changed to issue int15 callback to determine the boot graphics device. If we list both LFP and EFP then the dev/rec screens will show on the panel when HDMI is not attached and otherwise will display on HDMI. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi, see firmware/kernel screens on the panel when HDMI is not attached, and firmware screens on the panel and kernel screens on both when HDMI is attached. Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175952 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 18 +++++++++--------- src/mainboard/google/rambi/mainboard.c | 2 +- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index d7082be..9919d30 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -38,15 +38,15 @@ static const struct soc_gpio_map gpncore_gpio_map[] = { GPIO_NC, /* S0_NC12 - NC */ GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */ GPIO_NC, /* S0_NC14 - NC */ - GPIO_NC, /* S0_NC15 - XDP_GPIO_S0_NC15 */ - GPIO_NC, /* S0_NC16 - XDP_GPIO_S0_NC16 */ - GPIO_NC, /* S0_NC17 - XDP_GPIO_S0_NC17 */ - GPIO_NC, /* S0_NC18 - XDP_GPIO_S0_NC18 */ - GPIO_NC, /* S0_NC19 - XDP_GPIO_S0_NC19 */ - GPIO_NC, /* S0_NC20 - XDP_GPIO_S0_NC20 */ - GPIO_NC, /* S0_NC21 - XDP_GPIO_S0_NC21 */ - GPIO_NC, /* S0_NC22 - XDP_GPIO_S0_NC22 */ - GPIO_NC, /* S0_NC23 - XDP_GPIO_S0_NC23 */ + GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */ + GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */ + GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */ + GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */ + GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */ + GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */ + GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */ + GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */ + GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */ GPIO_NC, /* S0_NC24 - NC */ GPIO_NC, /* S0_NC25 - NC */ GPIO_NC, /* S0_NC26 - NC */ diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 8c5b666..4ef8a9f 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -75,7 +75,7 @@ static int int15_handler(void) * bit 7 = LFP2 */ X86_AX = 0x005f; - X86_CX = 0x0000; + X86_CX = 0x0006; res = 1; break; case 0x5f51:

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Patch set updated for coreboot: 1726628 baytrail: add more irq defintions
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4947 -gerrit commit 172662861db4aedb4b9d54b433b274b1ea32e2ed Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 10:47:01 2013 -0600 baytrail: add more irq defintions The IRQs used for devices that are in acpi mode are added as well as the IRQ defitions for the dedicated GPIO IRQ routing. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built. Change-Id: I2eed5a4584e2d908c32617c9289a2abeaa30bd44 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176120 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/irq.h | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h index 6461878..2359d21 100644 --- a/src/soc/intel/baytrail/baytrail/irq.h +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -28,7 +28,33 @@ #define PIRQF_APIC_IRQ 21 #define PIRQG_APIC_IRQ 22 #define PIRQH_APIC_IRQ 23 +/* The below IRQs are for when devices are in ACPI mode. Active low. */ +#define LPE_DMA0_IRQ 24 +#define LPE_DMA1_IRQ 25 +#define LPE_SSP0_IRQ 26 +#define LPE_SSP1_IRQ 27 +#define LPE_SSP2_IRQ 28 +#define LPE_IPC2HOST_IRQ 29 +#define LPSS_I2C1_IRQ 32 +#define LPSS_I2C2_IRQ 33 +#define LPSS_I2C3_IRQ 34 +#define LPSS_I2C4_IRQ 35 +#define LPSS_I2C5_IRQ 36 +#define LPSS_I2C6_IRQ 37 +#define LPSS_I2C7_IRQ 38 +#define LPSS_HSUART1_IRQ 39 +#define LPSS_HSUART2_IRQ 40 +#define LPSS_SPI_IRQ 41 +#define LPSS_DMA2_IRQ 42 +#define LPSS_DMA1_IRQ 43 +#define SCC_EMMC_IRQ 45 +#define SCC_SDIO_IRQ 46 +#define SCC_SD_IRQ 47 +/* The dedicated gpio irqs are active high. */ +#define GPIO_S0_DED_IRQ(slot) (51 + (slot)) +#define GPIO_S5_DED_IRQ(slot) (67 + (slot)) +/* PIC IRQ settings. */ #define PIRQ_PIC_IRQDISABLE 0x0 #define PIRQ_PIC_IRQ3 0x3 #define PIRQ_PIC_IRQ4 0x4

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Patch set updated for coreboot: 9e43a6a baytrail: configure acpi SCI irq
by Aaron Durbin 06 May '14

06 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4946 -gerrit commit 9e43a6a25e337160905be83b50b00c68900701ea Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Nov 7 10:42:16 2013 -0600 baytrail: configure acpi SCI irq Baytrail has a configurable SCI irq. Add support for properly configuring SCI irq. Note that it is currently fixed to IRQ9, but the code supports setting it to the other supported values. The current mainboards using baytrail defer the madt IRQ override information to the chipset. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted. Noted 'SCI is IRQ9' message. Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/176075 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/rambi/acpi_tables.c | 6 +--- src/soc/intel/baytrail/acpi.c | 61 +++++++++++++++++++++++++++++++- src/soc/intel/baytrail/baytrail/acpi.h | 1 + src/soc/intel/baytrail/baytrail/irq.h | 11 ++++++ src/soc/intel/baytrail/southcluster.c | 4 +++ 5 files changed, 77 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index f61db1d..a4754f1 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -78,11 +78,7 @@ unsigned long acpi_fill_madt(unsigned long current) current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, IO_APIC_ADDR, 0); - /* INT_SRC_OVR */ - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 0, 2, 0); - current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) - current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + current = acpi_madt_irq_overrides(current); return current; } diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index e2e4937..ce7f5e4 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -20,14 +20,51 @@ #include <arch/acpi.h> #include <arch/acpigen.h> +#include <arch/io.h> +#include <arch/smp/mpspec.h> +#include <console/console.h> #include <cpu/x86/smm.h> #include <types.h> #include <string.h> #include <baytrail/acpi.h> #include <baytrail/iomap.h> +#include <baytrail/irq.h> #include <baytrail/pmc.h> +static int acpi_sci_irq(void) +{ + const unsigned long actl = ILB_BASE_ADDRESS + ACTL; + int scis; + static int sci_irq; + + if (sci_irq) + return sci_irq; + + /* Determine how SCI is routed. */ + scis = read32(actl) & SCIS_MASK; + switch (scis) { + case SCIS_IRQ9: + case SCIS_IRQ10: + case SCIS_IRQ11: + sci_irq = scis - SCIS_IRQ9 + 9; + break; + case SCIS_IRQ20: + case SCIS_IRQ21: + case SCIS_IRQ22: + case SCIS_IRQ23: + sci_irq = scis - SCIS_IRQ20 + 20; + break; + default: + printk(BIOS_DEBUG, "Invalid SCI route! Defaulting to IRQ9.\n"); + sci_irq = 9; + break; + } + + printk(BIOS_DEBUG, "SCI is IRQ%d\n", sci_irq); + return sci_irq; +} + void acpi_create_intel_hpet(acpi_hpet_t * hpet) { acpi_header_t *header = &(hpet->header); @@ -70,7 +107,7 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) { const uint16_t pmbase = ACPI_BASE_ADDRESS; - fadt->sci_int = 0x9; + fadt->sci_int = acpi_sci_irq(); fadt->smi_cmd = APM_CNT; fadt->acpi_enable = APM_CNT_ACPI_ENABLE; fadt->acpi_disable = APM_CNT_ACPI_DISABLE; @@ -175,3 +212,25 @@ void acpi_fill_in_fadt(acpi_fadt_t *fadt) fadt->x_gpe1_blk.addrh = 0x0; } + +unsigned long acpi_madt_irq_overrides(unsigned long current) +{ + int sci_irq = acpi_sci_irq(); + acpi_madt_irqoverride_t *irqovr; + uint16_t sci_flags = MP_IRQ_TRIGGER_LEVEL; + + /* INT_SRC_OVR */ + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, 0, 2, 0); + + if (sci_irq >= 20) + sci_flags |= MP_IRQ_POLARITY_LOW; + else + sci_flags |= MP_IRQ_POLARITY_HIGH; + + irqovr = (void *)current; + current += acpi_create_madt_irqoverride(irqovr, 0, sci_irq, sci_irq, + sci_flags); + + return current; +} diff --git a/src/soc/intel/baytrail/baytrail/acpi.h b/src/soc/intel/baytrail/baytrail/acpi.h index bfb7d40..da5f406 100644 --- a/src/soc/intel/baytrail/baytrail/acpi.h +++ b/src/soc/intel/baytrail/baytrail/acpi.h @@ -24,6 +24,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_fill_in_fadt(acpi_fadt_t *fadt); +unsigned long acpi_madt_irq_overrides(unsigned long current); #endif /* _BAYTRAIL_ACPI_H_ */ diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h index d037b89..6461878 100644 --- a/src/soc/intel/baytrail/baytrail/irq.h +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -52,6 +52,17 @@ #define PIRQG 6 #define PIRQH 7 +/* These registers live behind the ILB_BASE_ADDRESS */ +#define ACTL 0x00 +# define SCIS_MASK 0x07 +# define SCIS_IRQ9 0x00 +# define SCIS_IRQ10 0x01 +# define SCIS_IRQ11 0x02 +# define SCIS_IRQ20 0x04 +# define SCIS_IRQ21 0x05 +# define SCIS_IRQ22 0x06 +# define SCIS_IRQ23 0x07 + /* In each mainbaord directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which * consist of PCI_DEV_PIRQ_ROUTE and PIRQ_PIC entries. */ diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 10c0b89..b7cf4e5 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -122,6 +122,7 @@ static void sc_init(device_t dev) int i; const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08; const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20; + const unsigned long actl = ILB_BASE_ADDRESS + ACTL; const struct baytrail_irq_route *ir = &global_baytrail_irq_route; /* Set up the PIRQ PIC routing based on static config. */ @@ -132,6 +133,9 @@ static void sc_init(device_t dev) for (i = 0; i < NUM_IR_DEVS; i++) { write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]); } + + /* Route SCI to IRQ9 */ + write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); } /*

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Patch merged into coreboot/master: 303525b baytrail: fix up FADT
by gerrit＠coreboot.org 05 May '14

05 May '14

the following patch was just integrated into master: commit 303525b446469157ede480ca61aa6c14bb774eb9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 5 11:42:32 2013 -0600 baytrail: fix up FADT The FADT for baytrail had incorrect offsets leading to the kernel spewing a huge mess of ACPI errors. Fix these offsets to be initialized in the chipset code. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted into kernel on rambi. Login screen comes up. Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175663 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4941 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/4941 for details. -gerrit

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Patch merged into coreboot/master: 3bde3d7 baytrail: interrupt routing support
by gerrit＠coreboot.org 05 May '14

05 May '14

the following patch was just integrated into master: commit 3bde3d74c5574d7855d1845130bdd357bd2cb7e4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Nov 4 21:45:52 2013 -0600 baytrail: interrupt routing support This provides the initial support for interrupt routing in bay trail. It includes both acpi changes and board changes to ensure the interdependencies are met with the current ASL code. The PIRQ routing is handled by the mainboard exporting an irqroute.h header that describes the per device and PIRQ PCI settings. There are still a lot of ACPI errors in the kernel with this change, though. BUG=chrome-os-partner:23505 BRANCH=None TEST=Built and booted rambi into kernel. Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e Reviewed-on: https://chromium-review.googlesource.com/175700 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4940 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/4940 for details. -gerrit

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Patch merged into coreboot/master: 014baea haswell: move to mp_init library
by gerrit＠coreboot.org 05 May '14

05 May '14

the following patch was just integrated into master: commit 014baea1ceda67aa5df8bb4fbf20782893915f81 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Mar 28 22:01:05 2014 -0500 haswell: move to mp_init library The mp_init library was based off of haswell code, but baytrail was the first chipset to take advantage of it. Move haswell over to using it so that the code duplication can be removed. Change-Id: Id6e9464df028aa6ec138051f925817c85b4c13e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5413 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/5413 for details. -gerrit

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New patch to review for coreboot: 2f9e060 mainboard/jetway/nf81-t56n-lf: Disable ALIB SSDT in acpi_tables.c
by Edward O'Callaghan 05 May '14

05 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5665 -gerrit commit 2f9e0603375ac91ca568c9d8c18e5e7ad9e51c0b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 04:52:06 2014 +1000 mainboard/jetway/nf81-t56n-lf: Disable ALIB SSDT in acpi_tables.c The ALIB SSDT found in AGESA is a binary blob compiled with the Microsoft DSDT compiler suite. It has in fact syntax errors and is invalid. Thus we disable building a image with it by default until this has been corrected in AGESA itself. Change-Id: If4b60122762bfa3a1a482d2374d6fb035fb4c1b4 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c index 63cdb52..23932fa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c +++ b/src/mainboard/jetway/nf81-t56n-lf/acpi_tables.c @@ -232,9 +232,13 @@ unsigned long write_acpi_tables(unsigned long start) } /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); - alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); +// current = ALIGN(current, 16); +// printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); +// alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); + /* ALIB SSDT is a MS compiled blob inside AGESA that is broken with syntax + * errors! We disable it for now. */ + printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT broken so disabled!\n"); + alib = NULL; if (alib != NULL) { memcpy((void *)current, alib, alib->length); alib = (acpi_header_t *) current;

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coreboot-gerrit May 2014