coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

New patch to review for coreboot: 01de8eb SeaBIOS: Fix cpp use
by Patrick Georgi 10 May '14

10 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5715 -gerrit commit 01de8eb102fef5c23549785e45b3ac4d11d99f45 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 10 14:21:38 2014 +0200 SeaBIOS: Fix cpp use No need to pass CPP down to SeaBIOS, it's not architecture specific and they define their own variable. Change-Id: I811aaf3929fa11cc01b7f168ccd310008e21e60c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/arch/x86/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 8e02f45..b02df5a 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -346,7 +346,7 @@ seabios: HOSTCC="$(HOSTCC)" \ CC="$(CC_x86_32)" LD="$(LD_x86_32)" OBJDUMP="$(OBJDUMP_x86_32)" \ OBJCOPY="$(OBJCOPY_x86_32)" STRIP="$(STRIP_x86_32)" \ - AS="$(AS_x86_32)" CPP="$(CPP)" \ + AS="$(AS_x86_32)" \ CONFIG_SEABIOS_MASTER=$(CONFIG_SEABIOS_MASTER) \ CONFIG_SEABIOS_STABLE=$(CONFIG_SEABIOS_STABLE) \ CONFIG_SEABIOS_THREAD_OPTIONROMS=$(CONFIG_SEABIOS_THREAD_OPTIONROMS) \

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New patch to review for coreboot: f743048 payloads/external/SeaBIOS: Adapt for new opt in master
by Edward O'Callaghan 10 May '14

10 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5714 -gerrit commit f74304842f70a844d1eccc9c0e6f3874ed446ce2 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 10 21:27:50 2014 +1000 payloads/external/SeaBIOS: Adapt for new opt in master SeaBIOS has some new support options, select the default values. Change-Id: I65dd79b4683b7d8bdfbf1d4a05bf28976658ce76 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/external/SeaBIOS/Makefile.inc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 042df0a..e05c888 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -36,6 +36,10 @@ endif echo "CONFIG_FLASH_FLOPPY=y" >> $(OUT)/seabios/.config echo "CONFIG_VGAHOOKS=y" >> $(OUT)/seabios/.config echo "CONFIG_DEBUG_COREBOOT=y" >> $(OUT)/seabios/.config + echo "CONFIG_CBFS_LOCATION=0x0" >> $(OUT)/seabios/.config + echo "CONFIG_VGA_COREBOOT=y" >> $(OUT)/seabios/.config + echo "CONFIG_VGA_ALLOCATE_EXTRA_STACK=y" >> $(OUT)/seabios/.config + echo "CONFIG_VGA_VBE=y" >> $(OUT)/seabios/.config # This shows how to force a previously set .config option *off* #echo "# CONFIG_SMBIOS is not set" >> $(OUT)/seabios/.config

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Patch merged into coreboot/master: 5c3f384 Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit 5c3f384f064f5c05945d561784fd7e8ef002a295 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu May 8 15:27:15 2014 +0300 Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT Lines with 'select SERIAL_CPU_INIT' where redundant with the default being yes. Since there is no 'unselect SERIAL_CPU_INIT' possibility, invert the default and rename option. This squelches Kconfig warnings about unmet dependencies. Change-Id: Iae546c56006278489ebae10f2daa627af48abe94 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5700 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/5700 for details. -gerrit

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Patch set updated for coreboot: 691d663 superio/ite/it8728f: RAMstage PNP configuration component
by Edward O'Callaghan 10 May '14

10 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5668 -gerrit commit 691d66356b2318b5c78fb5e962c1ff82ea7eea36 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 18:00:07 2014 +1000 superio/ite/it8728f: RAMstage PNP configuration component Provide devicetree.cb RAMstage configuration of this superio component. Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8728f/Makefile.inc | 2 + src/superio/ite/it8728f/chip.h | 34 +++++++++++++ src/superio/ite/it8728f/it8728f_hwm.c | 80 ++++++++++++++++++++++++++++++ src/superio/ite/it8728f/it8728f_internal.h | 28 +++++++++++ src/superio/ite/it8728f/superio.c | 69 ++++++++++++++++++++++++++ 5 files changed, 213 insertions(+) diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc index d8d4f6a..a146db8 100644 --- a/src/superio/ite/it8728f/Makefile.inc +++ b/src/superio/ite/it8728f/Makefile.inc @@ -19,3 +19,5 @@ ## romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += it8728f_hwm.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c diff --git a/src/superio/ite/it8728f/chip.h b/src/superio/ite/it8728f/chip.h new file mode 100644 index 0000000..678c19b --- /dev/null +++ b/src/superio/ite/it8728f/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_CHIP_H +#define SUPERIO_ITE_IT8728F_CHIP_H + +struct superio_ite_it8728f_config { + /* HWM configuration registers */ + uint8_t hwm_ctl_register; + uint8_t hwm_main_ctl_register; + uint8_t hwm_adc_temp_chan_en_reg; + uint8_t hwm_fan1_ctl_pwm; + uint8_t hwm_fan2_ctl_pwm; + uint8_t hwm_fan3_ctl_pwm; +}; + +#endif /* SUPERIO_ITE_IT8728F_CHIP_H */ diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c new file mode 100644 index 0000000..389cfd5 --- /dev/null +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "ite_internal.h" + +/* + * FAN controller configuration register index's + */ +#define HWM_MAIN_CTL_REG 0x13 /* default 0x07 */ +#define HWM_CTL_REG 0x14 /* default 0x40 */ +#define HWM_FAN1_CTL_PWM 0x15 /* default 0x00 */ +#define HWM_FAN2_CTL_PWM 0x16 /* default 0x00 */ +#define HWM_FAN3_CTL_PWM 0x17 /* default 0x00 */ +#define HWM_ADC_TEMP_CHAN_EN_REG 0x51 /* default 0x00 */ + +static void pnp_write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +void it8728f_hwm_ec_init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + u16 port = res->base; + + printk(BIOS_INFO, + "ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n"); + printk(BIOS_DEBUG, + "ITE IT8728F Super I/O HWM: Base Address at 0x%x\n", port); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + /* ITE IT8728F HWM (ordered) programming sequence. */ + + /* configure fan polarity */ + pnp_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register); + + /* enable fans 1-3 */ + pnp_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register); + + /* enable termistor temps for temp1-temp3 */ + pnp_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg); + + /* configure which fanX uses which tempY */ + pnp_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm); + pnp_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm); + pnp_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/ite/it8728f/it8728f_internal.h b/src/superio/ite/it8728f/it8728f_internal.h new file mode 100644 index 0000000..89aecb4 --- /dev/null +++ b/src/superio/ite/it8728f/it8728f_internal.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_INTERNAL_H +#define SUPERIO_ITE_IT8728F_INTERNAL_H + +#include <device/device.h> + +void it8728f_hwm_ec_init(device_t dev); + +#endif /* SUPERIO_ITE_IT8728F_INTERNAL_H */ diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c new file mode 100644 index 0000000..ac08f72 --- /dev/null +++ b/src/superio/ite/it8728f/superio.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> + +#include "chip.h" +#include "it8728f.h" +#include "it8728f_internal.h" + +static void it8728f_init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case IT8728F_EC: + it8728f_hwm_ec_init(dev); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8728f_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +/* TODO: incomplete */ +static struct pnp_info pnp_dev_info[] = { + { &ops, IT8728F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8728f_ops = { + CHIP_NAME("ITE IT8728F Super I/O") + .enable_dev = enable_dev +};

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Patch merged into coreboot/master: a7e2cc5 mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cb
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit a7e2cc507b520583fe2e727371e431d65924ee53 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 8 20:45:09 2014 +1000 mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cb Turn on WDT support in the devicetree. Turn off CIR support. Dispense with old commentary. Change-Id: Icf0c0e12a0ed7ce6c3b6176653e076ffc2ba937e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5698 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5698 for details. -gerrit

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Patch merged into coreboot/master: c848098 superio/fintek/f71869ad: Fix incorrect LDN's
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit c848098b2fc1a93b777fa811c988ce2f9b732816 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 8 19:50:55 2014 +1000 superio/fintek/f71869ad: Fix incorrect LDN's Turns out there are a few minor differences of the LDN's in the AD rev. of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the now incorrect io mask. Add missing CIR LDN functionality and touch up src inline doc. Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5696 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5696 for details. -gerrit

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Patch merged into coreboot/master: 63fcb4a baytrail: cache reference code for S3 resume
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit 63fcb4a1f89f1b74f834249b1bc683da280221fa Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:29:48 2013 -0800 baytrail: cache reference code for S3 resume In order to use the same reference code on S3 resume that was booted the program needs to be cached. Piggy back on the ramstage cache to save the loaded reference code program. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Noted locations of reference code caching and load addresses in console. Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179777 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5013 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5013 for details. -gerrit

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Patch merged into coreboot/master: ce727e1 baytrail: allow ramstage_cache_location() usage in ramstage
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit ce727e18f0992126b7a27b8a51b426834e804390 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:27:11 2013 -0800 baytrail: allow ramstage_cache_location() usage in ramstage To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5012 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5012 for details. -gerrit

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Patch merged into coreboot/master: be25129 ramstage_cache: allow ramstage usage add valid helper
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit be2512973d04f3da3cebfd3e7ee10809fbe4ae4a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:10:52 2013 -0800 ramstage_cache: allow ramstage usage add valid helper Allow ramstage cache to be used from ramstage proper. Also add a helper function for checking validity of ramstage cache structure. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179775 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5011 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5011 for details. -gerrit

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Patch merged into coreboot/master: 7d34c60 baytrail: note S3 resume status earlier
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit 7d34c6070b8fc2e8dc2f5274794e2374a883d4ce Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:07:00 2013 -0800 baytrail: note S3 resume status earlier Certain code paths want to know if S3 resume is happening. However, the current baytrail code doesn't note S3 resume early enough. Therefore, mark S3 resume just after pattr setup. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179774 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5010 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5010 for details. -gerrit

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coreboot-gerrit May 2014