coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

New patch to review for coreboot: 3ff1582 payloads: make build system integration work again
by Patrick Georgi 09 May '14

09 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5710 -gerrit commit 3ff15825462ebe08c38ddfd11b272d90c426024e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri May 9 20:41:01 2014 +0200 payloads: make build system integration work again Payloads using Kconfig get confused by coreboot Kconfig configuration in environment variables. Prune them. Change-Id: I63da2af0a15dca35d70cd65b2f74a1564aab9483 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- payloads/external/FILO/Makefile.inc | 5 +++++ payloads/external/SeaBIOS/Makefile.inc | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/payloads/external/FILO/Makefile.inc b/payloads/external/FILO/Makefile.inc index 72f86bc..d298d1d 100644 --- a/payloads/external/FILO/Makefile.inc +++ b/payloads/external/FILO/Makefile.inc @@ -3,7 +3,12 @@ NAME-$(CONFIG_FILO_MASTER)=MASTER TAG-$(CONFIG_FILO_STABLE)=4dbb31a64fe5b1c7e3025ab34619220609897646 NAME-$(CONFIG_FILO_STABLE)=STABLE +unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES all: filo diff --git a/payloads/external/SeaBIOS/Makefile.inc b/payloads/external/SeaBIOS/Makefile.inc index 153cf97..042df0a 100644 --- a/payloads/external/SeaBIOS/Makefile.inc +++ b/payloads/external/SeaBIOS/Makefile.inc @@ -1,7 +1,12 @@ TAG-$(CONFIG_SEABIOS_MASTER)=origin/master TAG-$(CONFIG_SEABIOS_STABLE)=88cb66ea542906ffff8a80ef397b9e3adbb33116 +unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES all: build

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New patch to review for coreboot: 578c7b9 Makefile.inc: Make clang once again a valid toolchain
by Edward O'Callaghan 09 May '14

09 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5709 -gerrit commit 578c7b977764f3e10e65ef2774e48a5415e46517 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat May 10 04:39:06 2014 +1000 Makefile.inc: Make clang once again a valid toolchain 'prove' that clang is supported (to some extent). Change-Id: I181f4910ba64ab9746e7ac94aa79da23cdd41dad Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index bd1a58a..3205a10 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -29,6 +29,9 @@ ifneq ($(NOCOMPILE),1) # only run if we're doing a build (not for tests, kconfig, ...) ifneq ($(CONFIG_ANY_TOOLCHAIN),y) _toolchain=$(shell $(CC_x86_32) -v 2>&1 |grep -q "gcc version .*coreboot toolchain" && echo coreboot) +ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) +_toolchain=coreboot +endif ifneq ($(_toolchain),coreboot) $(error Please use the coreboot toolchain (or prove that your toolchain works)) endif

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Patch set updated for coreboot: 5720ffe baytrail: initialize perf/power registers
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5008 -gerrit commit 5720ffe311c3d26bf7910a223b435a66e0a87c3b Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 11 17:15:45 2013 -0800 baytrail: initialize perf/power registers According to the reference code all these registers need to be set to their best known values. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. Suspend and wake. No idea about observable impact yet. Change-Id: I0e31505a165eee1d177e5d726edcfa6947430476 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179749 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/perf_power.c | 295 ++++++++++++++++++++++++++++++++++++ 2 files changed, 296 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 48fb4b4..e2a949f 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += emmc.c ramstage-y += lpss.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += perf_power.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c new file mode 100644 index 0000000..a577c6b --- /dev/null +++ b/src/soc/intel/baytrail/perf_power.c @@ -0,0 +1,295 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <bootstate.h> +#include <console/console.h> +#include <reg_script.h> +#include <baytrail/iosf.h> + +#define MAKE_MASK_INCLUSIVE(msb) \ + ((1ULL << (1 + (msb))) - 1) +#define MAKE_MASK(msb) \ + ((1ULL << (msb)) - 1) +#define MASK_VAL(msb, lsb, val) \ + ~(MAKE_MASK_INCLUSIVE(msb) & ~MAKE_MASK(lsb)), (val) << (lsb) + +#define E(arg1, arg2, args) \ + REG_IOSF_RMW(IOSF_PORT_##arg1, arg2, args) + +static const struct reg_script perf_power_settings[] = { +E(AUNIT, 0x18, MASK_VAL(22, 22, 0x1)), // ACKGATE.AMESSAGE_MSGIF +E(AUNIT, 0x18, MASK_VAL(21, 21, 0x1)), // ACKGATE.AREQDOWN_SCL0_ARB +E(AUNIT, 0x18, MASK_VAL(20, 20, 0x1)), // ACKGATE.AREQUP_MIRROR +E(AUNIT, 0x18, MASK_VAL(19, 19, 0x1)), // ACKGATE.AREQTAHACK +E(AUNIT, 0x18, MASK_VAL(18, 18, 0x1)), // ACKGATE.AREQDOWN_TAREQQ +E(AUNIT, 0x18, MASK_VAL(17, 17, 0x1)), // ACKGATE.AREQDOWN_CREDIT +E(AUNIT, 0x18, MASK_VAL(16, 16, 0x1)), // ACKGATE.ASCLUP_FAIR_ARBITER +E(AUNIT, 0x18, MASK_VAL(15, 15, 0x1)), // ACKGATE.AIOSFDOWN_DATA +E(AUNIT, 0x18, MASK_VAL(14, 14, 0x1)), // ACKGATE.ASCLUP_IOSF_ADAPTER +E(AUNIT, 0x18, MASK_VAL(12, 12, 0x1)), // ACKGATE.ASCLUP_CMD_QUEUE +E(AUNIT, 0x18, MASK_VAL(11, 11, 0x1)), // ACKGATE.ASCLUP_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(10, 10, 0x1)), // ACKGATE.AREQUP_CMD_QUEUE +E(AUNIT, 0x18, MASK_VAL(9, 9, 0x1)), // ACKGATE.AREQUP_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(8, 8, 0x1)), // ACKGATE.AREQDOWN_RSP_QUEUE +E(AUNIT, 0x18, MASK_VAL(7, 7, 0x1)), // ACKGATE.AREQDOWN_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(6, 6, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DRVR +E(AUNIT, 0x18, MASK_VAL(5, 5, 0x1)), // ACKGATE.AIOSFDOWN_CMD_DATA_BUFF +E(AUNIT, 0x18, MASK_VAL(4, 4, 0x1)), // ACKGATE.AT_REQ_QUEUE +E(AUNIT, 0x18, MASK_VAL(3, 3, 0x1)), // ACKGATE.AT_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(2, 2, 0x1)), // ACKGATE.TA_REQ_QUEUE +E(AUNIT, 0x18, MASK_VAL(1, 1, 0x1)), // ACKGATE.TA_DATA_QUEUE +E(AUNIT, 0x18, MASK_VAL(0, 0, 0x1)), // ACKGATE.CONFIG_REGS +E(AUNIT, 0x20, MASK_VAL(26, 24, 0x2)), // AISOCHCTL.CHANNEL_AB_DEADLINE_EN +E(AUNIT, 0x20, MASK_VAL(8, 0, 0x1)), // AISOCHCTL.VC1_ISOC_CH_DEFAULT_DDLINE_DLY +E(AUNIT, 0x21, MASK_VAL(31, 31, 0x1)), // AVCCTL.EFFICIENT_PERF_UP_EN +E(AUNIT, 0x21, MASK_VAL(8, 8, 0x0)), // AVCCTL.VC_EN_PRIORITY_DNARB +E(AUNIT, 0x0C0, MASK_VAL(11, 8, 0x4)), // AARBCTL0.IOSF0VC2_WGT +E(AUNIT, 0x0C0, MASK_VAL(7, 4, 0x4)), // AARBCTL0.IOSF0VC1_WGT +E(AUNIT, 0x0C0, MASK_VAL(3, 0, 0x4)), // AARBCTL0.IOSF0VC0_WGT +E(BUNIT, 0x3, MASK_VAL(29, 24, 0x4)), // BARBCTRL0.AGENT3_WEIGHT +E(BUNIT, 0x3, MASK_VAL(21, 16, 0x4)), // BARBCTRL0.AGENT2_WEIGHT +E(BUNIT, 0x3, MASK_VAL(13, 8, 0x4)), // BARBCTRL0.AGENT1_WEIGHT +E(BUNIT, 0x3, MASK_VAL(5, 0, 0x4)), // BARBCTRL0.AGENT0_WEIGHT +E(BUNIT, 0x4, MASK_VAL(29, 24, 0x4)), // BARBCTRL1.AGENT7_WEIGHT +E(BUNIT, 0x4, MASK_VAL(21, 16, 0x4)), // BARBCTRL1.AGENT6_WEIGHT +E(BUNIT, 0x4, MASK_VAL(13, 8, 0x4)), // BARBCTRL1.AGENT5_WEIGHT +E(BUNIT, 0x4, MASK_VAL(5, 0, 0x4)), // BARBCTRL1.AGENT4_WEIGHT +E(BUNIT, 0x5, MASK_VAL(21, 16, 0x4)), // BARBCTRL2.AGENT10_WEIGHT +E(BUNIT, 0x5, MASK_VAL(13, 8, 0x4)), // BARBCTRL2.AGENT9_WEIGHT +E(BUNIT, 0x5, MASK_VAL(5, 0, 0x8)), // BARBCTRL2.AGENT8_WEIGHT +E(BUNIT, 0x7, MASK_VAL(31, 24, 0x20)), // BWFLUSH.FLUSH_THRSHOLD +E(BUNIT, 0x7, MASK_VAL(15, 8, 0x0A)), // BWFLUSH.DIRTY_LWM +E(BUNIT, 0x7, MASK_VAL(7, 0, 0x10)), // BWFLUSH.DIRTY_HWM +E(BUNIT, 0x8, MASK_VAL(23, 0, 0x0)), // BBANKMASK.BANK_MASK +E(BUNIT, 0x9, MASK_VAL(23, 0, 0x3FFFFC)), // BROWMASK.ROW_MASK +E(BUNIT, 0x0A, MASK_VAL(9, 0, 0x080)), // BRANKMASK.RANK_MASK +E(BUNIT, 0x0B, MASK_VAL(29, 24, 0x1F)), // BALIMIT0.AGENT3_LIMIT +E(BUNIT, 0x0B, MASK_VAL(21, 16, 0x2F)), // BALIMIT0.AGENT2_LIMIT +E(BUNIT, 0x0B, MASK_VAL(13, 8, 0x2F)), // BALIMIT0.AGENT1_LIMIT +E(BUNIT, 0x0B, MASK_VAL(5, 0, 0x2F)), // BALIMIT0.AGENT0_LIMIT +E(BUNIT, 0x0C, MASK_VAL(29, 24, 0x2F)), // BALIMIT1.AGENT7_LIMIT +E(BUNIT, 0x0C, MASK_VAL(21, 16, 0x2F)), // BALIMIT1.AGENT6_LIMIT +E(BUNIT, 0x0C, MASK_VAL(13, 8, 0x2F)), // BALIMIT1.AGENT5_LIMIT +E(BUNIT, 0x0C, MASK_VAL(5, 0, 0x2B)), // BALIMIT1.AGENT4_LIMIT +E(BUNIT, 0x0D, MASK_VAL(21, 16, 0x2F)), // BALIMIT2.AGENT10_LIMIT +E(BUNIT, 0x0D, MASK_VAL(13, 8, 0x2F)), // BALIMIT2.AGENT9_LIMIT +E(BUNIT, 0x0D, MASK_VAL(5, 0, 0x2F)), // BALIMIT2.AGENT8_LIMIT +E(BUNIT, 0x0F, MASK_VAL(29, 28, 0x0)), // BARES0.AGENT7_RSVD +E(BUNIT, 0x0F, MASK_VAL(25, 24, 0x0)), // BARES0.AGENT6_RSVD +E(BUNIT, 0x0F, MASK_VAL(21, 20, 0x0)), // BARES0.AGENT5_RSVD +E(BUNIT, 0x0F, MASK_VAL(17, 16, 0x0)), // BARES0.AGENT4_RSVD +E(BUNIT, 0x0F, MASK_VAL(13, 12, 0x0)), // BARES0.AGENT3_RSVD +E(BUNIT, 0x0F, MASK_VAL(9, 8, 0x0)), // BARES0.AGENT2_RSVD +E(BUNIT, 0x0F, MASK_VAL(5, 4, 0x0)), // BARES0.AGENT1_RSVD +E(BUNIT, 0x0F, MASK_VAL(1, 0, 0x0)), // BARES0.AGENT0_RSVD +E(BUNIT, 0x10, MASK_VAL(9, 8, 0x0)), // BARES1.AGENT10_RSVD +E(BUNIT, 0x10, MASK_VAL(5, 4, 0x0)), // BARES1.AGENT9_RSVD +E(BUNIT, 0x10, MASK_VAL(1, 0, 0x0)), // BARES1.AGENT8_RSVD +E(BUNIT, 0x11, MASK_VAL(31, 22, 0x20)), // BISOC.ENTER_SELF_REFRESH_THRSH +E(BUNIT, 0x11, MASK_VAL(18, 18, 0x1)), // BISOC.SR_EXIT_SYNC_EN +E(BUNIT, 0x11, MASK_VAL(17, 12, 0x4)), // BISOC.ENTER_SELF_REFRESH_DLY +E(BUNIT, 0x11, MASK_VAL(11, 8, 0x8)), // BISOC.SCHEDULER_LATENCY +E(BUNIT, 0x11, MASK_VAL(6, 0, 0xC)), // BISOC.EXIT_SELF_REFRESH_LATENCY +E(BUNIT, 0x12, MASK_VAL(31, 30, 0x0)), // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE +E(BUNIT, 0x12, MASK_VAL(29, 28, 0x0)), // BCOSCAT.COS_CAT_AGENT14 +E(BUNIT, 0x12, MASK_VAL(27, 26, 0x0)), // BCOSCAT.COS_CAT_AGENT13 +E(BUNIT, 0x12, MASK_VAL(25, 24, 0x0)), // BCOSCAT.COS_CAT_AGENT12 +E(BUNIT, 0x12, MASK_VAL(23, 22, 0x0)), // BCOSCAT.COS_CAT_AGENT11 +E(BUNIT, 0x12, MASK_VAL(21, 20, 0x0)), // BCOSCAT.COS_CAT_AGENT10 +E(BUNIT, 0x12, MASK_VAL(19, 18, 0x0)), // BCOSCAT.COS_CAT_AGENT9 +E(BUNIT, 0x12, MASK_VAL(17, 16, 0x1)), // BCOSCAT.COS_CAT_AGENT8 +E(BUNIT, 0x12, MASK_VAL(15, 14, 0x0)), // BCOSCAT.COS_CAT_AGENT7 +E(BUNIT, 0x12, MASK_VAL(13, 12, 0x0)), // BCOSCAT.COS_CAT_AGENT6 +E(BUNIT, 0x12, MASK_VAL(11, 10, 0x1)), // BCOSCAT.COS_CAT_AGENT5 +E(BUNIT, 0x12, MASK_VAL(9, 8, 0x1)), // BCOSCAT.COS_CAT_AGENT4 +E(BUNIT, 0x12, MASK_VAL(7, 6, 0x0)), // BCOSCAT.COS_CAT_AGENT3 +E(BUNIT, 0x12, MASK_VAL(5, 4, 0x0)), // BCOSCAT.COS_CAT_AGENT2 +E(BUNIT, 0x12, MASK_VAL(3, 2, 0x0)), // BCOSCAT.COS_CAT_AGENT1 +E(BUNIT, 0x12, MASK_VAL(1, 0, 0x0)), // BCOSCAT.COS_CAT_AGENT0 +E(BUNIT, 0x14, MASK_VAL(31, 31, 0x0)), // BFLWT.DISABLE_FLUSH_WEIGHTS +E(BUNIT, 0x14, MASK_VAL(30, 30, 0x0)), // BFLWT.ENABLE_READ_INVALIDATE_TIMER +E(BUNIT, 0x14, MASK_VAL(13, 8, 0x8)), // BFLWT.WRITE_WEIGHTS +E(BUNIT, 0x14, MASK_VAL(5, 0, 0x10)), // BFLWT.READ_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(31, 31, 0x0)), // BISOCWT.ENABLE_ISOC_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(13, 8, 0x3F)), // BISOCWT.ISOC_REQUEST_WEIGHTS +E(BUNIT, 0x16, MASK_VAL(5, 0, 0x8)), // BISOCWT.NON_ISOC_REQUEST_WEIGHTS +E(BUNIT, 0x18, MASK_VAL(31, 24, 0x20)), // BSCHCTRL0.BEST_EFFORT_MAX_LATENCY +E(BUNIT, 0x18, MASK_VAL(23, 21, 0x6)), // BSCHCTRL0.PAGE_HIT_DELAY +E(BUNIT, 0x18, MASK_VAL(13, 7, 0x0)), // BSCHCTRL0.ISOC_BANK_PREFETCH +E(BUNIT, 0x18, MASK_VAL(6, 0, 0x20)), // BSCHCTRL0.BEST_EFFORT_BANK_PREFETCH +E(BUNIT, 0x3B, MASK_VAL(23, 16, 0x4)), // BDEBUG0.CASUAL_TIMER +E(BUNIT, 0x3B, MASK_VAL(9, 9, 0x0)), // BDEBUG0.DISABLE_BADMIT_URGENT_ISOC +E(BUNIT, 0x3B, MASK_VAL(7, 0, 0x0A)), // BDEBUG0.CASUAL_WATER_MARK +E(BUNIT, 0x3C, MASK_VAL(31, 16, 0x0FFFF)), // BDEBUG1.AGENT_WEIGHT_ENABLE +E(BUNIT, 0x3C, MASK_VAL(2, 2, 0x0)), // BDEBUG1.EXIT_SR_FOR_CASUAL_FLUSH +E(BUNIT, 0x3C, MASK_VAL(1, 1, 0x0)), // BDEBUG1.ENABLE_DRAM_SELF_RFRSH +E(BUNIT, 0x3D, MASK_VAL(14, 14, 0x1)), // BCTRL.BANK_STATUS_ENABLE +E(BUNIT, 0x3D, MASK_VAL(13, 13, 0x0)), // BCTRL.DISABLE_OWNED +E(BUNIT, 0x3D, MASK_VAL(12, 12, 0x0)), // BCTRL.INORDER_READ_ENABLE +E(BUNIT, 0x3D, MASK_VAL(11, 11, 0x0)), // BCTRL.INORDER_FLUSH_ENABLE +E(BUNIT, 0x3D, MASK_VAL(8, 8, 0x0)), // BCTRL.MISS_VALID_ENTRIES +E(BUNIT, 0x3D, MASK_VAL(7, 7, 0x0)), // BCTRL.DIRTY_STALL +E(BUNIT, 0x3D, MASK_VAL(6, 6, 0x0)), // BCTRL.SINGLE_TAG_ACCESS +E(BUNIT, 0x3D, MASK_VAL(5, 5, 0x0)), // BCTRL.SINGLE_CHUNK_ACCESS +E(BUNIT, 0x3D, MASK_VAL(2, 2, 0x1)), // BCTRL.BECLK_GATE_EN +E(BUNIT, 0x3D, MASK_VAL(1, 1, 0x1)), // BCTRL.MASTERCLK_GATE_EN +E(BUNIT, 0x3D, MASK_VAL(0, 0, 0x1)), // BCTRL.REQUESTCLK_GATE_EN +E(BUNIT, 0x3E, MASK_VAL(31, 16, 0x0)), // BTHCTRL.AGENT_THROTTLING_ENABLE +E(BUNIT, 0x3E, MASK_VAL(7, 0, 0x0)), // BTHCTRL.RANK_SELECTION_MASK +E(BUNIT, 0x3F, MASK_VAL(31, 24, 0x0FF)), // BTHMASK.ORWRITE_MASK +E(BUNIT, 0x3F, MASK_VAL(23, 16, 0x0FF)), // BTHMASK.ORREAD_MASK +E(BUNIT, 0x3F, MASK_VAL(15, 8, 0x0FF)), // BTHMASK.ERWRITE_MASK +E(BUNIT, 0x3F, MASK_VAL(7, 0, 0x0FF)), // BTHMASK.ERREAD_MASK + //0x02, 0x0, 2, 0, 0x1, //T_INTR_REDIR_CTL.REDIR_MODE_SEL +E(CPU_BUS, 0x3, MASK_VAL(20, 20, 0x1)), // T_CTL.SPLIT_GOIWP_MODE +E(CPU_BUS, 0x3, MASK_VAL(19, 19, 0x0)), // T_CTL.DISABLE_TRDY_RDGO +E(CPU_BUS, 0x3, MASK_VAL(18, 18, 0x0)), // T_CTL.DISABLE_ISOC_HIGHPRI_RDDATA_RETURN +E(CPU_BUS, 0x3, MASK_VAL(17, 17, 0x0)), // T_CTL.ENABLE_NPC_COLLECTOR +E(CPU_BUS, 0x3, MASK_VAL(16, 16, 0x1)), // T_CTL.ENABLE_IN_ORDER_APIC +E(CPU_BUS, 0x3, MASK_VAL(15, 15, 0x0)), // T_CTL.TG_HIGHPRI_WRITE_PULLS + //0x02, 0x3, 12, 12, 0x1, // T_CTL.TG_NDRAMSNP +E(CPU_BUS, 0x3, MASK_VAL(10, 10, 0x1)), // T_CTL.TG_DW_POST_PUSH_LOG +E(CPU_BUS, 0x3, MASK_VAL(3, 3, 0x0)), // T_CTL.ALWAYS_SNP_IDI +E(CPU_BUS, 0x3, MASK_VAL(2, 2, 0x0)), // T_CTL.DIS_LIVE_BRAM_BYP_IDI +E(CPU_BUS, 0x4, MASK_VAL(18, 18, 0x1)), // T_MISC_CTL.DISABLE_IOSF_OUTBOUND_THROTTLE +E(CPU_BUS, 0x4, MASK_VAL(4, 1, 0x8)), // T_MISC_CTL.DPTE_CNT +E(CPU_BUS, 0x4, MASK_VAL(0, 0, 0x0)), // T_MISC_CTL.DPTE_EN +E(CPU_BUS, 0x5, MASK_VAL(27, 27, 0x1)), // T_CLKGATE_CTL.XUNIT_4_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(26, 26, 0x1)), // T_CLKGATE_CTL.XUNIT_3_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(25, 25, 0x1)), // T_CLKGATE_CTL.XUNIT_2_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(24, 24, 0x1)), // T_CLKGATE_CTL.XUNIT_1_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(23, 23, 0x1)), // T_CLKGATE_CTL.MON_LOG_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(22, 22, 0x1)), // T_CLKGATE_CTL.A2T_Q_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(21, 21, 0x1)), // T_CLKGATE_CTL.T2A_Q_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(20, 20, 0x1)), // T_CLKGATE_CTL.A2TAPIC_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(19, 19, 0x1)), // T_CLKGATE_CTL.B2X_DATSEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(18, 18, 0x1)), // T_CLKGATE_CTL.X2B_DATSEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(17, 17, 0x1)), // T_CLKGATE_CTL.S2C_RESP_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(16, 16, 0x1)), // T_CLKGATE_CTL.T2A_REQ_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(15, 15, 0x1)), // T_CLKGATE_CTL.C2APIC_FIFO_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(14, 14, 0x1)), // T_CLKGATE_CTL.S2C_REQ_FIFO_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(13, 13, 0x1)), // T_CLKGATE_CTL.S2C_REQ_SEL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(12, 12, 0x1)), // T_CLKGATE_CTL.TRKR_SB_LLST_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(11, 11, 0x1)), // T_CLKGATE_CTL.TRKR_SB_OLDST_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(10, 10, 0x1)), // T_CLKGATE_CTL.TRKR_SB_S2C_RESP_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(9, 9, 0x1)), // T_CLKGATE_CTL.TRKR_SB_T2A_REQSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(8, 8, 0x1)), // T_CLKGATE_CTL.TRKR_SB_B2X_DATSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(7, 7, 0x1)), // T_CLKGATE_CTL.TRKR_SB_WRSTAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(6, 6, 0x1)), // T_CLKGATE_CTL.TRKR_SB_SNP_STAT_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(5, 5, 0x1)), // T_CLKGATE_CTL.TRKR_SB_REQ_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(4, 4, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VIOL_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(3, 3, 0x1)), // T_CLKGATE_CTL.TRKR_SB_VALID_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(2, 2, 0x1)), // T_CLKGATE_CTL.TRKR_SB_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(1, 1, 0x1)), // T_CLKGATE_CTL.IOSF_SB_CFG_REG_CLK_GATE_EN +E(CPU_BUS, 0x5, MASK_VAL(0, 0, 0x1)), // T_CLKGATE_CTL.IOSF_SB_MSG_CLK_GATE_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x58, 0x40, MASK_VAL(4, 4, 0x0)), // SSCR2.ACG_EN +E(0x55, 0x54, MASK_VAL(1, 0, 0x0)), // SMB_Config_PMCSR.PS +E(0x55, 0x0FC, MASK_VAL(17, 17, 0x0)), // SMB_Config_CGC.FUNC_CLK_CGD +E(0x55, 0x0FC, MASK_VAL(9, 9, 0x0)), // SMB_Config_CGC.SB_LOCAL_CGD +E(0xa2, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x47, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x45, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(0x46, 0x0C000, MASK_VAL(0, 0, 0x0)), // power_options.clkgate_disable +E(PMC, 0x0, MASK_VAL(11, 11, 0x1)), // PUNIT_CONTROL.MODE_DEMOTE_EN +E(PMC, 0x0, MASK_VAL(10, 10, 0x1)), // PUNIT_CONTROL.CORE_DEMOTE_EN + + // + //s0ix_PnP_Settings + // +E(0x58, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfprim_trunk_gate_en +E(0x58, 0x1e0, MASK_VAL(0, 0, 0x0)), //vlv.audio.lpe.bridge.pmctl.iosfprimclk_gate_en +E(0x58, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.audio.lpe.bridge.pmctl.iosfsb_trunk_gate_en +E(0x58, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.audio.lpe.bridge.pmctl.pmctl.iosfsbclk_gate_en +E(0x58, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_gate_en +E(0x58, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.audio.lpe.bridge.pmctl.ocpclk_trunk_gate_en +E(CCU, 0x28, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate +E(CCU, 0x38, MASK_VAL(31, 0, 0x0)), //vlv.ccu.ccu_trunk_clkgate_2 +E(CCU, 0x1c, MASK_VAL(29, 28, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_pri_clkgate_en +E(CCU, 0x1c, MASK_VAL(25, 24, 0x0)), //vlv.ccu.clkgate_en_1.cr_lpe_sb_clkgate_en +E(CCU, 0x1c, MASK_VAL( 1, 0, 0x0)), //vlv.ccu.clkgate_en_1.lps_free_clkgate_en +E(CCU, 0x54, MASK_VAL(17, 16, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_func_ip_clkgate_en +E(CCU, 0x54, MASK_VAL(13, 12, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_osc_ip_clk_en +E(CCU, 0x54, MASK_VAL(15, 14, 0x0)), //vlv.ccu.clkgate_en_3.cr_lpe_xtal_ip_clkgate_en +E(CCU, 0x54, MASK_VAL(26, 24, 0x0)), //vlv.ccu.clkgate_en_3.psf_pri_clkgate_en +E(CCU, 0x24, MASK_VAL(24, 20, 0x0)), //vlv.ccu.iclk_clkgate_ctrl.iopcibuffen_force_on +E(0x59, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprim_trunk_gate_en +E(0x59, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfprimclk_gate_en +E(0x59, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsb_trunk_gate_en +E(0x59, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.iosfsbclk_gate_en +E(0x59, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_gate_en +E(0x59, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.usb.xdci_otg.controller.pmctl.ocpclk_trunk_gate_en +E(0x5a, 0xd0, MASK_VAL(8, 0, 0x3f)), //vlv.usb.xhci.controller.usb2pr.usb2hcsel +E(0x5a, 0x40, MASK_VAL(21, 19, 0x6)), //vlv.usb.xhci.controller.xhcc1.iil1e +E(0x5a, 0x40, MASK_VAL(10, 8, 0x1)), //vlv.usb.xhci.controller.xhcc1.l23hrawc +E(0x5a, 0x40, MASK_VAL(18, 18, 0x1)), //vlv.usb.xhci.controller.xhcc1.xhcil1e +E(0x5a, 0x50, MASK_VAL(3, 3, 0x1)), //vlv.usb.xhci.controller.xhclkgten.hsltcge +E(0x5a, 0x50, MASK_VAL(0, 0, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfblcge +E(0x5a, 0x50, MASK_VAL(1, 1, 0x1)), //vlv.usb.xhci.controller.xhclkgten.iosfbtcge +E(0x5a, 0x50, MASK_VAL(2, 2, 0x1)), //vlv.usb.xhci.controller.xhclkgten.ssltcge +E(0x5a, 0x50, MASK_VAL(7, 5, 0x2)), //vlv.usb.xhci.controller.xhclkgten.sspllsue +E(0x5a, 0x50, MASK_VAL(13, 13, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcbbtcgipiso +E(0x5a, 0x50, MASK_VAL(4, 4, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcblcge +E(0x5a, 0x50, MASK_VAL(14, 14, 0x1)), //vlv.usb.xhci.controller.xhclkgten.xhcftclkse +E(0x5a, 0x50, MASK_VAL(12, 12, 0x0)), //vlv.usb.xhci.controller.xhclkgten.xhchstcgu2nrwe +E(0x5a, 0x50, MASK_VAL(11, 10, 0x3)), //vlv.usb.xhci.controller.xhclkgten.xhcusb2pllsdle +E(SCORE, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpscore.cfio_regs_com_cfg_score_pb_config.sb_clkgaten +E(SSUS, 0x4900, MASK_VAL(16, 16, 0x1)), //vlv.gpio.gpssus.cfio_regs_com_cfg_ssus_pb_config.sb_clkgaten +E(LPSS, 0x180, MASK_VAL(1, 1, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_clk_gate_en +E(LPSS, 0x180, MASK_VAL(4, 4, 0x1)), //vlv.lpss.iosf2ahb.pmctl.ahb_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(0, 0, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosf_clk_gate_enable +E(LPSS, 0x180, MASK_VAL(3, 3, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfprim_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(5, 5, 0x1)), //vlv.lpss.iosf2ahb.pmctl.iosfsb_trunk_gate_enable +E(LPSS, 0x180, MASK_VAL(2, 2, 0x1)), //vlv.lpss.iosf2ahb.pmctl.side_clk_gate_enable + //0x54, 0xfc, 31, 0, 0x0, //vlv.pcu.iosfahbep.clock_gating_control + //0x55, 0xfc, 1, 1, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_local_cgd + //0x55, 0xfc, 0, 0, 0x0, //vlv.pcu.smbus.smb_config_cgc.pri_trunk_cgd + //0x55, 0xfc, 8, 8, 0x0, //vlv.pcu.smbus.smb_config_cgc.sb_trunk_cgd +E(SCC, 0x600, MASK_VAL(31, 15, 0x5)), //vlv.scc.iosf2ocp.gen_regrw1.gen_reg_rw1 +E(SCC, 0x1e0, MASK_VAL(4, 4, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprim_trunk_gate_en +E(SCC, 0x1e0, MASK_VAL(0, 0, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfprimclk_gate_en +E(SCC, 0x1e0, MASK_VAL(5, 5, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsb_trunk_gate_en +E(SCC, 0x1e0, MASK_VAL(3, 3, 0x1)), //vlv.scc.iosf2ocp.pmctl.iosfsbclk_gate_en +E(SCC, 0x1e0, MASK_VAL(1, 1, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_gate_en +E(SCC, 0x1e0, MASK_VAL(2, 2, 0x1)), //vlv.scc.iosf2ocp.pmctl.ocpclk_trunk_gate_en +E(SEC, 0x88, MASK_VAL(7, 7, 0x0)), //vlv.sec.clk_gate_dis.nfc_cg_dis +E(SEC, 0x88, MASK_VAL(1, 1, 0x0)), //vlv.sec.clk_gate_dis.prim_cg_dis +E(SEC, 0x88, MASK_VAL(2, 2, 0x0)), //vlv.sec.clk_gate_dis.prim_clkreq_dis +E(SEC, 0x88, MASK_VAL(3, 3, 0x0)), //vlv.sec.clk_gate_dis.prim_xsm_clkreq_dis +E(SEC, 0x88, MASK_VAL(4, 4, 0x0)), //vlv.sec.clk_gate_dis.sap_cg_dis +E(SEC, 0x88, MASK_VAL(6, 6, 0x0)), //vlv.sec.clk_gate_dis.sap_clkidle_dis +E(SEC, 0x88, MASK_VAL(5, 5, 0x0)), //vlv.sec.clk_gate_dis.sap_ip_cg_dis +E(SEC, 0x88, MASK_VAL(0, 0, 0x0)), //vlv.sec.clk_gate_dis.sb_cg_dis +REG_SCRIPT_END, +}; + + +static void perf_power(void *unused) +{ + printk(BIOS_DEBUG, "Applying perf/power settings.\n"); + reg_script_run(perf_power_settings); +} + +BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), + BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), +};

1 0

Patch set updated for coreboot: 73642fb baytrail: utilize reg_script_run_on_dev()
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5009 -gerrit commit 73642fb6a4476c18cb0f0958f4b59cdea6b148a1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 17:12:44 2013 -0800 baytrail: utilize reg_script_run_on_dev() The inclusion of reg_script_run_on_dev() allows for removing some of the chained reg_scripts just to set up the device context. Use the new reg_script function in those cases. BUG=None BRANCH=None TEST=Built and booted. Didn't see any bizarre dmesg or coreboot console output. Change-Id: I3207449424c1efe92186125004d5aea1bb5ba438 Signed-off-by: Aaron Durbin <adurbin(a)chromium.og> Reviewed-on: https://chromium-review.googlesource.com/179541 Tested-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/ehci.c | 28 +++++++++++----------------- src/soc/intel/baytrail/emmc.c | 9 ++------- src/soc/intel/baytrail/gfx.c | 15 ++++----------- src/soc/intel/baytrail/lpss.c | 11 ++++------- src/soc/intel/baytrail/pcie.c | 11 ++--------- src/soc/intel/baytrail/scc.c | 3 +-- src/soc/intel/baytrail/xhci.c | 11 ++++------- 7 files changed, 28 insertions(+), 60 deletions(-) diff --git a/src/soc/intel/baytrail/ehci.c b/src/soc/intel/baytrail/ehci.c index c648415..d4e2986 100644 --- a/src/soc/intel/baytrail/ehci.c +++ b/src/soc/intel/baytrail/ehci.c @@ -34,7 +34,7 @@ #include "chip.h" -const struct reg_script ehci_init_script[] = { +static const struct reg_script ehci_init_script[] = { /* Enable S0 PLL shutdown * D29:F0:7A[12,10,7,6,4,3,2,1]=11111111b */ REG_PCI_OR16(0x7a, 0x14de), @@ -60,7 +60,7 @@ const struct reg_script ehci_init_script[] = { REG_SCRIPT_END }; -const struct reg_script ehci_clock_gating_script[] = { +static const struct reg_script ehci_clock_gating_script[] = { /* Enable SB local clock gating */ REG_PCI_OR32(0x7c, 0x00004000), /* RCBA + 0x284=0xbe (step B0+) */ @@ -68,7 +68,7 @@ const struct reg_script ehci_clock_gating_script[] = { REG_SCRIPT_END }; -const struct reg_script ehci_disable_script[] = { +static const struct reg_script ehci_disable_script[] = { /* Clear Run/Stop Bit */ REG_RES_RMW32(PCI_BASE_ADDRESS_0, USB2CMD, ~USB2CMD_RS, 0), /* Wait for HC Halted */ @@ -86,6 +86,11 @@ const struct reg_script ehci_disable_script[] = { REG_SCRIPT_END }; +static const struct reg_script ehci_hc_reset[] = { + REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), + REG_SCRIPT_END +}; + static void usb2_phy_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -121,18 +126,7 @@ static void usb2_phy_init(device_t dev) static void ehci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ehci_hc_reset[] = { - REG_SCRIPT_SET_DEV(dev), - REG_RES_OR16(PCI_BASE_ADDRESS_0, USB2CMD, USB2CMD_HCRESET), - REG_SCRIPT_END - }; - struct reg_script ehci_hc_disable[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(ehci_disable_script), - REG_SCRIPT_END - }; struct reg_script ehci_hc_init[] = { - REG_SCRIPT_SET_DEV(dev), /* Controller init */ REG_SCRIPT_NEXT(ehci_init_script), /* Enable clock gating */ @@ -150,19 +144,19 @@ static void ehci_init(device_t dev) /* Don't reset controller in S3 resume path */ if (acpi_slp_type != 3) - reg_script_run(ehci_hc_reset); + reg_script_run_on_dev(dev, ehci_hc_reset); /* Disable controller if ports are routed to XHCI */ if (config->usb_route_to_xhci) { /* Disable controller */ - reg_script_run(ehci_hc_disable); + reg_script_run_on_dev(dev, ehci_disable_script); /* Hide device with southcluster function */ dev->enabled = 0; southcluster_enable_dev(dev); } else { /* Initialize EHCI controller */ - reg_script_run(ehci_hc_init); + reg_script_run_on_dev(dev, ehci_hc_init); } /* Setup USB2 PHY based on board config */ diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 0a7e9b1..a724c4a 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -52,16 +52,11 @@ static const struct reg_script emmc_ops[] = { static void emmc_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(emmc_ops), - REG_SCRIPT_END, - }; - printk(BIOS_DEBUG, "eMMC init\n"); - reg_script_run(ops); if (config->scc_acpi_mode) scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); + printk(BIOS_DEBUG, "eMMC init\n"); + reg_script_run_on_dev(dev, emmc_ops); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index d2a8ba5..6f78dac 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -259,14 +259,9 @@ static const struct reg_script gfx_post_vbios_script[] = { REG_SCRIPT_END }; -static void gfx_run_script(device_t dev, const struct reg_script *ops) +static inline void gfx_run_script(device_t dev, const struct reg_script *ops) { - struct reg_script steps[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(ops), - REG_SCRIPT_END, - }; - reg_script_run(&steps[0]); + reg_script_run_on_dev(dev, ops); } static void gfx_pre_vbios_init(device_t dev) @@ -294,7 +289,6 @@ static void gfx_panel_setup(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script gfx_pipea_init[] = { - REG_SCRIPT_SET_DEV(dev), /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), @@ -322,7 +316,6 @@ static void gfx_panel_setup(device_t dev) REG_SCRIPT_END }; struct reg_script gfx_pipeb_init[] = { - REG_SCRIPT_SET_DEV(dev), /* CONTROL */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), @@ -352,12 +345,12 @@ static void gfx_panel_setup(device_t dev) if (config->gpu_pipea_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); - reg_script_run(gfx_pipea_init); + reg_script_run_on_dev(dev, gfx_pipea_init); } if (config->gpu_pipeb_port_select) { printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); - reg_script_run(gfx_pipeb_init); + reg_script_run_on_dev(dev, gfx_pipeb_init); } } diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index e009c7d..a543fd8 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -36,7 +36,6 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), @@ -68,20 +67,19 @@ static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.lpss_en[nvs_index] = 1; /* Put device in ACPI mode */ - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), REG_IOSF_RMW(IOSF_PORT_LPSS, iosf_reg, ~(LPSS_CTL_SNOOP | LPSS_CTL_NOSNOOP), LPSS_CTL_SNOOP | LPSS_CTL_PM_CAP_PRSNT), REG_SCRIPT_END, }; - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) @@ -128,8 +126,7 @@ static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) static void i2c_disable_resets(device_t dev) { /* Release the I2C devices from reset. */ - struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), + static const struct reg_script ops[] = { REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x804, 0x3), REG_SCRIPT_END, }; @@ -146,7 +143,7 @@ static void i2c_disable_resets(device_t dev) CASE_I2C(I2C6): CASE_I2C(I2C7): printk(BIOS_DEBUG, "Releasing I2C device from reset.\n"); - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); break; default: return; diff --git a/src/soc/intel/baytrail/pcie.c b/src/soc/intel/baytrail/pcie.c index f68304d..ce76d6d 100644 --- a/src/soc/intel/baytrail/pcie.c +++ b/src/soc/intel/baytrail/pcie.c @@ -90,7 +90,6 @@ static const struct reg_script init_static_after_exit_latency[] = { static void byt_pcie_init(device_t dev) { struct reg_script init_script[] = { - REG_SCRIPT_SET_DEV(dev), REG_SCRIPT_NEXT(init_static_before_exit_latency), /* Exit latency configuration based on * PHYCTL2_IOSFBCTL[PLL_OFF_EN] set in root port 1*/ @@ -108,7 +107,7 @@ static void byt_pcie_init(device_t dev) REG_SCRIPT_END, }; - reg_script_run(init_script); + reg_script_run_on_dev(dev, init_script); if (is_first_port(dev)) { struct soc_intel_baytrail_config *config = dev->chip_info; @@ -157,19 +156,13 @@ static void check_port_enabled(device_t dev) static void check_device_present(device_t dev) { - struct reg_script no_dev[] = { - REG_SCRIPT_SET_DEV(dev), - REG_SCRIPT_NEXT(no_dev_behind_port), - REG_SCRIPT_END, - }; - /* Set slot implemented. */ pci_write_config32(dev, XCAP, pci_read_config32(dev, XCAP) | SI); /* No device present. */ if (!(pci_read_config32(dev, SLCTL_SLSTS) & PDS)) { printk(BIOS_DEBUG, "No PCIe device present.\n"); - reg_script_run(no_dev); + reg_script_run_on_dev(dev, no_dev_behind_port); dev->enabled = 0; } else if(!dev->enabled) { /* Port is disabled, but device present. Disable link. */ diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index 64792c2..7efb66d 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -90,7 +90,6 @@ void baytrail_init_scc(void) void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) { struct reg_script ops[] = { - REG_SCRIPT_SET_DEV(dev), /* Disable PCI interrupt, enable Memory and Bus Master */ REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), @@ -122,5 +121,5 @@ void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) gnvs->dev.scc_en[nvs_index] = 1; /* Put device in ACPI mode */ - reg_script_run(ops); + reg_script_run_on_dev(dev, ops); } diff --git a/src/soc/intel/baytrail/xhci.c b/src/soc/intel/baytrail/xhci.c index 30e6098..e3facb9 100644 --- a/src/soc/intel/baytrail/xhci.c +++ b/src/soc/intel/baytrail/xhci.c @@ -132,7 +132,6 @@ const struct reg_script xhci_clock_gating_script[] = { static void xhci_reset_port_usb3(device_t dev, int port) { struct reg_script reset_port_usb3_script[] = { - REG_SCRIPT_SET_DEV(dev), /* Issue Warm Port Rest to the port */ REG_RES_OR32(PCI_BASE_ADDRESS_0, XHCI_USB3_PORTSC(port), XHCI_USB3_PORTSC_WPR), @@ -145,14 +144,13 @@ static void xhci_reset_port_usb3(device_t dev, int port) ~XHCI_USB3_PORTSC_PED, XHCI_USB3_PORTSC_CHST), REG_SCRIPT_END }; - reg_script_run(reset_port_usb3_script); + reg_script_run_on_dev(dev, reset_port_usb3_script); } /* Prepare ports to be routed to EHCI or XHCI */ static void xhci_route_all(device_t dev) { - struct reg_script xhci_route_all_script[] = { - REG_SCRIPT_SET_DEV(dev), + static const struct reg_script xhci_route_all_script[] = { /* USB3 SuperSpeed Enable */ REG_PCI_WRITE32(XHCI_USB3PR, BYTM_USB3_PORT_MAP), /* USB2 Port Route to XHCI */ @@ -165,7 +163,7 @@ static void xhci_route_all(device_t dev) printk(BIOS_INFO, "USB: Route ports to XHCI controller\n"); /* Route ports to XHCI controller */ - reg_script_run(xhci_route_all_script); + reg_script_run_on_dev(dev, xhci_route_all_script); /* Reset enabled USB3 ports */ port_disabled = pci_read_config32(dev, XHCI_USB3PDO); @@ -180,7 +178,6 @@ static void xhci_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script xhci_hc_init[] = { - REG_SCRIPT_SET_DEV(dev), /* Setup USB3 phy */ REG_SCRIPT_NEXT(usb3_phy_script), /* Initialize host controller */ @@ -207,7 +204,7 @@ static void xhci_init(device_t dev) }; /* Initialize XHCI controller */ - reg_script_run(xhci_hc_init); + reg_script_run_on_dev(dev, xhci_hc_init); /* Route all ports to XHCI if requested */ if (config->usb_route_to_xhci)

1 0

Patch set updated for coreboot: 7d355c1 baytrail: note S3 resume status earlier
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5010 -gerrit commit 7d355c15ab3a73673c63fdf1b4fd2ce4d4586a3f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:07:00 2013 -0800 baytrail: note S3 resume status earlier Certain code paths want to know if S3 resume is happening. However, the current baytrail code doesn't note S3 resume early enough. Therefore, mark S3 resume just after pattr setup. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I5e5cc285940e4567521afb8483614ce6f813ddde Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179774 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/ramstage.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/ramstage.c b/src/soc/intel/baytrail/ramstage.c index b0b48b0..9fe6c27 100644 --- a/src/soc/intel/baytrail/ramstage.c +++ b/src/soc/intel/baytrail/ramstage.c @@ -159,6 +159,9 @@ void baytrail_init_pre_device(void) /* Allow for SSE instructions to be executed. */ write_cr4(read_cr4() | CR4_OSFXSR | CR4_OSXMMEXCPT); + /* Indicate S3 resume to rest of ramstage. */ + s3_resume_prepare(); + /* Run reference code. */ baytrail_run_reference_code(); @@ -167,7 +170,4 @@ void baytrail_init_pre_device(void) setup_soc_gpios(config); baytrail_init_scc(); - - /* Indicate S3 resume to rest of ramstage. */ - s3_resume_prepare(); }

1 0

Patch set updated for coreboot: fb45fae ramstage_cache: allow ramstage usage add valid helper
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5011 -gerrit commit fb45fae5c7028ee7754bdda7c7790b67dfb8c4ee Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:10:52 2013 -0800 ramstage_cache: allow ramstage usage add valid helper Allow ramstage cache to be used from ramstage proper. Also add a helper function for checking validity of ramstage cache structure. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: If1f2ad1bcf64504b42e315be243a12432b50e3d5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179775 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/ramstage_cache.h | 10 +++++++--- src/lib/ramstage_cache.c | 2 +- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/include/ramstage_cache.h b/src/include/ramstage_cache.h index 5b0597a..8d9b095 100644 --- a/src/include/ramstage_cache.h +++ b/src/include/ramstage_cache.h @@ -20,9 +20,8 @@ #ifndef _RAMSTAGE_CACHE_ #define _RAMSTAGE_CACHE_ -#if !defined(__PRE_RAM__) -#error "ramstage_cache only used in romstage for loading ramstage." -#endif +#include <stddef.h> +#include <stdint.h> /* This structure is saved along with the relocated ramstage program when * CONFIG_RELOCATED_RAMSTAGE is employed. For x86, it can used to protect @@ -46,4 +45,9 @@ struct ramstage_cache *ramstage_cache_location(long *size); /* Chipset/Board function called when cache is invalid on resume. */ void ramstage_cache_invalid(struct ramstage_cache *cache); +static inline int ramstage_cache_is_valid(const struct ramstage_cache *c) +{ + return (c != NULL && c->magic == RAMSTAGE_CACHE_MAGIC); +} + #endif /* _RAMSTAGE_CACHE_ */ diff --git a/src/lib/ramstage_cache.c b/src/lib/ramstage_cache.c index a1a4804..0f7273a 100644 --- a/src/lib/ramstage_cache.c +++ b/src/lib/ramstage_cache.c @@ -79,7 +79,7 @@ void *load_cached_ramstage(struct romstage_handoff *handoff, cache = ramstage_cache_location(&size); - if (cache == NULL || cache->magic != RAMSTAGE_CACHE_MAGIC) { + if (!ramstage_cache_is_valid(cache)) { printk(BIOS_DEBUG, "Invalid ramstage cache found.\n"); ramstage_cache_invalid(cache); return NULL;

1 0

Patch set updated for coreboot: 1733135 baytrail: allow ramstage_cache_location() usage in ramstage
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5012 -gerrit commit 1733135c6d1e5f930ee87804c477a0a13d860245 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:27:11 2013 -0800 baytrail: allow ramstage_cache_location() usage in ramstage To prepare for caching reference code for S3 resume the ramstage cache needs to be accesible in ramstage as well. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I4c825c965b98cd71ea0eb9c93fe168a358da4c97 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179776 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 2 ++ src/soc/intel/baytrail/romstage/romstage.c | 13 ----------- src/soc/intel/baytrail/stage_cache.c | 35 ++++++++++++++++++++++++++++++ 3 files changed, 37 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index e2a949f..aff09be 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -45,6 +45,8 @@ ramstage-y += lpss.c ramstage-y += pcie.c ramstage-y += sd.c ramstage-y += perf_power.c +ramstage-y += stage_cache.c +romstage-y += stage_cache.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 8436c65..cb884bd 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -355,19 +355,6 @@ static void *setup_stack_and_mttrs(void) return slot; } -struct ramstage_cache *ramstage_cache_location(long *size) -{ - char *smm_base; - /* 1MiB cache size */ - const long cache_size = CONFIG_SMM_RESERVED_SIZE; - - /* Ramstage cache lives in TSEG region which is the definition of - * cbmem_top(). */ - smm_base = cbmem_top(); - *size = cache_size; - return (void *)&smm_base[smm_region_size() - cache_size]; -} - void ramstage_cache_invalid(struct ramstage_cache *cache) { #if CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE diff --git a/src/soc/intel/baytrail/stage_cache.c b/src/soc/intel/baytrail/stage_cache.c new file mode 100644 index 0000000..3bda56d --- /dev/null +++ b/src/soc/intel/baytrail/stage_cache.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> +#include <ramstage_cache.h> +#include <baytrail/smm.h> + +struct ramstage_cache *ramstage_cache_location(long *size) +{ + char *smm_base; + /* 1MiB cache size */ + const long cache_size = CONFIG_SMM_RESERVED_SIZE; + + /* Ramstage cache lives in TSEG region which is the definition of + * cbmem_top(). */ + smm_base = cbmem_top(); + *size = cache_size; + return (void *)&smm_base[smm_region_size() - cache_size]; +}

1 0

Patch set updated for coreboot: ad2f2a5 baytrail: cache reference code for S3 resume
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5013 -gerrit commit ad2f2a5b77202a3e5ead9c0beeb20e50c5c52c52 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Dec 12 10:29:48 2013 -0800 baytrail: cache reference code for S3 resume In order to use the same reference code on S3 resume that was booted the program needs to be cached. Piggy back on the ramstage cache to save the loaded reference code program. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. S3 resumed. Noted locations of reference code caching and load addresses in console. Change-Id: I90ceaf5697e8c269c3244370519d4d8a8ee2eb4a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179777 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/refcode.c | 109 ++++++++++++++++++++++++++++++++++++--- 1 file changed, 101 insertions(+), 8 deletions(-) diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index 9b5aa67..f746358 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -17,19 +17,113 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <string.h> +#include <arch/acpi.h> #include <cbmem.h> #include <console/console.h> #include <cpu/x86/tsc.h> #include <rmodule.h> +#include <ramstage_cache.h> #include <baytrail/ramstage.h> #include <baytrail/efi_wrapper.h> +static inline int is_s3_resume(void) +{ +#if CONFIG_HAVE_ACPI_RESUME + return acpi_slp_type == 3; +#else + return 0; +#endif +} + +static inline struct ramstage_cache *next_cache(struct ramstage_cache *c) +{ + return (struct ramstage_cache *)&c->program[c->size]; +} + static void ABI_X86 send_to_console(unsigned char b) { console_tx_byte(b); } +static efi_wrapper_entry_t load_refcode_from_cache(void) +{ + struct ramstage_cache *c; + long cache_size; + + printk(BIOS_DEBUG, "refcode loading from cache.\n"); + + c = ramstage_cache_location(&cache_size); + + if (!ramstage_cache_is_valid(c)) { + printk(BIOS_DEBUG, "Invalid ramstage cache descriptor.\n"); + return NULL; + } + + c = next_cache(c); + if (!ramstage_cache_is_valid(c)) { + printk(BIOS_DEBUG, "Invalid refcode cache descriptor.\n"); + return NULL; + } + + printk(BIOS_DEBUG, "Loading cached reference code from 0x%08x(%x)\n", + c->load_address, c->size); + memcpy((void *)c->load_address, &c->program[0], c->size); + + return (efi_wrapper_entry_t)c->entry_point; +} + +static void cache_refcode(const struct rmod_stage_load *rsl) +{ + struct ramstage_cache *c; + long cache_size; + + c = ramstage_cache_location(&cache_size); + + if (!ramstage_cache_is_valid(c)) { + printk(BIOS_DEBUG, "No place to cache reference code.\n"); + return; + } + + /* Determine how much remaining cache available. */ + cache_size -= c->size + sizeof(*c); + + if (cache_size < (sizeof(*c) + cbmem_entry_size(rsl->cbmem_entry))) { + printk(BIOS_DEBUG, "Not enough cache space for ref code.\n"); + return; + } + + c = next_cache(c); + c->magic = RAMSTAGE_CACHE_MAGIC; + c->entry_point = (uint32_t)rsl->entry; + c->load_address = (uint32_t)cbmem_entry_start(rsl->cbmem_entry); + c->size = cbmem_entry_size(rsl->cbmem_entry);; + + printk(BIOS_DEBUG, "Caching refcode at 0x%p(%x)\n", + &c->program[0], c->size); + memcpy(&c->program[0], (void *)c->load_address, c->size); +} + +static efi_wrapper_entry_t load_refcode_from_cbfs(void) +{ + struct rmod_stage_load refcode = { + .cbmem_id = CBMEM_ID_REFCODE, + .name = CONFIG_CBFS_PREFIX "/refcode", + }; + + printk(BIOS_DEBUG, "refcode loading from cbfs.\n"); + + if (rmodule_stage_load_from_cbfs(&refcode) || refcode.entry == NULL) { + printk(BIOS_DEBUG, "Error loading reference code.\n"); + return NULL; + } + + cache_refcode(&refcode); + + return refcode.entry; +} + void baytrail_run_reference_code(void) { int ret; @@ -38,18 +132,17 @@ void baytrail_run_reference_code(void) .version = EFI_WRAPPER_VER, .console_out = send_to_console, }; - struct rmod_stage_load refcode = { - .cbmem_id = CBMEM_ID_REFCODE, - .name = CONFIG_CBFS_PREFIX "/refcode", - }; - if (rmodule_stage_load_from_cbfs(&refcode) || refcode.entry == NULL) { - printk(BIOS_DEBUG, "Error loading reference code.\n"); - return; + if (is_s3_resume()) { + entry = load_refcode_from_cache(); + } else { + entry = load_refcode_from_cbfs(); } + if (entry == NULL) + return; + wrp.tsc_ticks_per_microsecond = tsc_freq_mhz(); - entry = refcode.entry; /* Call into reference code. */ ret = entry(&wrp);

1 0

Patch set updated for coreboot: 2a86d04 reg_script: add reg_script_run_on_dev()
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5005 -gerrit commit 2a86d04bf88be6c9f68d589f85da7881d02ef484 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 17:09:40 2013 -0800 reg_script: add reg_script_run_on_dev() The reg_script library has proven to be useful. It's also shown that many scripts operate on devices. However, certain code paths run the same script on multiple, but different, devices. In order to make that easier introduce reg_script_run_on_dev() which takes a device as a parameter. That way, chained reg_scripts are not scrictly needed to run the same script on multiple devices. BUG=None BRANCH=None TEST=Built. Change-Id: I273499af4d303ebd7dc19e9b635ca23cf9bb2225 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179540 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/reg_script.h | 1 + src/lib/reg_script.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/include/reg_script.h b/src/include/reg_script.h index 81a4648..72e1e96 100644 --- a/src/include/reg_script.h +++ b/src/include/reg_script.h @@ -334,5 +334,6 @@ struct reg_script { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0) void reg_script_run(const struct reg_script *script); +void reg_script_run_on_dev(device_t dev, const struct reg_script *step); #endif /* REG_SCRIPT_H */ diff --git a/src/lib/reg_script.c b/src/lib/reg_script.c index d7c4577..0655520 100644 --- a/src/lib/reg_script.c +++ b/src/lib/reg_script.c @@ -468,11 +468,16 @@ static void reg_script_run_next(struct reg_script_context *prev_ctx, reg_script_run_with_context(&ctx); } -void reg_script_run(const struct reg_script *step) +void reg_script_run_on_dev(device_t dev, const struct reg_script *step) { struct reg_script_context ctx; - reg_script_set_dev(&ctx, EMPTY_DEV); + reg_script_set_dev(&ctx, dev); reg_script_set_step(&ctx, step); reg_script_run_with_context(&ctx); } + +void reg_script_run(const struct reg_script *step) +{ + reg_script_run_on_dev(EMPTY_DEV, step); +}

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Patch set updated for coreboot: 0e57e4f baytrail: Add support for LPSS and SCC devices in ACPI mode
by Aaron Durbin 09 May '14

09 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5004 -gerrit commit 0e57e4fade664c4d9b136d4307d2ee988f7102ba Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 10 14:37:42 2013 -0800 baytrail: Add support for LPSS and SCC devices in ACPI mode This adds the option to put LPSS and SCC devices into ACPI mode by saving their BAR0 and BAR1 base addresses in a new device NVS structure that is placed at offset 0x1000 within the global NVS table. The Chrome NVS strcture is padded out to 0xf00 bytes so there is a clean offset to work with as it will need to be used by depthcharge to know what addresses devices live at. A few ACPI Mode IRQs are fixed up, DMA1 and DMA2 are swapped and the EMMC 4.5 IRQ is changed to 44. New ACPI code is provided to instantiate the LPSS and SCC devices with the magic HID values from Intel so the kernel drivers can locate and use them. The default is still for devices to be in PCI mode so this does not have any real effect without it being enabled in the mainboard devicetree. Note: this needs the updated IASL compiler which is in the CQ now because it uses the FixedDMA() ACPI operator. BUG=chrome-os-partner:23505,chrome-os-partner:24380 CQ-DEPEND=CL:179459,CL:179364 BRANCH=none TEST=manual tests on rambi device: 1) build and boot with devices still in PCI mode and ensure that nothing is changed 2) enable lpss_acpi_mode and see I2C devices detected by the kernel in ACPI mode. Note that by itself this breaks trackpad probing so that will need to be implemented before it is enabled. 3) enable scc_acpi_mode and see EMMC and SDCard devices detected by the kernel in ACPI mode. Note that this breaks depthcharge use of the EMMC because it is not longer discoverable as a PCI device. Change-Id: I2a007f3c4e0b06ace5172a15c696a8eaad41ed73 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179481 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/acpi/device_nvs.asl | 87 ++++ src/soc/intel/baytrail/acpi/globalnvs.asl | 24 +- src/soc/intel/baytrail/acpi/lpss.asl | 670 +++++++++++++++++++++++++++ src/soc/intel/baytrail/acpi/scc.asl | 187 ++++++++ src/soc/intel/baytrail/acpi/southcluster.asl | 14 +- src/soc/intel/baytrail/baytrail/device_nvs.h | 59 +++ src/soc/intel/baytrail/baytrail/iosf.h | 9 + src/soc/intel/baytrail/baytrail/irq.h | 6 +- src/soc/intel/baytrail/baytrail/nvs.h | 16 +- src/soc/intel/baytrail/baytrail/ramstage.h | 1 + src/soc/intel/baytrail/chip.h | 5 + src/soc/intel/baytrail/emmc.c | 6 + src/soc/intel/baytrail/lpss.c | 58 ++- src/soc/intel/baytrail/scc.c | 43 ++ src/soc/intel/baytrail/sd.c | 5 + 15 files changed, 1152 insertions(+), 38 deletions(-) diff --git a/src/soc/intel/baytrail/acpi/device_nvs.asl b/src/soc/intel/baytrail/acpi/device_nvs.asl new file mode 100644 index 0000000..fce7b53 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/device_nvs.asl @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +/* Device Enabled in ACPI Mode */ + +S0EN, 8, // SDMA Enable +S1EN, 8, // I2C1 Enable +S2EN, 8, // I2C2 Enable +S3EN, 8, // I2C3 Enable +S4EN, 8, // I2C4 Enable +S5EN, 8, // I2C5 Enable +S6EN, 8, // I2C6 Enable +S7EN, 8, // I2C7 Enable +S8EN, 8, // SDMA2 Enable +S9EN, 8, // SPI Enable +SAEN, 8, // PWM1 Enable +SBEN, 8, // PWM2 Enable +SCEN, 8, // UART2 Enable +SDEN, 8, // UART2 Enable +C0EN, 8, // MMC Enable +C1EN, 8, // SDIO Enable +C2EN, 8, // SD Card Enable +LPEN, 8, // LPE Enable + +/* BAR 0 */ + +S0B0, 32, // SDMA BAR0 +S1B0, 32, // I2C1 BAR0 +S2B0, 32, // I2C2 BAR0 +S3B0, 32, // I2C3 BAR0 +S4B0, 32, // I2C4 BAR0 +S5B0, 32, // I2C5 BAR0 +S6B0, 32, // I2C6 BAR0 +S7B0, 32, // I2C7 BAR0 +S8B0, 32, // SDMA2 BAR0 +S9B0, 32, // SPI BAR0 +SAB0, 32, // PWM1 BAR0 +SBB0, 32, // PWM2 BAR0 +SCB0, 32, // UART1 BAR0 +SDB0, 32, // UART2 BAR0 +C0B0, 32, // MMC BAR0 +C1B0, 32, // SDIO BAR0 +C2B0, 32, // SD Card BAR0 +LPB0, 32, // LPE BAR0 + +/* BAR 1 */ + +S0B1, 32, // SDMA BAR1 +S1B1, 32, // I2C1 BAR1 +S2B1, 32, // I2C2 BAR1 +S3B1, 32, // I2C3 BAR1 +S4B1, 32, // I2C4 BAR1 +S5B1, 32, // I2C5 BAR1 +S6B1, 32, // I2C6 BAR1 +S7B1, 32, // I2C7 BAR1 +S8B1, 32, // SDMA2 BAR1 +S9B1, 32, // SPI BAR1 +SAB1, 32, // PWM1 BAR1 +SBB1, 32, // PWM2 BAR1 +SCB1, 32, // UART1 BAR1 +SDB1, 32, // UART2 BAR1 +C0B1, 32, // MMC BAR1 +C1B1, 32, // SDIO BAR1 +C2B1, 32, // SD Card BAR1 +LPB1, 32, // LPE BAR1 + +/* Extra */ + +LPFW, 32, // LPE BAR2 Firmware diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index cd00824..b384cea 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -30,7 +30,7 @@ Name(\PICM, 0) // IOAPIC/8259 */ -OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0xf00) +OperationRegion (GNVS, SystemMemory, 0xC0DEBABE, 0x2000) Field (GNVS, ByteAcc, NoLock, Preserve) { /* Miscellaneous */ @@ -70,28 +70,12 @@ Field (GNVS, ByteAcc, NoLock, Preserve) TOLM, 32, // 0x34 - Top of Low Memory CBMC, 32, // 0x38 - coreboot mem console pointer - /* Serial IO device BARs */ - Offset (0x60), - S0B0, 32, // 0x60 - D21:F0 Serial IO SDMA BAR0 - S1B0, 32, // 0x64 - D21:F1 Serial IO I2C0 BAR0 - S2B0, 32, // 0x68 - D21:F2 Serial IO I2C1 BAR0 - S3B0, 32, // 0x6c - D21:F3 Serial IO SPI0 BAR0 - S4B0, 32, // 0x70 - D21:F4 Serial IO SPI1 BAR0 - S5B0, 32, // 0x74 - D21:F5 Serial IO UAR0 BAR0 - S6B0, 32, // 0x78 - D21:F6 Serial IO UAR1 BAR0 - S7B0, 32, // 0x7c - D23:F0 Serial IO SDIO BAR0 - S0B1, 32, // 0x80 - D21:F0 Serial IO SDMA BAR1 - S1B1, 32, // 0x84 - D21:F1 Serial IO I2C0 BAR1 - S2B1, 32, // 0x88 - D21:F2 Serial IO I2C1 BAR1 - S3B1, 32, // 0x8c - D21:F3 Serial IO SPI0 BAR1 - S4B1, 32, // 0x90 - D21:F4 Serial IO SPI1 BAR1 - S5B1, 32, // 0x94 - D21:F5 Serial IO UAR0 BAR1 - S6B1, 32, // 0x98 - D21:F6 Serial IO UAR1 BAR1 - S7B1, 32, // 0x9c - D23:F0 Serial IO SDIO BAR1 - /* ChromeOS specific */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> + + Offset (0x1000), + #include <soc/intel/baytrail/acpi/device_nvs.asl> } /* Set flag to enable USB charging in S3 */ diff --git a/src/soc/intel/baytrail/acpi/lpss.asl b/src/soc/intel/baytrail/acpi/lpss.asl new file mode 100644 index 0000000..f56c6a8 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/lpss.asl @@ -0,0 +1,670 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (SDM1) +{ + Name (_HID, "INTL9C60") + Name (_UID, 1) + Name (_DDN, "DMA Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA1_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (SDM2) +{ + Name (_HID, "INTL9C60") + Name (_UID, 2) + Name (_DDN, "DMA Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_DMA2_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S8B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S8EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (I2C1) +{ + Name (_HID, "80860F41") + Name (_UID, 1) + Name (_DDN, "I2C Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C1_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C2) +{ + Name (_HID, "80860F41") + Name (_UID, 2) + Name (_DDN, "I2C Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C2_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C3) +{ + Name (_HID, "80860F41") + Name (_UID, 3) + Name (_DDN, "I2C Controller #3") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C3_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S3B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S3EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S3B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C4) +{ + Name (_HID, "80860F41") + Name (_UID, 4) + Name (_DDN, "I2C Controller #4") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C4_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S4B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S4EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S4B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C5) +{ + Name (_HID, "80860F41") + Name (_UID, 5) + Name (_DDN, "I2C Controller #5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C5_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S5B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S5B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C6) +{ + Name (_HID, "80860F41") + Name (_UID, 6) + Name (_DDN, "I2C Controller #6") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C6_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S6B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S6B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (I2C7) +{ + Name (_HID, "80860F41") + Name (_UID, 7) + Name (_DDN, "I2C Controller #7") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_I2C7_IRQ + } + FixedDMA (0x10, 0x0, Width32Bit, ) + FixedDMA (0x11, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S7B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S7EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S7B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SPI1) +{ + Name (_HID, "80860F0E") + Name (_UID, 1) + Name (_DDN, "SPI Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_SPI_IRQ + } + FixedDMA (0x0, 0x0, Width32Bit, ) + FixedDMA (0x1, 0x1, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\S9B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\S9EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, S9B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (PWM1) +{ + Name (_HID, "80860F09") + Name (_UID, 1) + Name (_DDN, "PWM Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SAB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SAEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (PWM2) +{ + Name (_HID, "80860F09") + Name (_UID, 2) + Name (_DDN, "PWM Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SBB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SBEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } +} + +Device (UAR1) +{ + Name (_HID, "80860F0A") + Name (_UID, 1) + Name (_DDN, "HS-UART Controller #1") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART1_IRQ + } + FixedDMA (0x2, 0x2, Width32Bit, ) + FixedDMA (0x3, 0x3, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SCB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SCEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SCB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (UAR2) +{ + Name (_HID, "80860F0A") + Name (_UID, 2) + Name (_DDN, "HS-UART Controller #2") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + LPSS_HSUART2_IRQ + } + FixedDMA (0x4, 0x4, Width32Bit, ) + FixedDMA (0x5, 0x5, Width32Bit, ) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\SDB0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\SDEN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, SDB1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/baytrail/acpi/scc.asl b/src/soc/intel/baytrail/acpi/scc.asl new file mode 100644 index 0000000..7181fb1 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/scc.asl @@ -0,0 +1,187 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (EMMC) +{ + Name (_HID, "80860F14") + Name (_CID, "PNP0D40") + Name (_UID, 1) + Name (_DDN, "eMMC Controller 4.5") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_EMMC_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C0B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C0EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C0B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Device (EM45) + { + /* Slot 0, Function 8 */ + Name (_ADR, 0x8) + + Method (_RMV, 0, NotSerialized) + { + Return (0) + } + } +} + +Device (SDIO) +{ + Name (_HID, "INT33BB") + Name (_CID, "PNP0D40") + Name (_UID, 2) + Name (_DDN, "SDIO Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SDIO_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C1B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C1B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} + +Device (SDCD) +{ + Name (_HID, "80860F16") + Name (_CID, "PNP0D40") + Name (_UID, 3) + Name (_DDN, "SD Card Controller") + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0x1000, BAR0) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive,,,) + { + SCC_SD_IRQ + } + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^BAR0._BAS, RBAS) + Store (\C2B0, RBAS) + Return (^RBUF) + } + + Method (_STA) + { + If (LEqual (\C2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + OperationRegion (KEYS, SystemMemory, C2B1, 0x100) + Field (KEYS, DWordAcc, NoLock, WriteAsZeros) + { + Offset (0x84), + PSAT, 32, + } + + Method (_PS3) + { + Or (PSAT, 0x00000003, PSAT) + Or (PSAT, 0x00000000, PSAT) + } + + Method (_PS0) + { + And (PSAT, 0xfffffffc, PSAT) + Or (PSAT, 0x00000000, PSAT) + } +} diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index 49349c4..cf27a24 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -20,6 +20,7 @@ */ #include <soc/intel/baytrail/baytrail/iomap.h> +#include <soc/intel/baytrail/baytrail/irq.h> Scope(\) { @@ -233,5 +234,14 @@ Method (_OSC, 4) // IRQ routing for each PCI device #include "irqroute.asl" -// GPIO Devices -#include "gpio.asl" +Scope (\_SB) +{ + // GPIO Devices + #include "gpio.asl" + + // LPSS Devices + #include "lpss.asl" + + // SCC Devices + #include "scc.asl" +} diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h new file mode 100644 index 0000000..dcb05d2 --- /dev/null +++ b/src/soc/intel/baytrail/baytrail/device_nvs.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> + +#define LPSS_NVS_SIO_DMA1 0 +#define LPSS_NVS_I2C1 1 +#define LPSS_NVS_I2C2 2 +#define LPSS_NVS_I2C3 3 +#define LPSS_NVS_I2C4 4 +#define LPSS_NVS_I2C5 5 +#define LPSS_NVS_I2C6 6 +#define LPSS_NVS_I2C7 7 +#define LPSS_NVS_SIO_DMA2 8 +#define LPSS_NVS_SPI 9 +#define LPSS_NVS_PWM1 10 +#define LPSS_NVS_PWM2 11 +#define LPSS_NVS_HSUART1 12 +#define LPSS_NVS_HSUART2 13 + +#define SCC_NVS_MMC 0 +#define SCC_NVS_SDIO 1 +#define SCC_NVS_SD 2 + +typedef struct { + /* Device Enabled in ACPI Mode */ + u8 lpss_en[14]; + u8 scc_en[3]; + u8 lpe_en; + + /* BAR 0 */ + u32 lpss_bar0[14]; + u32 scc_bar0[3]; + u32 lpe_bar0; + + /* BAR 0 */ + u32 lpss_bar1[14]; + u32 scc_bar1[3]; + u32 lpe_bar1; + + /* Extra */ + u32 lpe_fw; /* LPE Firmware */ +} __attribute__((packed)) device_nvs_t; diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 3a63d4a..d173901 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -211,6 +211,15 @@ void iosf_scc_write(int reg, uint32_t val); # define LPSS_CTL_PM_CAP_PRSNT (1 << 1) /* + * SCC Registers + */ +#define SCC_SD_CTL 0x504 +#define SCC_SDIO_CTL 0x508 +#define SCC_MMC_CTL 0x50c +# define SCC_CTL_PCI_CFG_DIS (1 << 0) +# define SCC_CTL_ACPI_INT_EN (1 << 1) + +/* * CCU Registers */ diff --git a/src/soc/intel/baytrail/baytrail/irq.h b/src/soc/intel/baytrail/baytrail/irq.h index deffad7..e66fab5 100644 --- a/src/soc/intel/baytrail/baytrail/irq.h +++ b/src/soc/intel/baytrail/baytrail/irq.h @@ -45,9 +45,9 @@ #define LPSS_HSUART1_IRQ 39 #define LPSS_HSUART2_IRQ 40 #define LPSS_SPI_IRQ 41 -#define LPSS_DMA2_IRQ 42 -#define LPSS_DMA1_IRQ 43 -#define SCC_EMMC_IRQ 45 +#define LPSS_DMA1_IRQ 42 +#define LPSS_DMA2_IRQ 43 +#define SCC_EMMC_IRQ 44 #define SCC_SDIO_IRQ 46 #define SCC_SD_IRQ 47 #define GPIO_NC_IRQ 48 diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index 8243ef3..09dee3a 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -18,7 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "vendorcode/google/chromeos/gnvs.h" +#include <vendorcode/google/chromeos/gnvs.h> +#include <baytrail/device_nvs.h> + typedef struct { /* Miscellaneous */ u16 osys; /* 0x00 - Operating System */ @@ -55,15 +57,13 @@ typedef struct { u32 cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd5[36]; - - /* Serial IO device BARs */ - u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ - u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ - u8 rsvd6[96]; + u8 rsvd3[196]; - /* ChromeOS specific (starts at 0x100)*/ + /* ChromeOS specific (0x100-0xfff)*/ chromeos_acpi_t chromeos; + + /* Baytrail LPSS (0x1000) */ + device_nvs_t dev; } __attribute__((packed)) global_nvs_t; #ifdef __SMM__ diff --git a/src/soc/intel/baytrail/baytrail/ramstage.h b/src/soc/intel/baytrail/baytrail/ramstage.h index 217c67b..d2e7e62 100644 --- a/src/soc/intel/baytrail/baytrail/ramstage.h +++ b/src/soc/intel/baytrail/baytrail/ramstage.h @@ -34,6 +34,7 @@ void baytrail_run_reference_code(void); static inline void baytrail_run_reference_code(void) {} #endif void baytrail_init_scc(void); +void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 2cc3fd6..955ecb0 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -56,6 +56,11 @@ struct soc_intel_baytrail_config { uint32_t sdcard_cap_low; uint32_t sdcard_cap_high; + /* Enable devices in ACPI mode */ + int lpss_acpi_mode; + int scc_acpi_mode; + int lpe_acpi_mode; + /* * Digital Port Hotplug Enable: * 0x04 = Enabled, 2ms short pulse diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index 18c16e8..0a7e9b1 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -26,8 +26,10 @@ #include <reg_script.h> #include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> +#include "chip.h" static const struct reg_script emmc_ops[] = { /* Enable 2ms card stable feature. */ @@ -49,6 +51,7 @@ static const struct reg_script emmc_ops[] = { static void emmc_init(device_t dev) { + struct soc_intel_baytrail_config *config = dev->chip_info; struct reg_script ops[] = { REG_SCRIPT_SET_DEV(dev), REG_SCRIPT_NEXT(emmc_ops), @@ -56,6 +59,9 @@ static void emmc_init(device_t dev) }; printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run(ops); + + if (config->scc_acpi_mode) + scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index ccfab38..e009c7d 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -19,6 +19,7 @@ #include <stdint.h> #include <arch/io.h> +#include <cbmem.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -26,9 +27,49 @@ #include <reg_script.h> #include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> +#include "chip.h" + +static void dev_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +{ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_LPSS, iosf_reg, + LPSS_CTL_PCI_CFG_DIS | LPSS_CTL_ACPI_INT_EN), + REG_SCRIPT_END + }; + struct resource *bar; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.lpss_bar0[nvs_index] = (u32)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.lpss_bar1[nvs_index] = (u32)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.lpss_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + reg_script_run(ops); +} static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) { @@ -43,12 +84,14 @@ static void dev_enable_snoop_and_pm(device_t dev, int iosf_reg) reg_script_run(ops); } -static int dev_ctl_reg(device_t dev) +static void dev_ctl_reg(device_t dev, int *iosf_reg, int *nvs_index) { - int iosf_reg = -1; + *iosf_reg = -1; + *nvs_index = -1; #define SET_IOSF_REG(name_) \ case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ - iosf_reg = LPSS_ ## name_ ## _CTL + *iosf_reg = LPSS_ ## name_ ## _CTL; \ + *nvs_index = LPSS_NVS_ ## name_ switch (dev->path.pci.devfn) { SET_IOSF_REG(SIO_DMA1); @@ -80,7 +123,6 @@ static int dev_ctl_reg(device_t dev) SET_IOSF_REG(SPI); break; } - return iosf_reg; } static void i2c_disable_resets(device_t dev) @@ -113,7 +155,10 @@ static void i2c_disable_resets(device_t dev) static void lpss_init(device_t dev) { - int iosf_reg = dev_ctl_reg(dev); + struct soc_intel_baytrail_config *config = dev->chip_info; + int iosf_reg, nvs_index; + + dev_ctl_reg(dev, &iosf_reg, &nvs_index); if (iosf_reg < 0) { int slot = PCI_SLOT(dev->path.pci.devfn); @@ -124,6 +169,9 @@ static void lpss_init(device_t dev) } dev_enable_snoop_and_pm(dev, iosf_reg); + if (config->lpss_acpi_mode) + dev_enable_acpi_mode(dev, iosf_reg, nvs_index); + i2c_disable_resets(dev); } diff --git a/src/soc/intel/baytrail/scc.c b/src/soc/intel/baytrail/scc.c index af941fa..64792c2 100644 --- a/src/soc/intel/baytrail/scc.c +++ b/src/soc/intel/baytrail/scc.c @@ -18,10 +18,15 @@ */ +#include <cbmem.h> #include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> #include <reg_script.h> #include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/ramstage.h> static const struct reg_script scc_start_dll[] = { @@ -81,3 +86,41 @@ void baytrail_init_scc(void) reg_script_run(scc_after_dll); } + +void scc_enable_acpi_mode(device_t dev, int iosf_reg, int nvs_index) +{ + struct reg_script ops[] = { + REG_SCRIPT_SET_DEV(dev), + /* Disable PCI interrupt, enable Memory and Bus Master */ + REG_PCI_OR32(PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | (1<<10)), + /* Enable ACPI mode */ + REG_IOSF_OR(IOSF_PORT_SCC, iosf_reg, + SCC_CTL_PCI_CFG_DIS | SCC_CTL_ACPI_INT_EN), + REG_SCRIPT_END + }; + struct resource *bar; + global_nvs_t *gnvs; + + /* Find ACPI NVS to update BARs */ + gnvs = (global_nvs_t *)cbmem_find(CBMEM_ID_ACPI_GNVS); + if (!gnvs) { + printk(BIOS_ERR, "Unable to locate Global NVS\n"); + return; + } + + /* Save BAR0 and BAR1 to ACPI NVS */ + bar = find_resource(dev, PCI_BASE_ADDRESS_0); + if (bar) + gnvs->dev.scc_bar0[nvs_index] = (u32)bar->base; + + bar = find_resource(dev, PCI_BASE_ADDRESS_1); + if (bar) + gnvs->dev.scc_bar1[nvs_index] = (u32)bar->base; + + /* Device is enabled in ACPI mode */ + gnvs->dev.scc_en[nvs_index] = 1; + + /* Put device in ACPI mode */ + reg_script_run(ops); +} diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c index 82833c3..97c8628 100644 --- a/src/soc/intel/baytrail/sd.c +++ b/src/soc/intel/baytrail/sd.c @@ -24,6 +24,8 @@ #include <device/pci_ids.h> #include <reg_script.h> +#include <baytrail/iosf.h> +#include <baytrail/nvs.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> #include "chip.h" @@ -46,6 +48,9 @@ static void sd_init(device_t dev) pci_write_config32(dev, CAP_OVERRIDE_HIGH, config->sdcard_cap_high | USE_CAP_OVERRIDES); } + + if (config->scc_acpi_mode) + scc_enable_acpi_mode(dev, SCC_SD_CTL, SCC_NVS_SD); } static const struct device_operations device_ops = {

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coreboot-gerrit May 2014