coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: 4cc4b04 rambi: Set panel power timings
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit 4cc4b04d8a5c5b2bdc5b0fcd34cf4ae6352b32c2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 9 14:40:05 2013 -0800 rambi: Set panel power timings These are the values that are seen with VBIOS and may need tweaked for derivative panels. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179365 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5001 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5001 for details. -gerrit

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Patch merged into coreboot/master: b40e444 baytrail: Enable panel and set timings
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit b40e444aee50c4b9768b596f0d7cf726f8d2c10f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 9 14:38:57 2013 -0800 baytrail: Enable panel and set timings These need to be set before the kernel will work without running the VBIOS option rom. Also necessary is setting the PP_CONTROL register with the EDP_FORCE_VDD bit. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179364 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5000 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5000 for details. -gerrit

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Patch merged into coreboot/master: 7b35706 rambi: change SD card pulls to 20K
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit 7b35706cf351675fc7b120a1d1d68baa9e2c717c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 09:17:18 2013 -0800 rambi: change SD card pulls to 20K Now that the SD card controller is limited to the SD card 2.0 spec it's possible to use 20K pulls for the pads. BUG=chrome-os-partner:24423 BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without any errors. Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179423 Reviewed-on: http://review.coreboot.org/4999 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4999 for details. -gerrit

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Patch merged into coreboot/master: 40b7455 rambi: limit SD card controller to 2.0 spec
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit 40b7455f9337605b0f3062a6feacb82f43099186 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 09:01:41 2013 -0800 rambi: limit SD card controller to 2.0 spec The rambi board can only meet the SD card 2.0 specification. Therefore, the controller capabilities need to be overridden to match. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows high speed as maximum timing as well as 3.3V signal voltage. Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179415 Reviewed-on: http://review.coreboot.org/4998 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/4998 for details. -gerrit

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Patch merged into coreboot/master: 8b120a8 baytrail: allow SD card controller capabilities overrides
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit 8b120a87c37c3667e8d19689500a1641fd98143e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 08:35:51 2013 -0800 baytrail: allow SD card controller capabilities overrides The SD card controller can have the capabilities it supports to be overridden. Add two optional fields to the chip structure to allow the mainboard to override the SD card controller capabilities. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. Noted capabilities override console output. Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179414 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/4997 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4997 for details. -gerrit

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Patch merged into coreboot/master: 16cc9c9 baytrail: fix nvs offsets
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit 16cc9c9599262828407146129485590d90600ad7 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 9 15:03:34 2013 -0800 baytrail: fix nvs offsets The VDAT data was off by 2 bytes when reading it from the kernel. The reason is that the header did not line up correctly with actual ACPI code. BUG=chrome-os-partner:24440 BRANCH=None TEST=crossystem devsw_cur now returns either 0 or 1 depending on state. Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a Signed-off-by: Aaron durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179372 Reviewed-on: http://review.coreboot.org/4996 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4996 for details. -gerrit

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Patch merged into coreboot/master: 7538937 rambi: export SPI write-protect GPIO correctly
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit 7538937d6e7c474dc7c17a1bc3c3591f0e6ef311 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 9 13:41:32 2013 -0600 rambi: export SPI write-protect GPIO correctly Bay Trail has 3 banks of gpios. Therefore, in order to properly identify a gpio the specific bank number as well as the GPIO within that bank is needed. The SPI write-protect GPIO is GPIO 6 within the SUS bank (offset 0x2000). BUG=chrome-os-partner:24324 BUG=chrome-os-partner:24408 BRANCH=None TEST=Built and booted. Looked at GPIO sysfs in the chromeos_acpi directory. Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179195 Reviewed-on: http://review.coreboot.org/4995 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4995 for details. -gerrit

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Patch merged into coreboot/master: f4fe3c3 baytrail: lpe audio device needs memory for its firmware
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit f4fe3c303ca5fe8124f48973eef2f798771be0fd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 9 12:52:37 2013 -0600 baytrail: lpe audio device needs memory for its firmware The LPE audio device needs 1MiB of memory for its firmware. It also has a requirement that the memory needs to be on a 512MiB boundary. Just take 1MiB @ 512MiB for the LPE device. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and analyzed console logs for resources. Also interrogated registres within the kernel. Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b Reviewed-on: https://chromium-review.googlesource.com/179192 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4994 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4994 for details. -gerrit

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Patch merged into coreboot/master: c087a9e toolchain: get rid of some bashisms
by gerrit＠coreboot.org 09 May '14

09 May '14

the following patch was just integrated into master: commit c087a9e46988f1842ec5525607fa19953f9cbbad Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu May 8 11:14:41 2014 -0500 toolchain: get rid of some bashisms On Ubuntu /bin/sh is symlinked to /bin/dash. The current toolchain.inc was doing some things that dash doesn't support. Make the shell callouts more conforming to the POSIX sh standard. Change-Id: I26b6b82b8d6158c9029e8be9e7c088ca9e207f21 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5701 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5701 for details. -gerrit

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New patch to review for coreboot: 7abed03 util: Add script to LZMA compress a file and set size in header
by Paul Menzel 08 May '14

08 May '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5705 -gerrit commit 7abed0303830ef3832ed1ec2460874f5b5990e4c Author: Kevin O'Connor <kevin(a)koconnor.net> Date: Fri May 2 16:06:26 2014 +0200 util: Add script to LZMA compress a file and set size in header Otherwise SeaBIOS does not decompress it. Change-Id: I7e3c9081c1bfbf130d0ec5f6aa221f672e29d441 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- util/lzma-with-size-in-header/lzma-with-size-in-header.sh | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/util/lzma-with-size-in-header/lzma-with-size-in-header.sh b/util/lzma-with-size-in-header/lzma-with-size-in-header.sh new file mode 100755 index 0000000..9aa0ad9 --- /dev/null +++ b/util/lzma-with-size-in-header/lzma-with-size-in-header.sh @@ -0,0 +1,9 @@ +#!/bin/sh +# Script to create an lzma file with the proper header. +FILENAME="$1" +OUTNAME="$1.lzma" + +size=`python -c "import os; print len(open(\"$FILENAME\", \"rb\").read())"` + +xz --format=lzma -zc "$FILENAME" > "$OUTNAME" +python -c "import struct; data=open(\"$OUTNAME\", 'rb').read(); data = data[:5] + struct.pack('<i', $size) + data[9:]; open(\"$OUTNAME\", 'wb').write(data)"

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coreboot-gerrit May 2014