coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 8f31abf rambi: export SPI write-protect GPIO correctly
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4995 -gerrit commit 8f31abf8861509f650d48197f1ee12040a86c4cf Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 9 13:41:32 2013 -0600 rambi: export SPI write-protect GPIO correctly Bay Trail has 3 banks of gpios. Therefore, in order to properly identify a gpio the specific bank number as well as the GPIO within that bank is needed. The SPI write-protect GPIO is GPIO 6 within the SUS bank (offset 0x2000). BUG=chrome-os-partner:24324 BUG=chrome-os-partner:24408 BRANCH=None TEST=Built and booted. Looked at GPIO sysfs in the chromeos_acpi directory. Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179195 --- src/mainboard/google/rambi/acpi/chromeos.asl | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/chromeos.asl b/src/mainboard/google/rambi/acpi/chromeos.asl index 40ffcf0..e748fb8 100644 --- a/src/mainboard/google/rambi/acpi/chromeos.asl +++ b/src/mainboard/google/rambi/acpi/chromeos.asl @@ -17,8 +17,20 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* + * Fields are in the following order. + * - Type: recovery = 1 developer mode = 2 write protect = 3 + * - Active Level - if -1 not a valid gpio + * - GPIO number encoding - if -1 not a valid gpio + * - Chipset Name + * + * Note: On Bay Trail we need to encode gpios within the 3 separate banks + * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded + * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000. + */ + Name(OIPG, Package() { - Package () { 0x0001, 0, 0xFF, "LynxPoint" }, // recovery - Package () { 0x0002, 0, 0xFF, "LynxPoint" }, // developer - Package () { 0x0003, 0, 0xFF, "LynxPoint" }, // firmware write protect + // No physical recovery button + Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" }, + Package () { 0x0003, 1, 0x2006, "BayTrail" }, })

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Patch set updated for coreboot: a1e6190 baytrail: lpe audio device needs memory for its firmware
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4994 -gerrit commit a1e6190654fc377eb3841e3d7f10bbccdb9227cd Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 9 12:52:37 2013 -0600 baytrail: lpe audio device needs memory for its firmware The LPE audio device needs 1MiB of memory for its firmware. It also has a requirement that the memory needs to be on a 512MiB boundary. Just take 1MiB @ 512MiB for the LPE device. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and analyzed console logs for resources. Also interrogated registres within the kernel. Change-Id: I4d9ad5c7b5a2f3eb627b30528d738289278b3a7b Reviewed-on: https://chromium-review.googlesource.com/179192 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/lpe.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c index c3bbff4..24daf55 100644 --- a/src/soc/intel/baytrail/lpe.c +++ b/src/soc/intel/baytrail/lpe.c @@ -30,6 +30,13 @@ #include "chip.h" +/* The LPE audio devices needs 1MiB of memory reserved aligned to a 512MiB + * address. Just take 1MiB @ 512MiB. */ +#define FIRMWARE_PHYS_BASE (512 << 20) +#define FIRMWARE_PHYS_LENGTH (1 << 20) +#define FIRMWARE_REG_BASE 0xa8 +#define FIRMWARE_REG_LENGTH 0xac + static void setup_codec_clock(device_t dev) { uint32_t reg; @@ -73,9 +80,33 @@ static void lpe_init(device_t dev) setup_codec_clock(dev); } +static void lpe_read_resources(device_t dev) +{ + pci_dev_read_resources(dev); + + reserved_ram_resource(dev, FIRMWARE_REG_BASE, + FIRMWARE_PHYS_BASE >> 10, + FIRMWARE_PHYS_LENGTH >> 10); +} + +static void lpe_set_resources(device_t dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + res = find_resource(dev, FIRMWARE_REG_BASE); + if (res == NULL) { + printk(BIOS_DEBUG, "LPE Firmware memory not found.\n"); + return; + } + pci_write_config32(dev, FIRMWARE_REG_BASE, res->base); + pci_write_config32(dev, FIRMWARE_REG_LENGTH, res->size); +} + static const struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, + .read_resources = lpe_read_resources, + .set_resources = lpe_set_resources, .enable_resources = pci_dev_enable_resources, .init = lpe_init, .enable = NULL,

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Patch set updated for coreboot: 8ed18f1 baytrail: allow SD card controller capabilities overrides
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4997 -gerrit commit 8ed18f1f5bf9bbb81cc58960db6cf54a68be4222 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 08:35:51 2013 -0800 baytrail: allow SD card controller capabilities overrides The SD card controller can have the capabilities it supports to be overridden. Add two optional fields to the chip structure to allow the mainboard to override the SD card controller capabilities. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. Noted capabilities override console output. Change-Id: Ibfef8f765b35eeec6da969dd05f5484f8672a7b9 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179414 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/chip.h | 4 +++ src/soc/intel/baytrail/sd.c | 65 +++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 6485cc0..48fb4b4 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -43,6 +43,7 @@ ramstage-y += scc.c ramstage-y += emmc.c ramstage-y += lpss.c ramstage-y += pcie.c +ramstage-y += sd.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 250f644..43a3efb 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -51,6 +51,10 @@ struct soc_intel_baytrail_config { /* LPE Audio Clock configuration. */ int lpe_codec_clk_freq; /* 19 or 25 are valid. */ int lpe_codec_clk_num; /* Platform clock pins. [0:5] are valid. */ + + /* Native SD Card controller - override controller capabilities. */ + uint32_t sdcard_cap_low; + uint32_t sdcard_cap_high; }; extern struct chip_operations soc_intel_baytrail_ops; diff --git a/src/soc/intel/baytrail/sd.c b/src/soc/intel/baytrail/sd.c new file mode 100644 index 0000000..82833c3 --- /dev/null +++ b/src/soc/intel/baytrail/sd.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <reg_script.h> + +#include <baytrail/pci_devs.h> +#include <baytrail/ramstage.h> +#include "chip.h" + +#define CAP_OVERRIDE_LOW 0xa0 +#define CAP_OVERRIDE_HIGH 0xa4 +# define USE_CAP_OVERRIDES (1 << 31) + +static void sd_init(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + + if (config == NULL) + return; + + if (config->sdcard_cap_low != 0 || config->sdcard_cap_high != 0) { + printk(BIOS_DEBUG, "Overriding SD Card controller caps.\n"); + pci_write_config32(dev, CAP_OVERRIDE_LOW, + config->sdcard_cap_low); + pci_write_config32(dev, CAP_OVERRIDE_HIGH, + config->sdcard_cap_high | USE_CAP_OVERRIDES); + } +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = sd_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = SD_DEVID, +};

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Patch set updated for coreboot: 575a196 baytrail: fix nvs offsets
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4996 -gerrit commit 575a196a424abe80cbc7e1c382e3e9faff80719f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Dec 9 15:03:34 2013 -0800 baytrail: fix nvs offsets The VDAT data was off by 2 bytes when reading it from the kernel. The reason is that the header did not line up correctly with actual ACPI code. BUG=chrome-os-partner:24440 BRANCH=None TEST=crossystem devsw_cur now returns either 0 or 1 depending on state. Change-Id: Ie78599f29cd5daf7da98db5e37fa276d24339f6a Signed-off-by: Aaron durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179372 --- src/soc/intel/baytrail/baytrail/nvs.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index aed0974..97b5fc5 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -50,12 +50,12 @@ typedef struct { u32 cmem; /* 0x30 - CBMEM TOC */ u32 tolm; /* 0x34 - Top of Low Memory */ u32 cbmc; /* 0x38 - coreboot memconsole */ - u8 rsvd5[39]; + u8 rsvd5[36]; /* Serial IO device BARs */ u32 s0b[8]; /* 0x60 - 0x7f - BAR0 */ u32 s1b[8]; /* 0x80 - 0x9f - BAR1 */ - u8 rsvd6[95]; + u8 rsvd6[96]; /* ChromeOS specific (starts at 0x100)*/ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: c3488a2 rambi: change SD card pulls to 20K
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4999 -gerrit commit c3488a2496f090ed67eaa192a5261bc4347c365d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 09:17:18 2013 -0800 rambi: change SD card pulls to 20K Now that the SD card controller is limited to the SD card 2.0 spec it's possible to use 20K pulls for the pads. BUG=chrome-os-partner:24423 BUG=chrome-os-partner:24312 BRANCH=None TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without any errors. Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179423 --- src/mainboard/google/rambi/gpio.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index a93da53..6e6efe6 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -90,13 +90,13 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC030 - NC */ GPIO_NC, /* S0-SC031 - NC */ GPIO_NC, /* S0-SC032 - NC */ - GPIO_FUNC(1, PULL_DOWN, 2K), /* S0-SC033 - SD3_CLK */ - GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC034 - SD3_D0 */ - GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC035 - SD3_D1 */ - GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC036 - SD3_D2 */ - GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC037 - SD3_D3 */ + GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */ - GPIO_FUNC(1, PULL_UP, 2K), /* S0-SC039 - SD3_CMD */ + GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */ GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */ GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */

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Patch set updated for coreboot: a424fe4 rambi: limit SD card controller to 2.0 spec
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4998 -gerrit commit a424fe48b75f6577169381d00cdd6ed7c1fd02b8 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Dec 10 09:01:41 2013 -0800 rambi: limit SD card controller to 2.0 spec The rambi board can only meet the SD card 2.0 specification. Therefore, the controller capabilities need to be overridden to match. BUG=chrome-os-partner:24423 BRANCH=None TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows high speed as maximum timing as well as 3.3V signal voltage. Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179415 --- src/mainboard/google/rambi/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 1c24d57..96772ac 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -27,6 +27,10 @@ chip soc/intel/baytrail register "lpe_codec_clk_freq" = "25" # 25MHz clock register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0] + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + device cpu_cluster 0 on device lapic 0 on end end

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Patch set updated for coreboot: 7428806 rambi: Set panel power timings
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5001 -gerrit commit 74288063d0692aa25b3b68e08cc806fe17a55e9e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 9 14:40:05 2013 -0800 rambi: Set panel power timings These are the values that are seen with VBIOS and may need tweaked for derivative panels. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179365 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index 96772ac..bd54f00 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -31,6 +31,16 @@ chip soc/intel/baytrail register "sdcard_cap_low" = "0x036864b2" register "sdcard_cap_high" = "0x0" + # Enable PIPEA as DP_C + register "gpu_pipea_hotplug" = "6" # 6ms Pulse + register "gpu_pipea_port_select" = "2" # DP_C + register "gpu_pipea_power_cycle_delay" = "5" # 400ms + register "gpu_pipea_power_on_delay" = "2000" # 200ms + register "gpu_pipea_light_on_delay" = "10" # 1ms + register "gpu_pipea_power_off_delay" = "500" # 50ms + register "gpu_pipea_light_off_delay" = "2000" # 200ms + register "gpu_pipea_backlight_pwm" = "0x400" + device cpu_cluster 0 on device lapic 0 on end end

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Patch set updated for coreboot: 266b7ce baytrail: Enable panel and set timings
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5000 -gerrit commit 266b7ce01bcc88eae4afd3a5e8283623551adab0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Dec 9 14:38:57 2013 -0800 baytrail: Enable panel and set timings These need to be set before the kernel will work without running the VBIOS option rom. Also necessary is setting the PP_CONTROL register with the EDP_FORCE_VDD bit. BUG=chrome-os-partner:24367 BRANCH=none TEST=boot on rambi in normal mode and see the panel come up Change-Id: I495f818d581d08b80db11785fe28b601ec956b3b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179364 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/gfx.h | 16 ++++++++ src/soc/intel/baytrail/chip.h | 25 ++++++++++++ src/soc/intel/baytrail/gfx.c | 75 +++++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/gfx.h b/src/soc/intel/baytrail/baytrail/gfx.h index 655615d..7047dd5 100644 --- a/src/soc/intel/baytrail/baytrail/gfx.h +++ b/src/soc/intel/baytrail/baytrail/gfx.h @@ -45,4 +45,20 @@ #define APERTURE_SIZE_256MB (1 << 1) #define APERTURE_SIZE_512MB (3 << 1) +#define VLV_DISPLAY_BASE 0x180000 +#define PIPEA_REG(reg) (VLV_DISPLAY_BASE + (reg)) +#define PIPEB_REG(reg) (VLV_DISPLAY_BASE + 0x100 + (reg)) + +/* Panel control registers */ +#define HOTPLUG_CTRL 0x61110 +#define PP_CONTROL 0x61204 +#define PP_CONTROL_UNLOCK 0xabcd0000 +#define PP_CONTROL_EDP_FORCE_VDD (1 << 3) +#define PP_ON_DELAYS 0x61208 +#define PP_OFF_DELAYS 0x6120c +#define PP_DIVISOR 0x61210 +#define BACKLIGHT_CTL2 0x61250 +#define BACKLIGHT_ENABLE (1 << 31) +#define BACKLIGHT_CTL 0x61254 + #endif /* _BAYTRAIL_GFX_H_ */ diff --git a/src/soc/intel/baytrail/chip.h b/src/soc/intel/baytrail/chip.h index 43a3efb..2cc3fd6 100644 --- a/src/soc/intel/baytrail/chip.h +++ b/src/soc/intel/baytrail/chip.h @@ -55,6 +55,31 @@ struct soc_intel_baytrail_config { /* Native SD Card controller - override controller capabilities. */ uint32_t sdcard_cap_low; uint32_t sdcard_cap_high; + + /* + * Digital Port Hotplug Enable: + * 0x04 = Enabled, 2ms short pulse + * 0x05 = Enabled, 4.5ms short pulse + * 0x06 = Enabled, 6ms short pulse + * 0x07 = Enabled, 100ms short pulse + */ + int gpu_pipea_hotplug; + int gpu_pipea_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipea_power_on_delay; + uint16_t gpu_pipea_light_on_delay; + uint16_t gpu_pipea_power_off_delay; + uint16_t gpu_pipea_light_off_delay; + uint16_t gpu_pipea_power_cycle_delay; + uint32_t gpu_pipea_backlight_pwm; + + int gpu_pipeb_hotplug; + int gpu_pipeb_port_select; /* Port select: 1=DP_B 2=DP_C */ + uint16_t gpu_pipeb_power_on_delay; + uint16_t gpu_pipeb_light_on_delay; + uint16_t gpu_pipeb_power_off_delay; + uint16_t gpu_pipeb_light_off_delay; + uint16_t gpu_pipeb_power_cycle_delay; + uint32_t gpu_pipeb_backlight_pwm; }; extern struct chip_operations soc_intel_baytrail_ops; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 28b73d5..d2a8ba5 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -30,6 +30,8 @@ #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> +#include "chip.h" + #define GFX_TIMEOUT 100000 /* 100ms */ /* @@ -288,6 +290,77 @@ static void gfx_post_vbios_init(device_t dev) gfx_run_script(dev, gfx_post_vbios_script); } +static void gfx_panel_setup(device_t dev) +{ + struct soc_intel_baytrail_config *config = dev->chip_info; + struct reg_script gfx_pipea_init[] = { + REG_SCRIPT_SET_DEV(dev), + /* CONTROL */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + /* HOTPLUG */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(HOTPLUG_CTRL), + 0x1 | (config->gpu_pipea_hotplug << 2)), + /* POWER ON */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_ON_DELAYS), + (config->gpu_pipea_port_select << 30 | + config->gpu_pipea_power_on_delay << 16 | + config->gpu_pipea_light_on_delay)), + /* POWER OFF */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_OFF_DELAYS), + (config->gpu_pipea_power_off_delay << 16 | + config->gpu_pipea_light_off_delay)), + /* DIVISOR */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEA_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipea_power_cycle_delay), + /* BACKLIGHT */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL), + (config->gpu_pipea_backlight_pwm << 16) | + (config->gpu_pipea_backlight_pwm >> 1)), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEA_REG(BACKLIGHT_CTL2), + BACKLIGHT_ENABLE), + REG_SCRIPT_END + }; + struct reg_script gfx_pipeb_init[] = { + REG_SCRIPT_SET_DEV(dev), + /* CONTROL */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_CONTROL), + PP_CONTROL_UNLOCK | PP_CONTROL_EDP_FORCE_VDD), + /* HOTPLUG */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(HOTPLUG_CTRL), + 0x1 | (config->gpu_pipeb_hotplug << 2)), + /* POWER ON */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_ON_DELAYS), + (config->gpu_pipeb_port_select << 30 | + config->gpu_pipeb_power_on_delay << 16 | + config->gpu_pipeb_light_on_delay)), + /* POWER OFF */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_OFF_DELAYS), + (config->gpu_pipeb_power_off_delay << 16 | + config->gpu_pipeb_light_off_delay)), + /* DIVISOR */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, PIPEB_REG(PP_DIVISOR), + ~0x1f, config->gpu_pipeb_power_cycle_delay), + /* BACKLIGHT */ + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL), + (config->gpu_pipeb_backlight_pwm << 16) | + (config->gpu_pipeb_backlight_pwm >> 1)), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, PIPEB_REG(BACKLIGHT_CTL2), + BACKLIGHT_ENABLE), + REG_SCRIPT_END + }; + + if (config->gpu_pipea_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEA\n"); + reg_script_run(gfx_pipea_init); + } + + if (config->gpu_pipeb_port_select) { + printk(BIOS_INFO, "GFX: Initialize PIPEB\n"); + reg_script_run(gfx_pipeb_init); + } +} + static void gfx_init(device_t dev) { /* Pre VBIOS Init */ @@ -296,6 +369,8 @@ static void gfx_init(device_t dev) /* Power Management Init */ gfx_pm_init(dev); + gfx_panel_setup(dev); + /* Run VBIOS */ pci_dev_init(dev);

1 0

Patch set updated for coreboot: 4649891 rambi: Enable DPTF
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5003 -gerrit commit 4649891d1522f71b416ba87c03288b1e7fec0ac7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 10 07:48:00 2013 -0800 rambi: Enable DPTF This enables the DPTF framework, but it doesn't do much without some sort of kernel+user components to drive it. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179480 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/acpi/dptf.asl | 28 +++++++++++++++++++++++++ src/mainboard/google/rambi/acpi_tables.c | 8 ++++++++ src/mainboard/google/rambi/dsdt.asl | 3 +++ src/mainboard/google/rambi/thermal.h | 35 +++++--------------------------- 4 files changed, 44 insertions(+), 30 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl new file mode 100644 index 0000000..0d5cd65 --- /dev/null +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -0,0 +1,28 @@ +#define DPTF_TSR0_SENSOR_ID 1 +#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" + +#define DPTF_TSR1_SENSOR_ID 2 +#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" + +#define DPTF_TSR2_SENSOR_ID 3 +#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0}, + + /* CPU and Charger Effect on Temp Sensor 0 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 80, 300, 0, 0, 0, 0 }, + + /* CPU and Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 80, 300, 0, 0, 0, 0 }, + + /* CPU and Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 }, + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 80, 300, 0, 0, 0, 0 }, +}) + +/* Include Baytrail DPTF */ +#include <soc/intel/baytrail/acpi/dptf/dptf.asl> diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index a4754f1..1d96dec 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -36,6 +36,8 @@ #include <baytrail/nvs.h> #include <baytrail/iomap.h> +#include "thermal.h" + extern const unsigned char AmlCode[]; static void acpi_create_gnvs(global_nvs_t *gnvs) @@ -59,6 +61,12 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* TPM Present */ gnvs->tpmp = 1; + /* Enable DPTF */ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; + gnvs->tact = ACTIVE_TEMPERATURE; + gnvs->dpte = 1; + #if CONFIG_CHROMEOS chromeos_init_vboot(&(gnvs->chromeos)); gnvs->chromeos.vbt2 = google_ec_running_ro() ? diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 1fbb8eb..53f2922 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -46,6 +46,9 @@ DefinitionBlock( //#include <soc/intel/baytrail/acpi/northcluster.asl> #include <soc/intel/baytrail/acpi/southcluster.asl> } + + /* Dynamic Platform Thermal Framework */ + #include "acpi/dptf.asl" } #include "acpi/chromeos.asl" diff --git a/src/mainboard/google/rambi/thermal.h b/src/mainboard/google/rambi/thermal.h index f771014..2432b8d 100644 --- a/src/mainboard/google/rambi/thermal.h +++ b/src/mainboard/google/rambi/thermal.h @@ -20,38 +20,13 @@ #ifndef BAYLEYBAY_THERMAL_H #define BAYLEYBAY_THERMAL_H -/* Fan is OFF */ -#define FAN4_THRESHOLD_OFF 0 -#define FAN4_THRESHOLD_ON 0 -#define FAN4_PWM 0x00 - -/* Fan is at LOW speed */ -#define FAN3_THRESHOLD_OFF 48 -#define FAN3_THRESHOLD_ON 55 -#define FAN3_PWM 0x40 - -/* Fan is at MEDIUM speed */ -#define FAN2_THRESHOLD_OFF 52 -#define FAN2_THRESHOLD_ON 64 -#define FAN2_PWM 0x80 - -/* Fan is at HIGH speed */ -#define FAN1_THRESHOLD_OFF 60 -#define FAN1_THRESHOLD_ON 68 -#define FAN1_PWM 0xb0 - -/* Fan is at FULL speed */ -#define FAN0_THRESHOLD_OFF 66 -#define FAN0_THRESHOLD_ON 78 -#define FAN0_PWM 0xff - /* Temperature which OS will shutdown at */ -#define CRITICAL_TEMPERATURE 100 +#define CRITICAL_TEMPERATURE 95 -/* Temperature which OS will throttle CPU */ -#define PASSIVE_TEMPERATURE 90 +/* Passive cooling policy threshold */ +#define PASSIVE_TEMPERATURE 0 -/* Tj_max value for calculating PECI CPU temperature */ -#define MAX_TEMPERATURE 100 +/* Temperature which OS will throttle CPU (when using a Fan) */ +#define ACTIVE_TEMPERATURE 80 #endif

1 0

Patch set updated for coreboot: fb03ef5 baytrail: Basic DPTF framework
by Aaron Durbin 08 May '14

08 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5002 -gerrit commit fb03ef58983422456c849d2377ae98e1e7e0c15a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Dec 10 07:41:33 2013 -0800 baytrail: Basic DPTF framework This is not complete yet but it compiles and doesn't cause any issues by itself. It is tied into the EC pretty closely so that is part of the same commit. Once we have more of the EC support done it will need some more work to make use of those new interfaces properly. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF Change-Id: I4b27e38baae18627a275488d77944208950b98bd Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179459 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/ec/google/chromeec/acpi/ec.asl | 71 +++++++++++ src/soc/intel/baytrail/acpi.c | 4 +- src/soc/intel/baytrail/acpi/dptf/charger.asl | 36 ++++++ src/soc/intel/baytrail/acpi/dptf/cpu.asl | 180 +++++++++++++++++++++++++++ src/soc/intel/baytrail/acpi/dptf/dptf.asl | 51 ++++++++ src/soc/intel/baytrail/acpi/dptf/thermal.asl | 116 +++++++++++++++++ src/soc/intel/baytrail/acpi/globalnvs.asl | 5 + src/soc/intel/baytrail/baytrail/nvs.h | 9 +- 8 files changed, 468 insertions(+), 4 deletions(-) diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl index 31ef905..d0540ed 100644 --- a/src/ec/google/chromeec/acpi/ec.asl +++ b/src/ec/google/chromeec/acpi/ec.asl @@ -25,6 +25,7 @@ // Mainboard specific throttle handler External (\_TZ.THRT, MethodObj) +External (\_SB.DPTF.TEVT, MethodObj) Device (EC0) { @@ -47,6 +48,7 @@ Device (EC0) TSTB, 8, // Test Byte TSTC, 8, // Complement of Test Byte KBLV, 8, // Keyboard Backlight + FAND, 8, // Set Fan Duty Cycle } OperationRegion (EMEM, SystemIO, EC_LPC_ADDR_MEMMAP, EC_MEMMAP_SIZE) @@ -89,6 +91,8 @@ Device (EC0) BMOD, 64, // Battery Model String BSER, 64, // Battery Serial String BTYP, 64, // Battery Type String + Offset (0x80), + ALS0, 16, // ALS reading 0 in lux } Method (TINS, 1, Serialized) @@ -134,6 +138,40 @@ Device (EC0) Store (LIDS, \LIDS) } + /* Read requested temperature and check against EC error values */ + Method (TSRD, 1, Serialized) + { + Store (\_SB.PCI0.LPCB.EC0.TINS (Arg0), Local0) + + /* Check for sensor not calibrated */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNCA)) { + Return (Zero) + } + + /* Check for sensor not present */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNPR)) { + Return (Zero) + } + + /* Check for sensor not powered */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TNOP)) { + Return (Zero) + } + + /* Check for sensor bad reading */ + If (LEqual (Local0, \_SB.PCI0.LPCB.EC0.TBAD)) { + Return (Zero) + } + + /* Adjust by offset to get Kelvin */ + Add (\_SB.PCI0.LPCB.EC0.TOFS, Local0, Local0) + + /* Convert to 1/10 Kelvin */ + Multiply (Local0, 10, Local0) + + Return (Local0) + } + // Lid Closed Event Method (_Q01, 0, NotSerialized) { @@ -247,6 +285,39 @@ Device (EC0) } } + /* + * Dynamic Platform Thermal Framework support + */ + + /* + * Set Aux Trip Point 0 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT0, 2, Serialized) + { + } + + /* + * Set Aux Trip Point 1 + * Arg0 = Temp Sensor ID + * Arg1 = Value to set + */ + Method (PAT1, 2, Serialized) + { + } + + /* + * DPTF Thermal Threshold Event + */ + Method (_Q14, 0, Serialized) + { + Store ("EC: DPTF THERMAL THRESHOLD", Debug) + If (CondRefOf (\_SB.DPTF.TEVT, Local0)) { + \_SB.DPTF.TEVT () + } + } + #include "ac.asl" #include "battery.asl" } diff --git a/src/soc/intel/baytrail/acpi.c b/src/soc/intel/baytrail/acpi.c index fff63e1..89ab929 100644 --- a/src/soc/intel/baytrail/acpi.c +++ b/src/soc/intel/baytrail/acpi.c @@ -338,8 +338,8 @@ static int generate_P_state_entries(int core, int cores_per_package) /* Write _PCT indicating use of FFixedHW */ len = acpigen_write_empty_PCT(); - /* Write _PPC with no limit on supported P-state */ - len += acpigen_write_PPC(0); + /* Write _PPC with NVS specified limit on supported P-state */ + len += acpigen_write_PPC_NVS(); /* Write PSD indicating configured coordination type */ len += acpigen_write_PSD_package(core, 1, coord_type); diff --git a/src/soc/intel/baytrail/acpi/dptf/charger.asl b/src/soc/intel/baytrail/acpi/dptf/charger.asl new file mode 100644 index 0000000..7560f13 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/charger.asl @@ -0,0 +1,36 @@ +Device (TCHG) +{ + Name (_HID, "INT3403") + Name (_UID, 0) + Name (PTYP, 0x0B) + Name (_STR, Unicode("Battery Charger")) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Name (PPSS, Package () + { + Package () { 0, 0, 0, 0, 0, 0x880, "mA", 0 }, /* 2.1A */ + Package () { 0, 0, 0, 0, 1, 0x800, "mA", 0 }, /* 2.0A */ + Package () { 0, 0, 0, 0, 2, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 3, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 4, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 5, 0x000, "mA", 0 }, /* 0.0A */ + }) + + Method (PPPC) + { + Return (0) + } + + Method (SPPC, 1, Serialized) + { + /* TODO: Tell EC to limit battery charging */ + } +} diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl new file mode 100644 index 0000000..6e6c792 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -0,0 +1,180 @@ +External (\_PR.CPU0._TSS, MethodObj) +External (\_PR.CPU0._TPC, MethodObj) +External (\_PR.CPU0._PTC, PkgObj) +External (\_PR.CPU0._TSD, PkgObj) +External (\_PR.CPU0._PPC, MethodObj) +External (\_PR.CPU0._PSS, MethodObj) + +Device (TCPU) +{ + Name (_HID, EISAID ("INT3401")) + Name (_UID, 0) + Name (CTYP, 0) /* Passive Cooling by default */ + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* + * Processor Throttling Controls + */ + + Method (_TSS) + { + If (CondRefOf (\_PR.CPU0._TSS)) { + Return (\_PR.CPU0._TSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0 } + }) + } + } + + Method (_TPC) + { + If (CondRefOf (\_PR.CPU0._TPC)) { + Return (\_PR.CPU0._TPC) + } Else { + Return (0) + } + } + + Method (_PTC) + { + If (CondRefOf (\_PR.CPU0._PTC)) { + Return (\_PR.CPU0._PTC) + } Else { + Return (Package () + { + Buffer () { 0 }, + Buffer () { 0 } + }) + } + } + + Method (_TSD) + { + If (CondRefOf (\_PR.CPU0._TSD)) { + Return (\_PR.CPU0._TSD) + } Else { + Return (Package () + { + Package () { 5, 0, 0, 0, 0 } + }) + } + } + + Method (_TDL) + { + If (CondRefOf (\_PR.CPU0._TSS)) { + Store (SizeOf (\_PR.CPU0._TSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * Processor Performance Control + */ + + Method (_PPC) + { + If (CondRefOf (\_PR.CPU0._PPC)) { + Return (\_PR.CPU0._PPC) + } Else { + Return (0) + } + } + + Method (SPPC, 1) + { + Store (Arg0, \PPCM) + + /* Notify OS to re-read _PPC limit on each CPU */ + \PPCN () + } + + Method (_PSS) + { + If (CondRefOf (\_PR.CPU0._PSS)) { + Return (\_PR.CPU0._PSS) + } Else { + Return (Package () + { + Package () { 0, 0, 0, 0, 0, 0 } + }) + } + } + + Method (_PDL) + { + If (CondRefOf (\_PR.CPU0._PSS)) { + Store (SizeOf (\_PR.CPU0._PSS ()), Local0) + Decrement (Local0) + Return (Local0) + } Else { + Return (0) + } + } + + /* + * DPTF + */ + + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) + } + + /* Critical temperature from NVS */ + Method (_CRT, 0, Serialized) + { + Return (CTOK (\TCRT)) + } + + /* Hot temperature is 3 less than critical temperature */ + Method (_HOT, 0, Serialized) + { + Return (CTOK (Subtract (\TCRT, 3))) + } + + Method (_PSV, 0, Serialized) + { + If (CTYP) { + Return (CTOK (\TACT)) + } Else { + Return (CTOK (\TPSV)) + } + } + + /* Set Cooling Policy + * Arg0 - Cooling policy mode, 1=active, 0=passive + * Arg1 - Acoustic Limit + * Arg2 - Power Limit + */ + Method (_SCP, 3, Serialized) + { + If (LEqual (Arg0, 0)) { + Store (0, CTYP) + } Else { + Store (1, CTYP) + } + + /* DPTF Thermal Trip Points Changed Event */ + Notify (TCPU, 0x91) + } +} diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl new file mode 100644 index 0000000..b636886 --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl @@ -0,0 +1,51 @@ +Device (DPTF) +{ + Name (_HID, EISAID ("INT3400")) + Name (_UID, 0) + + Name (IDSP, Package() + { + /* DPPM Passive Policy 1.0 */ + ToUUID("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), + + /* DPPM Critical Policy */ + ToUUID("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), + + /* DPPM Cooling Policy */ + ToUUID("16CAF1B7-DD38-40ED-B1C1-1B8A1913D531"), + }) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_OSC, 4, Serialized) + { + /* TODO: Enable/Disable EC control of thermals/charging */ + Return (Arg3) + } + + Method (_TRT) + { + Return (\_SB.DTRT) + } + + /* Thermal Threshold Event Handler */ + Method (TEVT, 0, Serialized) + { + } + + /* Include CPU Participant */ + #include "cpu.asl" + + /* Include Thermal Participants */ + #include "thermal.asl" + + /* Include Charger Participant */ + #include "charger.asl" +} diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl new file mode 100644 index 0000000..2a77e6a --- /dev/null +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -0,0 +1,116 @@ +#ifdef DPTF_TSR0_SENSOR_ID +Device (TSR0) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 1) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR0_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } +} +#endif + +#ifdef DPTF_TSR1_SENSOR_ID +Device (TSR1) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 2) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR1_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } +} +#endif + +#ifdef DPTF_TSR2_SENSOR_ID +Device (TSR2) +{ + Name (_HID, EISAID ("INT3403")) + Name (_UID, 3) + Name (PTYP, 0x03) + Name (TMPI, DPTF_TSR2_SENSOR_ID) + Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + + Method (_STA) + { + If (LEqual (\DPTE, One)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + Method (_TMP, 0, Serialized) + { + Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) + } + + Name (PATC, 2) + + /* Set Aux Trip Point */ + Method (PAT0, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT0 (TMPI, Arg0) + } + + /* Set Aux Trip Point */ + Method (PAT1, 1, Serialized) + { + \_SB.PCI0.LPCB.EC0.PAT1 (TMPI, Arg0) + } +} +#endif diff --git a/src/soc/intel/baytrail/acpi/globalnvs.asl b/src/soc/intel/baytrail/acpi/globalnvs.asl index 2f614a9..cd00824 100644 --- a/src/soc/intel/baytrail/acpi/globalnvs.asl +++ b/src/soc/intel/baytrail/acpi/globalnvs.asl @@ -51,6 +51,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) PCNT, 8, // 0x11 - Processor count TPMP, 8, // 0x12 - TPM Present and Enabled TLVL, 8, // 0x13 - Throttle Level + PPCM, 8, // 0x14 - Maximum P-state usable by OS /* Device Config */ Offset (0x20), @@ -58,6 +59,10 @@ Field (GNVS, ByteAcc, NoLock, Preserve) S5U1, 8, // 0x21 - Enable USB1 in S5 S3U0, 8, // 0x22 - Enable USB0 in S3 S3U1, 8, // 0x23 - Enable USB1 in S3 + TACT, 8, // 0x24 - Thermal Active trip point + TPSV, 8, // 0x25 - Thermal Passive trip point + TCRT, 8, // 0x26 - Thermal Critical trip point + DPTE, 8, // 0x27 - Enable DPTF /* Base addresses */ Offset (0x30), diff --git a/src/soc/intel/baytrail/baytrail/nvs.h b/src/soc/intel/baytrail/baytrail/nvs.h index 97b5fc5..8243ef3 100644 --- a/src/soc/intel/baytrail/baytrail/nvs.h +++ b/src/soc/intel/baytrail/baytrail/nvs.h @@ -37,14 +37,19 @@ typedef struct { u8 pcnt; /* 0x11 - Processor Count */ u8 tpmp; /* 0x12 - TPM Present and Enabled */ u8 tlvl; /* 0x13 - Throttle Level */ - u8 rsvd1[12]; + u8 ppcm; /* 0x14 - Maximum P-state usable by OS */ + u8 rsvd1[11]; /* Device Config */ u8 s5u0; /* 0x20 - Enable USB0 in S5 */ u8 s5u1; /* 0x21 - Enable USB1 in S5 */ u8 s3u0; /* 0x22 - Enable USB0 in S3 */ u8 s3u1; /* 0x23 - Enable USB1 in S3 */ - u8 rsvd2[12]; + u8 tact; /* 0x24 - Thermal Active trip point */ + u8 tpsv; /* 0x25 - Thermal Passive trip point */ + u8 tcrt; /* 0x26 - Thermal Critical trip point */ + u8 dpte; /* 0x27 - Enable DPTF */ + u8 rsvd2[8]; /* Base Addresses */ u32 cmem; /* 0x30 - CBMEM TOC */

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coreboot-gerrit May 2014