coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch merged into coreboot/master: dd2e8c3 superio/fintek/f71869ad: Configure multi-func reg in devicetree
by gerrit＠coreboot.org 08 May '14

08 May '14

the following patch was just integrated into master: commit dd2e8c35fb368316b51d969d046696a017f09d25 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 24 02:58:11 2014 +1000 superio/fintek/f71869ad: Configure multi-func reg in devicetree Facilitate for the configuration of so called "Multi-function Select Registers" with devicetree.cb in ramstage. Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI mode. This allows the Fintek to correctly talk to the Southbridge over the SMBus for CPU temperature data as to control fans and so on. Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5576 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/5576 for details. -gerrit

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Patch merged into coreboot/master: 708be1a mainboard/jetway/nf81-t56n-lf: Improve diags in romstage
by gerrit＠coreboot.org 08 May '14

08 May '14

the following patch was just integrated into master: commit 708be1a45356b33eaf5f287e529a99fb856736af Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 6 12:34:56 2014 +1000 mainboard/jetway/nf81-t56n-lf: Improve diags in romstage romstage reports a completely unintelligible printf of "error level:", fix this and document meaning of the return values in source. Change-Id: Ia2fb9a6206e08822f6c2f62b69bf22cdae2ba819 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5465 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5465 for details. -gerrit

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New patch to review for coreboot: 566381c superio/fintek/f71869ad: Fix incorrect LDN's
by Edward O'Callaghan 08 May '14

08 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5696 -gerrit commit 566381cd1148755e3b7f24fb99c21113d39f4c82 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 8 19:50:55 2014 +1000 superio/fintek/f71869ad: Fix incorrect LDN's Turns out there are a few minor differences of the LDN's in the AD rev. of this Fintek chip. 0x07 is in fact the WDT so renaming and remove the now incorrect io mask. Add missing CIR LDN functionality and touch up src inline doc. Change-Id: I440aebad71d62d199d3283dd061933e76b21dda5 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/fintek/f71869ad/f71869ad.h | 3 ++- src/superio/fintek/f71869ad/superio.c | 8 +++++--- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/src/superio/fintek/f71869ad/f71869ad.h b/src/superio/fintek/f71869ad/f71869ad.h index 3aeac56..c6e8ead 100644 --- a/src/superio/fintek/f71869ad/f71869ad.h +++ b/src/superio/fintek/f71869ad/f71869ad.h @@ -29,7 +29,8 @@ #define F71869AD_HWM 0x04 /* Hardware monitor */ #define F71869AD_KBC 0x05 /* PS/2 keyboard and mouse */ #define F71869AD_GPIO 0x06 /* General Purpose I/O (GPIO) */ -#define F71869AD_BSEL 0x07 /* BSEL */ +#define F71869AD_WDT 0x07 /* WDT */ +#define F71869AD_CIR 0x08 /* CIR */ #define F71869AD_PME 0x0a /* Power Management Events (PME) and ACPI */ #endif /* SUPERIO_FINTEK_F71869AD_H */ diff --git a/src/superio/fintek/f71869ad/superio.c b/src/superio/fintek/f71869ad/superio.c index 11ad6f8..1c10abd 100644 --- a/src/superio/fintek/f71869ad/superio.c +++ b/src/superio/fintek/f71869ad/superio.c @@ -99,8 +99,9 @@ static struct device_operations ops = { * irq 0x72 = 12 # Mouse IRQ * end * device pnp 4e.06 off end # GPIO - * device pnp 4e.07 on end # BSEL - * device pnp 4e.0a off end # PME + * device pnp 4e.07 on end # WDT + * device pnp 4e.08 off end # CIR + * device pnp 4e.0a on end # PME * end # f71869ad * */ @@ -112,7 +113,8 @@ static struct pnp_info pnp_dev_info[] = { { &ops, F71869AD_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, F71869AD_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71869AD_GPIO, }, - { &ops, F71869AD_BSEL, PNP_IO0, {0x07f8, 0}, }, + { &ops, F71869AD_WDT, }, + { &ops, F71869AD_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71869AD_PME, }, };

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Patch set updated for coreboot: c2d509f superio/ite/it8728f: RAMstage PNP configuration component
by Edward O'Callaghan 08 May '14

08 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5668 -gerrit commit c2d509ff6ef015998cca65c0b78c5b520761709e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 18:00:07 2014 +1000 superio/ite/it8728f: RAMstage PNP configuration component Provide devicetree.cb RAMstage configuration of this superio component. Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/ite/it8728f/Makefile.inc | 2 + src/superio/ite/it8728f/chip.h | 34 +++++++++++++ src/superio/ite/it8728f/it8728f_hwm.c | 80 ++++++++++++++++++++++++++++++ src/superio/ite/it8728f/it8728f_internal.h | 28 +++++++++++ src/superio/ite/it8728f/superio.c | 69 ++++++++++++++++++++++++++ 5 files changed, 213 insertions(+) diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc index d8d4f6a..a146db8 100644 --- a/src/superio/ite/it8728f/Makefile.inc +++ b/src/superio/ite/it8728f/Makefile.inc @@ -19,3 +19,5 @@ ## romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += it8728f_hwm.c +ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c diff --git a/src/superio/ite/it8728f/chip.h b/src/superio/ite/it8728f/chip.h new file mode 100644 index 0000000..998685f --- /dev/null +++ b/src/superio/ite/it8728f/chip.h @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_CHIP_H +#define SUPERIO_ITE_IT8728F_CHIP_H + +struct superio_ite_it8728f_config { + /* HWM configuration registers */ + uint8_t hhwm_ctl_register; + uint8_t hhwm_main_ctl_register; + uint8_t hhwm_adc_temp_chan_en_reg; + uint8_t hhwm_fan1_ctl_pwm; + uint8_t hhwm_fan2_ctl_pwm; + uint8_t hhwm_fan3_ctl_pwm; +}; + +#endif /* SUPERIO_ITE_IT8728F_CHIP_H */ diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c new file mode 100644 index 0000000..01eae2a --- /dev/null +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pnp.h> +#include "chip.h" +#include "ite_internal.h" + +/* + * FAN controller configuration register index's + */ +#define HWM_MAIN_CTL_REG 0x13 /* default 0x07 */ +#define HWM_CTL_REG 0x14 /* default 0x40 */ +#define HWM_FAN1_CTL_PWM 0x15 /* default 0x00 */ +#define HWM_FAN2_CTL_PWM 0x16 /* default 0x00 */ +#define HWM_FAN3_CTL_PWM 0x17 /* default 0x00 */ +#define HWM_ADC_TEMP_CHAN_EN_REG 0x51 /* default 0x00 */ + +static void pnp_write_index(u16 port, u8 reg, u8 value) +{ + outb(reg, port); + outb(value, port + 1); +} + +void it8728f_ec_init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + struct resource *res = find_resource(dev, PNP_IDX_IO0); + + if (!res) { + printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); + return; + } + u16 port = res->base; + + printk(BIOS_INFO, + "ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n"); + printk(BIOS_DEBUG, + "ITE IT8728F Super I/O HWM: Base Address at 0x%x\n", port); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + /* ITE IT8728F HWM (ordered) programming sequence. */ + + /* configure fan polarity */ + pnp_write_index(port, HWM_CTL_REG, conf->hwm_ctl_register); + + /* enable fans 1-3 */ + pnp_write_index(port, HWM_MAIN_CTL_REG, conf->hwm_main_ctl_register); + + /* enable termistor temps for temp1-temp3 */ + pnp_write_index(port, HWM_ADC_TEMP_CHAN_EN_REG, conf->hwm_adc_temp_chan_en_reg); + + /* configure which fanX uses which tempY */ + pnp_write_index(port, HWM_FAN1_CTL_PWM, conf->hwm_fan1_ctl_pwm); + pnp_write_index(port, HWM_FAN2_CTL_PWM, conf->hwm_fan2_ctl_pwm); + pnp_write_index(port, HWM_FAN3_CTL_PWM, conf->hwm_fan3_ctl_pwm); + + pnp_exit_conf_mode(dev); +} diff --git a/src/superio/ite/it8728f/it8728f_internal.h b/src/superio/ite/it8728f/it8728f_internal.h new file mode 100644 index 0000000..ece41b9 --- /dev/null +++ b/src/superio/ite/it8728f/it8728f_internal.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_IT8728F_INTERNAL_H +#define SUPERIO_ITE_IT8728F_INTERNAL_H + +#include <device/device.h> + +void hwm_init(device_t dev); + +#endif /* SUPERIO_ITE_IT8728F_INTERNAL_H */ diff --git a/src/superio/ite/it8728f/superio.c b/src/superio/ite/it8728f/superio.c new file mode 100644 index 0000000..45aea0f --- /dev/null +++ b/src/superio/ite/it8728f/superio.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> + +#include "chip.h" +#include "it8728f.h" +#include "it8728f_internal.h" + +static void it8728f_init(device_t dev) +{ + struct superio_ite_it8728f_config *conf = dev->chip_info; + + if (!dev->enabled) + return; + + switch(dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case IT8728F_EC: + it8728f_ec_init(dev); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = it8728f_init, + .ops_pnp_mode = &pnp_conf_mode_870155_aa, +}; + +/* TODO: incomplete */ +static struct pnp_info pnp_dev_info[] = { + { &ops, IT8728F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_ite_it8728f_ops = { + CHIP_NAME("ITE IT8728F Super I/O") + .enable_dev = enable_dev +};

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New patch to review for coreboot: b868e6e [NOTFORMERGE] gizmosphere/gizmo/mptable.c: Program PIC mode correctly
by Paul Menzel 08 May '14

08 May '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5695 -gerrit commit b868e6e363e771f3ec631b82f81e2ead85691be2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu May 8 08:46:16 2014 +0200 [NOTFORMERGE] gizmosphere/gizmo/mptable.c: Program PIC mode correctly Ported Scott’s first patch for ASRock E350M1 to Gizmo. Needs testing and setup should be moved to southbridge code so all boards profit. Change-Id: Id4cf3f84744e844f869a7898b62f36f5e4c6d90a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/gizmosphere/gizmo/mptable.c | 37 +++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index cc9e627..f6f37e4 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -34,6 +34,7 @@ extern u32 apicid_sb800; extern u32 bus_type[256]; extern u32 sbdn_sb800; +/* SB800 interrupt routing register values: APIC mode */ u8 intr_data[] = { [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -49,6 +50,17 @@ u8 intr_data[] = { 0x10, 0x11, 0x12, 0x13 }; +/* SB800 interrupt routing register values: PIC mode */ +u8 intr_data_pic[] = { + 0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F, // 0x00 + 0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, // 0x08 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x10 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x18 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x20 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x28 + 0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F // 0x30 +}; + static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -79,6 +91,12 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); } + /* program the SB800 PIC mode interrupt routing register values */ + for (byte = 0x0; byte < sizeof(intr_data_pic); byte++) { + outb(byte, 0xC00); + outb(intr_data_pic[byte], 0xC01); + } + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -153,6 +171,25 @@ static void *smp_write_config_table(void *v) IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ + /* program interrupt line registers for legacy OS use */ + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 1)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x04, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x11, 0)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 1)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 2)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 5)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(3, PCI_DEVFN(0x00, 0)), 0x3C, 0x0B); + + /* program slave PIC edge-level control register */ + outb(0x0C, 0x4D1); + /* Compute the checksums */ return mptable_finalize(mc); }

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New patch to review for coreboot: d8a97e6 gizmosphere/gizmo/mptable.c: Properly indent with GNU indent 2.2.11
by Paul Menzel 08 May '14

08 May '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5694 -gerrit commit d8a97e6283a49baec9f2f926820401f51a33cf52 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Thu May 8 08:04:44 2014 +0200 gizmosphere/gizmo/mptable.c: Properly indent with GNU indent 2.2.11 $ indent -linux src/mainboard/gizmosphere/gizmo/mptable.c Change-Id: I69ea5b7cd28aadee104d5df8fc3b7e6c88c4ea2a Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/gizmosphere/gizmo/mptable.c | 34 +++++++++++++++++-------------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/src/mainboard/gizmosphere/gizmo/mptable.c b/src/mainboard/gizmosphere/gizmo/mptable.c index 6dfd11d..cc9e627 100755 --- a/src/mainboard/gizmosphere/gizmo/mptable.c +++ b/src/mainboard/gizmosphere/gizmo/mptable.c @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - #include <console/console.h> #include <arch/smp/mpspec.h> #include <device/pci.h> @@ -36,13 +35,18 @@ extern u32 bus_type[256]; extern u32 sbdn_sb800; u8 intr_data[] = { - [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ - [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ - [0x10] = 0x09,0x1F,0x1F,0x10,0x1F,0x12,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, - 0x10,0x11,0x12,0x13 + [0x00] = 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17, /* INTA# - INTH# */ + [0x08] = 0x00, 0x00, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ + [0x10] = + 0x09, 0x1F, 0x1F, 0x10, 0x1F, 0x12, 0x1F, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x12, 0x11, 0x12, 0x11, 0x12, 0x11, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x11, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, + 0x10, 0x11, 0x12, 0x13 }; static void *smp_write_config_table(void *v) @@ -61,7 +65,7 @@ static void *smp_write_config_table(void *v) mptable_write_buses(mc, NULL, &bus_isa); - /* I/O APICs: APIC ID Version State Address */ + /* I/O APICs: APIC ID Version State Address */ u32 dword; u8 byte; @@ -70,12 +74,12 @@ static void *smp_write_config_table(void *v) dword &= 0xFFFFFFF0; smp_write_ioapic(mc, apicid_sb800, 0x21, dword); - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + for (byte = 0x0; byte < sizeof(intr_data); byte++) { outb(byte | 0x80, 0xC00); outb(intr_data[byte], 0xC01); } - /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -91,7 +95,7 @@ static void *smp_write_config_table(void *v) #define PCI_INT(bus, dev, fn, pin) #endif - /* APU Internal Graphic Device*/ + /* APU Internal Graphic Device */ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); @@ -100,7 +104,7 @@ static void *smp_write_config_table(void *v) /* Southbridge HD Audio: */ PCI_INT(0x0, 0x14, 0x2, 0x12); - PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */ PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); @@ -110,7 +114,7 @@ static void *smp_write_config_table(void *v) /* sata */ PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* on board NIC & Slot PCIE. */ + /* on board NIC & Slot PCIE. */ /* PCI slots */ /* PCI_SLOT 0. */ @@ -144,7 +148,7 @@ static void *smp_write_config_table(void *v) /* PCIe PortD */ PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */

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New patch to review for coreboot: 592e9a4 [NOTFORMERGE] asrock/e350m1/mptable.c: Add PIC routing
by Paul Menzel 08 May '14

08 May '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5693 -gerrit commit 592e9a42aea59dc2c939c0d41c3c952dac917a1b Author: Scott Duplichan <scott(a)notabs.org> Date: Wed May 7 18:23:49 2014 +0200 [NOTFORMERGE] asrock/e350m1/mptable.c: Add PIC routing PIC was set up incorrectly. KolibriOS [1] requires PIC and now USB mouse and keyboard work correctly. Tested with KolibriOS from May 7th, 2014. Put the image `kolibri.img` on `/boot` and load it from GRUB 2. [1] http://kolibrios.org/ Change-Id: I8d8f229228706498323875f0c58f02e031fa9a68 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/asrock/e350m1/mptable.c | 36 +++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/src/mainboard/asrock/e350m1/mptable.c b/src/mainboard/asrock/e350m1/mptable.c index 6444be5..313c9fa 100644 --- a/src/mainboard/asrock/e350m1/mptable.c +++ b/src/mainboard/asrock/e350m1/mptable.c @@ -35,6 +35,7 @@ extern u32 apicid_sb800; extern u32 bus_type[256]; extern u32 sbdn_sb800; +// SB800 interrupt routing register values: APIC mode u8 intr_data[] = { [0x00] = 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17, /* INTA# - INTH# */ [0x08] = 0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, /* Misc-nil,0,1,2, INT from Serial irq */ @@ -45,6 +46,16 @@ u8 intr_data[] = { 0x10,0x11,0x12,0x13 }; +// SB800 interrupt routing register values: PIC mode +u8 intr_data_pic[] = { + 0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F, // 0x00 + 0x00, 0xF1, 0x00, 0x00, 0x1F, 0x1F, 0x1F, 0x1F, // 0x08 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x10 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x18 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x20 + 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, 0x1F, // 0x28 + 0x0B, 0x0A, 0x0B, 0x0A, 0x1F, 0x1F, 0x1F, 0x1F}; // 0x30 + static void *smp_write_config_table(void *v) { struct mp_config_table *mc; @@ -75,6 +86,12 @@ static void *smp_write_config_table(void *v) outb(intr_data[byte], 0xC01); } + // program the SB800 PIC mode interrupt routing register values + for (byte = 0x0; byte < sizeof(intr_data_pic); byte ++) { + outb(byte, 0xC00); + outb(intr_data_pic[byte], 0xC01); + } + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ #define IO_LOCAL_INT(type, intr, apicid, pin) \ smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); @@ -149,6 +166,25 @@ static void *smp_write_config_table(void *v) IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ + // program interrupt line registers for legacy OS use + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x01, 1)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x04, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x11, 0)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x12, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x13, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 1)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 2)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x14, 5)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 0)), 0x3C, 0x0B); + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x16, 2)), 0x3C, 0x0A); + pci_write_config32(dev_find_slot(3, PCI_DEVFN(0x00, 0)), 0x3C, 0x0B); + + // program slave PIC edge-level control register + outb (0x0C, 0x4D1); + /* Compute the checksums */ return mptable_finalize(mc); }

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Patch merged into coreboot/master: 9928197 rambi: Make ec_in_rw a legacy GPIO
by gerrit＠coreboot.org 08 May '14

08 May '14

the following patch was just integrated into master: commit 9928197c2678d6b19df40fe0d049f237bc924614 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Sat Dec 7 17:08:27 2013 -0800 rambi: Make ec_in_rw a legacy GPIO ec_in_rw needs to be read by depthcharge, which only supports legacy GPIOs. BUG=chrome-os-partner:24408 TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge detects the proper ec_in_ro state. BRANCH=None Change-Id: I25802b445c795eb85580c22d880efee8eeb21318 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179228 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4993 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4993 for details. -gerrit

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Patch merged into coreboot/master: 27351b9 baytrail: gpio: Make GPIO inputs MMIO by default
by gerrit＠coreboot.org 08 May '14

08 May '14

the following patch was just integrated into master: commit 27351b93c07e62a1b23dd492b625f0eca6e9283a Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Dec 6 16:58:10 2013 -0800 baytrail: gpio: Make GPIO inputs MMIO by default The Linux kernel driver cannot handle Baytrail legacy GPIOs, so make the default input GPIO type MMIO. BUG=chrome-os-partner:24408 TEST=Manual on Rambi. Run "echo 169 > /sys/class/gpio/export; cat /sys/class/gpio/gpio169/value", verify GPIO value changes based upon mic jack status. BRANCH=None Change-Id: I27870ce8b7ecae9228e06e48c8759409c824c2eb Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179169 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4992 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4992 for details. -gerrit

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Patch merged into coreboot/master: 70cc908 rambi: Change eMMC pin PUs to 2K
by gerrit＠coreboot.org 08 May '14

08 May '14

the following patch was just integrated into master: commit 70cc9084a51e7f276b20d146fdab5fda6884febb Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Thu Dec 5 14:57:08 2013 -0800 rambi: Change eMMC pin PUs to 2K Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up on certain boards. BUG=chrome-os-partner:24353 TEST=Manual. Burn FW on board that previously failed to boot eMMC, verify chromeos can now install + boot from eMMC. BRANCH=none Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178917 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/4991 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/4991 for details. -gerrit

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