coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 7bf0bce via: Remove GFXUMA and related global variables
by Kyösti Mälkki 12 May '14

12 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5721 -gerrit commit 7bf0bceb11bf3b9c4169f1612ba5fbc87c37bdf3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 18 11:02:56 2013 +0300 via: Remove GFXUMA and related global variables Remove global variables uma_memory_base and uma_memory_size from builds with VIA northbridge, as these variables can be kept within the chipset. Change-Id: I9f8aea4836d81e704eae6a0f2cefc7fd4586b8b8 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/via/vx900/Kconfig | 1 - src/northbridge/via/vx900/chrome9hd.c | 18 ++++++------------ src/northbridge/via/vx900/northbridge.c | 14 ++++++++++++++ src/northbridge/via/vx900/vx900.h | 1 + 4 files changed, 21 insertions(+), 13 deletions(-) diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 910523f..9fe5909 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -26,7 +26,6 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_HARD_RESET select MMCONF_SUPPORT select MMCONF_SUPPORT_DEFAULT - select GFXUMA if NORTHBRIDGE_VIA_VX900 diff --git a/src/northbridge/via/vx900/chrome9hd.c b/src/northbridge/via/vx900/chrome9hd.c index 55e2a96..bf0b278 100644 --- a/src/northbridge/via/vx900/chrome9hd.c +++ b/src/northbridge/via/vx900/chrome9hd.c @@ -220,12 +220,6 @@ static void chrome9hd_handle_uma(device_t dev) /* Mirror mirror, shiny glass, tell me that is not my ass */ u32 fb_size = chrome9hd_fb_size() >> 20; - //uma_resource(dev, 0x18, uma_memory_base>>10, uma_memory_size>>10); - - printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); - printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, - uma_memory_size >> 20); u8 fb_pow = 0; while (fb_size >> fb_pow) fb_pow++; @@ -286,13 +280,13 @@ static void chrome9hd_biosguide_init_seq(device_t dev) chrome9hd_handle_uma(dev); - /* Step 8 - Enable memory base register on the GFX */ - if (uma_memory_base == 0) + uint64_t gfx_base = get_uma_memory_base(); + if (gfx_base == 0) die("uma_memory_base not set. Abandon ship!\n"); - printk(BIOS_DEBUG, "UMA base 0x%.10llx (%lluMB)\n", uma_memory_base, - uma_memory_base >> 20); - vga_sr_write(0x6d, (uma_memory_base >> 21) & 0xff); /* base 28:21 */ - vga_sr_write(0x6e, (uma_memory_base >> 29) & 0xff); /* base 36:29 */ + + /* Step 8 - Enable memory base register on the GFX */ + vga_sr_write(0x6d, (gfx_base >> 21) & 0xff); /* base 28:21 */ + vga_sr_write(0x6e, (gfx_base >> 29) & 0xff); /* base 36:29 */ vga_sr_write(0x6f, 0x00); /* base 43:37 */ /* Step 9 - Set SID/VID */ diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index 25e6045..56d1da0 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -32,6 +32,9 @@ #define RAM_4GB (((u64)1) << 32) +static uint64_t uma_memory_base = 0; +static uint64_t uma_memory_size = 0; + /** * @file northbridge.c * @@ -48,6 +51,15 @@ void hard_reset(void) outb((1 << 2) | (1 << 1), 0xcf9); } +uint64_t get_uma_memory_base(void) +{ + printk(BIOS_DEBUG, "UMA base 0x%.8llx (%lluMB)\n", uma_memory_base, + uma_memory_base >> 20); + printk(BIOS_DEBUG, "UMA size 0x%.8llx (%lluMB)\n", uma_memory_size, + uma_memory_size >> 20); + return uma_memory_base; +} + static u64 vx900_get_top_of_ram(device_t mcu) { u16 reg16; @@ -260,6 +272,8 @@ static void vx900_set_resources(device_t dev) uma_memory_size = fbufk << 10; uma_memory_base = tolmk << 10; + //uma_resource(dev, idx++, uma_memory_base>>10, uma_memory_size>>10); + printk(BIOS_DEBUG, "UMA @ %lldMB + %lldMB\n", uma_memory_base >> 20, uma_memory_size >> 20); /* FIXME: How do we handle remapping above 4G? */ diff --git a/src/northbridge/via/vx900/vx900.h b/src/northbridge/via/vx900/vx900.h index 8c0157a..d00daa3 100644 --- a/src/northbridge/via/vx900/vx900.h +++ b/src/northbridge/via/vx900/vx900.h @@ -40,6 +40,7 @@ u32 chrome9hd_fb_size(void); u8 vx900_int15_get_5f18_bl(void); +uint64_t get_uma_memory_base(void); /* We use these throughout the code. They really belong in a generic part of * coreboot, but until bureaucracy gets them there, we still need them */

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New patch to review for coreboot: 7a1e17f intel: Remove GFXUMA and related global variables
by Kyösti Mälkki 12 May '14

12 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5720 -gerrit commit 7a1e17fac31402efd241bbd20868c9a37595b62c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 18 11:02:46 2013 +0300 intel: Remove GFXUMA and related global variables Remove use of global variables uma_memory_base and uma_memory_size from builds with Intel northbridges, as these variables can be kept within the chipset or even as stack locals. Intel platforms have no functional implemenation for option GFXUMA. If we did implement some choice between external and integrated graphics, it needs to be named in less obscure fashion. Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/asus/mew-am/Kconfig | 1 - src/mainboard/asus/mew-vm/Kconfig | 1 - src/mainboard/ecs/p6iwp-fe/Kconfig | 1 - src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/google/butterfly/Kconfig | 1 - src/mainboard/google/link/Kconfig | 1 - src/mainboard/google/parrot/Kconfig | 1 - src/mainboard/google/stout/Kconfig | 1 - src/mainboard/hp/e_vectra_p2706t/Kconfig | 1 - src/mainboard/ibase/mb899/Kconfig | 1 - src/mainboard/intel/cougar_canyon2/Kconfig | 1 - src/mainboard/intel/d810e2cb/Kconfig | 1 - src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/intel/emeraldlake2/Kconfig | 1 - src/mainboard/iwave/iWRainbowG6/Kconfig | 1 - src/mainboard/kontron/986lcd-m/Kconfig | 1 - src/mainboard/kontron/ktqm77/Kconfig | 1 - src/mainboard/lenovo/t530/Kconfig | 1 - src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x201/Kconfig | 1 - src/mainboard/lenovo/x230/Kconfig | 1 - src/mainboard/lenovo/x60/Kconfig | 1 - src/mainboard/mitac/6513wu/Kconfig | 1 - src/mainboard/msi/ms6178/Kconfig | 1 - src/mainboard/nec/powermate2000/Kconfig | 1 - src/mainboard/packardbell/ms2290/Kconfig | 1 - src/mainboard/rca/rm4100/Kconfig | 1 - src/mainboard/roda/rk886ex/Kconfig | 1 - src/mainboard/samsung/lumpy/Kconfig | 1 - src/mainboard/samsung/stumpy/Kconfig | 1 - src/mainboard/thomson/ip1000/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/northbridge.c | 4 ++++ src/northbridge/intel/i82810/northbridge.c | 1 + src/northbridge/intel/i82830/northbridge.c | 1 + src/northbridge/intel/i945/northbridge.c | 1 + src/northbridge/intel/sandybridge/northbridge.c | 4 ++++ src/northbridge/intel/sch/northbridge.c | 1 + 37 files changed, 12 insertions(+), 31 deletions(-) diff --git a/src/mainboard/asus/mew-am/Kconfig b/src/mainboard/asus/mew-am/Kconfig index ad08c31..509d281 100644 --- a/src/mainboard/asus/mew-am/Kconfig +++ b/src/mainboard/asus/mew-am/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/asus/mew-vm/Kconfig b/src/mainboard/asus/mew-vm/Kconfig index 58910be..46b6eb8 100644 --- a/src/mainboard/asus/mew-vm/Kconfig +++ b/src/mainboard/asus/mew-vm/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/ecs/p6iwp-fe/Kconfig b/src/mainboard/ecs/p6iwp-fe/Kconfig index 99170be..5670dae 100644 --- a/src/mainboard/ecs/p6iwp-fe/Kconfig +++ b/src/mainboard/ecs/p6iwp-fe/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 3696b14..1ccf39e 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -38,7 +38,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_SLIC select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 - select GFXUMA select CHANNEL_XOR_RANDOMIZATION select RTL8168_ROM_DISABLE diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 1b7fe32..6a61e6b 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select GFXUMA select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index fcecca0..ebd038a 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select GFXUMA select MAINBOARD_HAS_CHROMEOS select SERIRQ_CONTINUOUS_MODE select MAINBOARD_HAS_NATIVE_VGA_INIT diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 23cea06..ed494e8 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select GFXUMA select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index e683455..2f8f580 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select GFXUMA select MAINBOARD_HAS_CHROMEOS config MAINBOARD_DIR diff --git a/src/mainboard/hp/e_vectra_p2706t/Kconfig b/src/mainboard/hp/e_vectra_p2706t/Kconfig index c5aa340..4ae03cc 100644 --- a/src/mainboard/hp/e_vectra_p2706t/Kconfig +++ b/src/mainboard/hp/e_vectra_p2706t/Kconfig @@ -31,7 +31,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 8975be2..e1809fe 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select GFXUMA select CHANNEL_XOR_RANDOMIZATION config MAINBOARD_DIR diff --git a/src/mainboard/intel/cougar_canyon2/Kconfig b/src/mainboard/intel/cougar_canyon2/Kconfig index cc263fd..ad3a404 100644 --- a/src/mainboard/intel/cougar_canyon2/Kconfig +++ b/src/mainboard/intel/cougar_canyon2/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select MMCONF_SUPPORT - select GFXUMA select SUPERIO_SMSC_SIO1007 select ENABLE_VMX select EARLY_CBMEM_INIT diff --git a/src/mainboard/intel/d810e2cb/Kconfig b/src/mainboard/intel/d810e2cb/Kconfig index 85b0e6c..691055d 100644 --- a/src/mainboard/intel/d810e2cb/Kconfig +++ b/src/mainboard/intel/d810e2cb/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select USE_WATCHDOG_ON_BOOT select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 490aa80..02522f1 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 - select GFXUMA select CHANNEL_XOR_RANDOMIZATION select RTL8168_ROM_DISABLE diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 77aa910..aa273bd 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select GFXUMA #select MAINBOARD_HAS_CHROMEOS select EARLY_CBMEM_INIT diff --git a/src/mainboard/iwave/iWRainbowG6/Kconfig b/src/mainboard/iwave/iWRainbowG6/Kconfig index e29615e..e9ecede 100644 --- a/src/mainboard/iwave/iWRainbowG6/Kconfig +++ b/src/mainboard/iwave/iWRainbowG6/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_LAPIC select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 - select GFXUMA select BROKEN_CAR_MIGRATE config MAINBOARD_DIR diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index f5d4f8c..8fce5eb 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 - select GFXUMA select CHANNEL_XOR_RANDOMIZATION select OVERRIDE_CLOCK_DISABLE select RTL8168_ROM_DISABLE diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 96153f7..1175b67 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,7 +12,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select GFXUMA select EARLY_CBMEM_INIT select ENABLE_VMX select HAVE_MRC diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 99b5849..86280d5 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select GFXUMA select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index cb2bb39..a99cc2c 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -15,7 +15,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index ff9f0ae..50df47b 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -11,7 +11,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select GFXUMA select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 2ce51a8..54270d3 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -13,7 +13,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER - select GFXUMA select EARLY_CBMEM_INIT # Workaround for EC/KBC IRQ1. diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 1158046..5abb14c 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES diff --git a/src/mainboard/mitac/6513wu/Kconfig b/src/mainboard/mitac/6513wu/Kconfig index 6228a6e..729ac29 100644 --- a/src/mainboard/mitac/6513wu/Kconfig +++ b/src/mainboard/mitac/6513wu/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/msi/ms6178/Kconfig b/src/mainboard/msi/ms6178/Kconfig index cc70e76..ed6f636 100644 --- a/src/mainboard/msi/ms6178/Kconfig +++ b/src/mainboard/msi/ms6178/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/nec/powermate2000/Kconfig b/src/mainboard/nec/powermate2000/Kconfig index 6fddcc1..d69aa46 100644 --- a/src/mainboard/nec/powermate2000/Kconfig +++ b/src/mainboard/nec/powermate2000/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/packardbell/ms2290/Kconfig b/src/mainboard/packardbell/ms2290/Kconfig index 5b71ad8..9508aa6 100644 --- a/src/mainboard/packardbell/ms2290/Kconfig +++ b/src/mainboard/packardbell/ms2290/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_IBEXPEAK select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT - select GFXUMA select BOARD_ROMSIZE_KB_4096 select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME diff --git a/src/mainboard/rca/rm4100/Kconfig b/src/mainboard/rca/rm4100/Kconfig index 975977f..8f04505 100644 --- a/src/mainboard/rca/rm4100/Kconfig +++ b/src/mainboard/rca/rm4100/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 94290d5..ffc593e 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION - select GFXUMA select RTL8168_ROM_DISABLE config MAINBOARD_DIR diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 9c8c466..64c2446 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -6,7 +6,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 select EC_SMSC_MEC1308 - select GFXUMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index e38efe0..e9a7097 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS select CPU_INTEL_SOCKET_RPGA989 - select GFXUMA select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE diff --git a/src/mainboard/thomson/ip1000/Kconfig b/src/mainboard/thomson/ip1000/Kconfig index 971c41c..a68c72a 100644 --- a/src/mainboard/thomson/ip1000/Kconfig +++ b/src/mainboard/thomson/ip1000/Kconfig @@ -9,7 +9,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 - select GFXUMA config MAINBOARD_DIR string diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 2922ca0..182252d 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -41,6 +41,10 @@ static int bridge_revision_id = -1; static u8 finished_FSP_after_pci = 0; +/* IGD UMA memory */ +static uint64_t uma_memory_base = 0; +static uint64_t uma_memory_size = 0; + int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { diff --git a/src/northbridge/intel/i82810/northbridge.c b/src/northbridge/intel/i82810/northbridge.c index 2e07db8..9d10f1d 100644 --- a/src/northbridge/intel/i82810/northbridge.c +++ b/src/northbridge/intel/i82810/northbridge.c @@ -73,6 +73,7 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; int igd_memory = 0; + uint64_t uma_memory_base = 0, uma_memory_size = 0; mc_dev = dev->link_list->children; if (!mc_dev) diff --git a/src/northbridge/intel/i82830/northbridge.c b/src/northbridge/intel/i82830/northbridge.c index 08ed279..c78bdf1 100644 --- a/src/northbridge/intel/i82830/northbridge.c +++ b/src/northbridge/intel/i82830/northbridge.c @@ -54,6 +54,7 @@ static void pci_domain_set_resources(device_t dev) { device_t mc_dev; int igd_memory = 0; + uint64_t uma_memory_base = 0, uma_memory_size = 0; mc_dev = dev->link_list->children; if (!mc_dev) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 922a819..180ffde 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -87,6 +87,7 @@ static void pci_domain_set_resources(device_t dev) uint8_t tolud, reg8; uint16_t reg16; unsigned long long tomk, tomk_stolen; + uint64_t uma_memory_base = 0, uma_memory_size = 0; uint64_t tseg_memory_base = 0, tseg_memory_size = 0; /* Can we find out how much memory we can use at most diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 1fd252b..5f9912f 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -39,6 +39,10 @@ static int bridge_revision_id = -1; +/* IGD UMA memory */ +static uint64_t uma_memory_base = 0; +static uint64_t uma_memory_size = 0; + int bridge_silicon_revision(void) { if (bridge_revision_id < 0) { diff --git a/src/northbridge/intel/sch/northbridge.c b/src/northbridge/intel/sch/northbridge.c index 9dc33f5..0bbf91b 100644 --- a/src/northbridge/intel/sch/northbridge.c +++ b/src/northbridge/intel/sch/northbridge.c @@ -99,6 +99,7 @@ static void pci_domain_set_resources(device_t dev) u8 reg8; u16 reg16; unsigned long long tomk, tolud, tomk_stolen; + uint64_t uma_memory_base = 0, uma_memory_size = 0; uint64_t tseg_memory_base = 0, tseg_memory_size = 0; /* Can we find out how much memory we can use at most this way? */

1 0

New patch to review for coreboot: c7079b8 intel: Drop obsolete comments on MTRR usage
by Kyösti Mälkki 12 May '14

12 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5719 -gerrit commit c7079b8c9534ccb53a15d1103b54bcff2becd9ff Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 12 15:00:03 2014 +0300 intel: Drop obsolete comments on MTRR usage Problem with UMA region allocation was fixed when MTRRs changed to use memrange implementation. Change-Id: I420dac30de2836a91596d81f88bb45b46f248532 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/device/device.h | 4 ---- src/northbridge/intel/fsp_sandybridge/northbridge.c | 11 ----------- src/northbridge/intel/nehalem/northbridge.c | 11 ----------- src/northbridge/intel/sandybridge/northbridge.c | 11 ----------- 4 files changed, 37 deletions(-) diff --git a/src/include/device/device.h b/src/include/device/device.h index fd26c04..a4ef456 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -213,10 +213,6 @@ void fixed_mem_resource(device_t dev, unsigned long index, /* It is the caller's responsibility to adjust regions such that ram_resource() * and mmio_resource() do not overlap. - * - * Current MTRR setup creates exclusive uncacheable holes for uma_resource() - * only and these are allowed to overlap any ram_resource(). This approach - * is used for all UMA except Intel Sandy/IvyBridge. */ #define ram_resource(dev, idx, basek, sizek) \ fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE) diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index d5b1575..2922ca0 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -102,17 +102,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index d94bc09..639d245 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -134,17 +134,6 @@ static void mc_read_resources(device_t dev) ram_resource(dev, 3, 0, 640); ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768)); - /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10); reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC); diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5440140..1fd252b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -100,17 +100,6 @@ static void add_fixed_resources(struct device *dev, int index) struct resource *resource; u32 pcie_config_base, pcie_config_size; - /* Using uma_resource() here would fail as base & size cannot - * be used as-is for a single MTRR. This would cause excessive - * use of MTRRs. - * - * Use of mmio_resource() instead does not create UC holes by using - * MTRRs, but making these regions uncacheable is taken care of by - * making sure they do not overlap with any ram_resource(). - * - * The resources can be changed to use separate mmio_resource() - * calls after MTRR code is able to merge them wisely. - */ mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {

1 0

New patch to review for coreboot: 71c3c6e Add guard for UMA globals
by Kyösti Mälkki 12 May '14

12 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5718 -gerrit commit 71c3c6eb98a36ff847fb39736966529fe4f7cb33 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Oct 18 11:02:46 2013 +0300 Add guard for UMA globals We no longer need these globally. Guard them so we get to declare static replacements at few locations until complete removal. Change-Id: Ie33e2a680fc9bbb7e28c8fbe17e5181e626736a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/device/device.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/include/device/device.h b/src/include/device/device.h index dfebeaa..fd26c04 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -131,9 +131,11 @@ extern struct bus *free_links; extern const char mainboard_name[]; +#if CONFIG_GFXUMA /* IGD UMA memory */ extern uint64_t uma_memory_base; extern uint64_t uma_memory_size; +#endif /* Generic device interface functions */ device_t alloc_dev(struct bus *parent, struct device_path *path);

1 0

Patch set updated for coreboot: 93f96d4 southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
by Edward O'Callaghan 12 May '14

12 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5669 -gerrit commit 93f96d44bff7848147aeb13cc9b0135af5ce656b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 23:53:09 2014 +1000 southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/romstage.c | 10 ---------- src/mainboard/amd/inagua/romstage.c | 10 ---------- src/mainboard/amd/olivehill/romstage.c | 9 --------- src/mainboard/amd/parmer/romstage.c | 10 ---------- src/mainboard/amd/persimmon/romstage.c | 10 ---------- src/mainboard/amd/thatcher/romstage.c | 10 ---------- src/mainboard/amd/torpedo/romstage.c | 13 ------------- src/mainboard/asrock/e350m1/romstage.c | 10 ---------- src/mainboard/asrock/imb-a180/romstage.c | 9 --------- src/mainboard/asus/f2a85-m/romstage.c | 11 ----------- src/mainboard/gizmosphere/gizmo/romstage.c | 10 ---------- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 11 ----------- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 12 ------------ src/mainboard/lippert/frontrunner-af/romstage.c | 10 ---------- src/mainboard/lippert/toucan-af/romstage.c | 10 ---------- src/mainboard/supermicro/h8scm/romstage.c | 10 ---------- src/mainboard/tyan/s8226/romstage.c | 4 ---- src/southbridge/amd/cimx/sb700/late.c | 5 +++++ src/southbridge/amd/cimx/sb800/late.c | 5 +++++ src/southbridge/amd/cimx/sb900/late.c | 5 +++++ 20 files changed, 15 insertions(+), 169 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 776ecd5..8ed1398 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -32,8 +32,6 @@ #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "nb_cimx.h" #include <sb_cimx.h> #include "Platform.h" @@ -140,14 +138,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 98c74d6..a304d31 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -35,8 +35,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -112,14 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 6422393..73cd40a 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -160,13 +158,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index a5d041f..668dfc8 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -141,14 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 47c03ec..9ba34e7 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,8 +35,6 @@ #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -170,14 +168,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 9c3cf5b..1a7a399 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -35,8 +35,6 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "src/superio/smsc/lpc47n217/early_serial.c" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) @@ -158,14 +156,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 58b88d0..dcab52b 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -32,8 +32,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> @@ -112,17 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - printk(BIOS_DEBUG, "setup_i8259\n"); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - printk(BIOS_DEBUG, "setup_i8254\n"); - setup_i8254(); - - post_code(0x43); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index ba2e34d..2913c08 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -35,8 +35,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -115,14 +113,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 59d95f9..5b64cf9 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" #include "superio/winbond/w83627uhg/early_serial.c" @@ -184,13 +182,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 487f068..ffd91bf 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -38,9 +38,6 @@ #include <string.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -/* TODO: remove .c includes */ -#include <drivers/pc80/i8254.c> -#include <drivers/pc80/i8259.c> #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff @@ -201,14 +198,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index f639d1f..11ae623 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,8 +33,6 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -178,14 +176,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 24751f4..2be2bc5 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -34,9 +34,6 @@ #include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -139,14 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 8c05236..bfd24cb 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -44,10 +44,6 @@ #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> -/* FIXME: should not include .c files */ -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" - /* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1) @@ -188,14 +184,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif /* CONFIG_HAVE_ACPI_RESUME */ - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 16fb8ab..cf5c566 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -173,14 +171,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 93ff521..accf381 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -35,8 +35,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -174,14 +172,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 0f5abdf..e7a1c4c 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -31,8 +31,6 @@ #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "superio/nuvoton/wpcm450/wpcm450.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -122,14 +120,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index fc239e4..f4befe6 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -33,8 +33,6 @@ #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -133,8 +131,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n"); post_code(0x51); - setup_i8259 (); - setup_i8254 (); copy_and_run(); /* We will not return, Should never see this message and post code. */ diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 9605083..42330ca 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -24,6 +24,8 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <console/console.h> /* printk */ #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ @@ -87,6 +89,9 @@ static void lpc_init(device_t dev) */ rtc_init(0); + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 219118a..40b422b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,8 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <console/console.h> /* printk */ #include <arch/acpi.h> #include <device/pci_ehci.h> @@ -136,6 +138,9 @@ static void lpc_init(device_t dev) */ rtc_init(0); + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 3cd603c..7303bdc 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -23,6 +23,8 @@ #include <device/pci_ids.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <console/console.h> /* printk */ #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ @@ -109,6 +111,9 @@ static void lpc_init(device_t dev) */ rtc_init(0); + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); }

1 0

Patch set updated for coreboot: 539ff4f southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
by Edward O'Callaghan 12 May '14

12 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5669 -gerrit commit 539ff4f897de4fc4de84c543ec78e2ce092433cb Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 23:53:09 2014 +1000 southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge We should configure i8254/i8259 down in to the southbridge rather than romstage of every AGESA/CIMx board much like Intel boards do. Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dinar/romstage.c | 10 ---------- src/mainboard/amd/inagua/romstage.c | 10 ---------- src/mainboard/amd/olivehill/romstage.c | 9 --------- src/mainboard/amd/parmer/romstage.c | 10 ---------- src/mainboard/amd/persimmon/romstage.c | 10 ---------- src/mainboard/amd/thatcher/romstage.c | 10 ---------- src/mainboard/amd/torpedo/romstage.c | 13 ------------- src/mainboard/asrock/e350m1/romstage.c | 10 ---------- src/mainboard/asrock/imb-a180/romstage.c | 9 --------- src/mainboard/asus/f2a85-m/romstage.c | 11 ----------- src/mainboard/gizmosphere/gizmo/romstage.c | 10 ---------- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 11 ----------- src/mainboard/lippert/frontrunner-af/romstage.c | 10 ---------- src/mainboard/lippert/toucan-af/romstage.c | 10 ---------- src/mainboard/supermicro/h8scm/romstage.c | 10 ---------- src/mainboard/tyan/s8226/romstage.c | 4 ---- src/southbridge/amd/cimx/sb700/late.c | 5 +++++ src/southbridge/amd/cimx/sb800/late.c | 5 +++++ src/southbridge/amd/cimx/sb900/late.c | 5 +++++ 19 files changed, 15 insertions(+), 157 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 776ecd5..8ed1398 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -32,8 +32,6 @@ #include "superio/smsc/sch4037/sch4037_early_init.c" #include "superio/smsc/sio1036/sio1036_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "nb_cimx.h" #include <sb_cimx.h> #include "Platform.h" @@ -140,14 +138,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x43); print_debug("Disabling cache as ram "); disable_cache_as_ram(); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 98c74d6..a304d31 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -35,8 +35,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -112,14 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 6422393..73cd40a 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -160,13 +158,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index a5d041f..668dfc8 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" @@ -141,14 +139,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 47c03ec..9ba34e7 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -35,8 +35,6 @@ #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -170,14 +168,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 9c3cf5b..1a7a399 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -35,8 +35,6 @@ #include "southbridge/amd/agesa/hudson/hudson.h" #include "src/superio/smsc/lpc47n217/early_serial.c" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" #define SERIAL_DEV PNP_DEV(0x2e, LPC47N217_SP1) @@ -158,14 +156,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 58b88d0..dcab52b 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -32,8 +32,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/kbc1100/kbc1100_early_init.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include "sb_cimx.h" #include "SbPlatform.h" #include <arch/cpu.h> @@ -112,17 +110,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - printk(BIOS_DEBUG, "setup_i8259\n"); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - printk(BIOS_DEBUG, "setup_i8254\n"); - setup_i8254(); - - post_code(0x43); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run returned!\n"); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index ba2e34d..2913c08 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -35,8 +35,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -115,14 +113,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) else printk(BIOS_DEBUG, "passed.\n"); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259(); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254(); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 59d95f9..5b64cf9 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" #include "cpu/amd/agesa/s3_resume.h" -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "cbmem.h" #include "superio/winbond/w83627uhg/early_serial.c" @@ -184,13 +182,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xEA, 0xCD6); outb(0x1, 0xcd7); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 487f068..ffd91bf 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -38,9 +38,6 @@ #include <string.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> -/* TODO: remove .c includes */ -#include <drivers/pc80/i8254.c> -#include <drivers/pc80/i8259.c> #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff @@ -201,14 +198,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index f639d1f..11ae623 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,8 +33,6 @@ #include "cpu/amd/car.h" #include "agesawrapper.h" #include "cpu/x86/bist.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -178,14 +176,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 24751f4..2be2bc5 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -34,9 +34,6 @@ #include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; @@ -139,14 +136,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); copy_and_run(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 16fb8ab..cf5c566 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -34,8 +34,6 @@ #include "cpu/x86/bist.h" #include "superio/smsc/smscsuperio/early_serial.c" #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -173,14 +171,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 93ff521..accf381 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -35,8 +35,6 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include "cpu/x86/lapic.h" -#include "drivers/pc80/i8254.c" -#include "drivers/pc80/i8259.c" #include <cpu/x86/cache.h> #include <sb_cimx.h> #include "SBPLATFORM.h" @@ -174,14 +172,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } #endif - /* Initialize i8259 pic */ - post_code(0x43); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x44); - setup_i8254 (); - post_code(0x50); copy_and_run(); printk(BIOS_ERR, "Error: copy_and_run() returned!\n"); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index 0f5abdf..e7a1c4c 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -31,8 +31,6 @@ #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #include "superio/nuvoton/wpcm450/wpcm450.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -122,14 +120,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x42); - /* Initialize i8259 pic */ - post_code(0x41); - setup_i8259 (); - - /* Initialize i8254 timers */ - post_code(0x42); - setup_i8254 (); - post_code(0x50); print_debug("Disabling cache as ram "); disable_cache_as_ram(); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index fc239e4..f4befe6 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -33,8 +33,6 @@ #include <sb_cimx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> -#include "src/drivers/pc80/i8254.c" -#include "src/drivers/pc80/i8259.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) @@ -133,8 +131,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) print_debug("done\n"); post_code(0x51); - setup_i8259 (); - setup_i8254 (); copy_and_run(); /* We will not return, Should never see this message and post code. */ diff --git a/src/southbridge/amd/cimx/sb700/late.c b/src/southbridge/amd/cimx/sb700/late.c index 9605083..42330ca 100644 --- a/src/southbridge/amd/cimx/sb700/late.c +++ b/src/southbridge/amd/cimx/sb700/late.c @@ -24,6 +24,8 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <console/console.h> /* printk */ #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ @@ -87,6 +89,9 @@ static void lpc_init(device_t dev) */ rtc_init(0); + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + printk(BIOS_DEBUG, "SB700 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 219118a..40b422b 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -24,6 +24,8 @@ #include <arch/ioapic.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <console/console.h> /* printk */ #include <arch/acpi.h> #include <device/pci_ehci.h> @@ -136,6 +138,9 @@ static void lpc_init(device_t dev) */ rtc_init(0); + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + printk(BIOS_DEBUG, "SB800 - Late.c - lpc_init - End.\n"); } diff --git a/src/southbridge/amd/cimx/sb900/late.c b/src/southbridge/amd/cimx/sb900/late.c index 3cd603c..7303bdc 100644 --- a/src/southbridge/amd/cimx/sb900/late.c +++ b/src/southbridge/amd/cimx/sb900/late.c @@ -23,6 +23,8 @@ #include <device/pci_ids.h> #include <device/smbus.h> /* smbus_bus_operations */ #include <pc80/mc146818rtc.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> #include <console/console.h> /* printk */ #include <device/pci_ehci.h> #include "lpc.h" /* lpc_read_resources */ @@ -109,6 +111,9 @@ static void lpc_init(device_t dev) */ rtc_init(0); + setup_i8259(); /* Initialize i8259 pic */ + setup_i8254(); /* Initialize i8254 timers */ + printk(BIOS_DEBUG, "SB900 - Late.c - lpc_init - End.\n"); }

1 0

Patch set updated for coreboot: b3bd6e2 superio/ite/it8718f: Remove hard coding from romstage
by Edward O'Callaghan 11 May '14

11 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5717 -gerrit commit b3bd6e2ecd340cf7d251608c632ef8a8127c717d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 12 05:02:58 2014 +1000 superio/ite/it8718f: Remove hard coding from romstage Make use of the ITE common Super I/O framework and there-by removing any hard coding of Super I/O base address. Change-Id: I14af89d2727d7c6bac0f9840043c430726297429 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/gigabyte/ma785gm/romstage.c | 3 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 3 +- src/mainboard/gigabyte/ma78gm/romstage.c | 3 +- src/superio/ite/it8718f/early_serial.c | 44 +++--------------------------- src/superio/ite/it8718f/it8718f.h | 6 ++-- 5 files changed, 13 insertions(+), 46 deletions(-) diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 451cb79..62a9211 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 451cb79..62a9211 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bfc50b6..a437009 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -51,6 +51,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index deef840..166c856 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -19,51 +19,15 @@ */ #include <arch/io.h> +#include <superio/ite/common/ite.h> #include "it8718f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8718f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8718f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8718f_exit_conf(void) -{ - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); -} - - /* * GIGABYTE uses a special Super I/O register to protect its Dual BIOS * mechanism. It lives in the GPIO LDN. However, register 0xEF is not * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ -void it8718f_disable_reboot(void) +void it8718f_disable_reboot(device_t dev) { - it8718f_enter_conf(); - it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); - it8718f_exit_conf(); + ite_reg_write(dev, 0xEF, 0x7E); } diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 018f08a..61c75cf 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -21,6 +21,8 @@ #ifndef SUPERIO_ITE_IT8718F_H #define SUPERIO_ITE_IT8718F_H +#include <arch/io.h> + /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */ #define IT8718F_FDC 0x00 /* Floppy */ @@ -33,8 +35,6 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) -void it8718f_disable_reboot(void); -#endif +void it8718f_disable_reboot(device_t dev); #endif /* SUPERIO_ITE_IT8718F_H */

1 0

New patch to review for coreboot: 056b0ff superio/ite/it8718f: Remove hard coding from romstage
by Edward O'Callaghan 11 May '14

11 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5717 -gerrit commit 056b0ff6f5f9399d7be1ac877ea742b0027a5f85 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Mon May 12 05:02:58 2014 +1000 superio/ite/it8718f: Remove hard coding from romstage Make use of common ITE superio framework and there-by removing any hard coding of superio base address. Change-Id: I14af89d2727d7c6bac0f9840043c430726297429 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/gigabyte/ma785gm/romstage.c | 3 ++- src/mainboard/gigabyte/ma785gmt/romstage.c | 3 ++- src/mainboard/gigabyte/ma78gm/romstage.c | 3 ++- src/superio/ite/it8718f/early_serial.c | 43 +++--------------------------- src/superio/ite/it8718f/it8718f.h | 6 ++--- 5 files changed, 12 insertions(+), 46 deletions(-) diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index 451cb79..62a9211 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index 451cb79..62a9211 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -47,6 +47,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bfc50b6..a437009 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -51,6 +51,7 @@ #include "northbridge/amd/amdfam10/debug.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8718F_GPIO) static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -99,7 +100,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8718f_disable_reboot(); + it8718f_disable_reboot(GPIO_DEV); console_init(); diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index deef840..85854c2 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -21,49 +21,12 @@ #include <arch/io.h> #include "it8718f.h" -/* The base address is 0x2e or 0x4e, depending on config bytes. */ -#define SIO_BASE 0x2e -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8718f_sio_write(u8 ldn, u8 index, u8 value) -{ - outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); -} - -static void it8718f_enter_conf(void) -{ - u16 port = 0x2e; /* TODO: Don't hardcode! */ - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8718f_exit_conf(void) -{ - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); -} - - /* * GIGABYTE uses a special Super I/O register to protect its Dual BIOS * mechanism. It lives in the GPIO LDN. However, register 0xEF is not * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ -void it8718f_disable_reboot(void) +void it8718f_disable_reboot(device_t dev) { - it8718f_enter_conf(); - it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); - it8718f_exit_conf(); + ite_reg_write(dev, 0xEF, 0x7E); } diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 018f08a..61c75cf 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -21,6 +21,8 @@ #ifndef SUPERIO_ITE_IT8718F_H #define SUPERIO_ITE_IT8718F_H +#include <arch/io.h> + /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */ #define IT8718F_FDC 0x00 /* Floppy */ @@ -33,8 +35,6 @@ #define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ -#if defined(__PRE_RAM__) -void it8718f_disable_reboot(void); -#endif +void it8718f_disable_reboot(device_t dev); #endif /* SUPERIO_ITE_IT8718F_H */

1 0

Patch merged into coreboot/master: f292002 superio/ite/*: Factor out generic romstage component
by gerrit＠coreboot.org 11 May '14

11 May '14

the following patch was just integrated into master: commit f29200240e428761827ab8d179fa23068bfa9d59 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 00:41:50 2014 +1000 superio/ite/*: Factor out generic romstage component Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5585 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek(a)assembler.cz> See http://review.coreboot.org/5585 for details. -gerrit

1 0

Patch set updated for coreboot: 54e0aed superio/ite/*: Factor out generic romstage component
by Edward O'Callaghan 11 May '14

11 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5585 -gerrit commit 54e0aed9b296393bd602a9d8425a1a08ae8c707b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 00:41:50 2014 +1000 superio/ite/*: Factor out generic romstage component Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dbm690t/romstage.c | 8 ++- src/mainboard/amd/mahogany/romstage.c | 7 +- src/mainboard/amd/mahogany_fam10/romstage.c | 7 +- src/mainboard/amd/tilapia_fam10/romstage.c | 7 +- src/mainboard/asus/a8n_e/romstage.c | 10 +-- src/mainboard/asus/f2a85-m/romstage.c | 7 +- src/mainboard/asus/m2n-e/romstage.c | 5 +- src/mainboard/asus/m2v-mx_se/romstage.c | 5 +- src/mainboard/asus/m2v/romstage.c | 12 ++-- src/mainboard/asus/m4a78-em/romstage.c | 7 +- src/mainboard/asus/m4a785-m/romstage.c | 7 +- src/mainboard/asus/m5a88-v/romstage.c | 3 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 10 ++- src/mainboard/gigabyte/ga-6bxc/romstage.c | 3 +- src/mainboard/gigabyte/ga-6bxe/romstage.c | 3 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 5 +- src/mainboard/gigabyte/m57sli/romstage.c | 5 +- src/mainboard/gigabyte/ma785gm/romstage.c | 7 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 7 +- src/mainboard/gigabyte/ma78gm/romstage.c | 7 +- src/mainboard/lippert/hurricane-lx/romstage.c | 16 ++--- src/mainboard/lippert/literunner-lx/romstage.c | 16 ++--- src/mainboard/lippert/roadrunner-lx/romstage.c | 16 ++--- src/mainboard/lippert/spacerunner-lx/romstage.c | 16 ++--- src/mainboard/siemens/sitemp_g1p1/romstage.c | 8 ++- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 3 +- src/mainboard/technexion/tim5690/romstage.c | 8 ++- src/mainboard/technexion/tim8690/romstage.c | 8 ++- src/mainboard/via/pc2500e/romstage.c | 3 +- src/superio/ite/Kconfig | 22 +++++++ src/superio/ite/Makefile.inc | 3 + src/superio/ite/common/early_serial.c | 86 +++++++++++++++++++++++++ src/superio/ite/common/ite.h | 36 +++++++++++ src/superio/ite/it8671f/Makefile.inc | 2 +- src/superio/ite/it8671f/early_serial.c | 4 +- src/superio/ite/it8671f/it8671f.h | 12 +++- src/superio/ite/it8712f/Makefile.inc | 2 +- src/superio/ite/it8712f/early_serial.c | 38 +---------- src/superio/ite/it8712f/it8712f.h | 9 ++- src/superio/ite/it8716f/Makefile.inc | 1 - src/superio/ite/it8716f/early_serial.c | 79 ----------------------- src/superio/ite/it8716f/it8716f.h | 7 -- src/superio/ite/it8718f/Makefile.inc | 2 +- src/superio/ite/it8718f/early_serial.c | 35 ---------- src/superio/ite/it8718f/it8718f.h | 8 +-- src/superio/ite/it8721f/Makefile.inc | 1 - src/superio/ite/it8721f/early_serial.c | 85 ------------------------ src/superio/ite/it8721f/it8721f.h | 6 -- src/superio/ite/it8728f/Makefile.inc | 1 - src/superio/ite/it8728f/early_serial.c | 74 --------------------- src/superio/ite/it8728f/it8728f.h | 12 ---- 51 files changed, 306 insertions(+), 445 deletions(-) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 7a0c8f9..c9a04f5 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -30,7 +30,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -38,6 +39,8 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 93870c5..00223ae 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -31,7 +31,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -39,6 +40,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -81,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 06deb18..278a3bd 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include <spd.h> +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 30e56d4..6e28cbd 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 29f425a..c0fa6a5 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -21,8 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Used by it8712f_enable_serial(). */ +/* Used by ite_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) #include <stdint.h> #include <string.h> @@ -33,7 +34,8 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -103,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 4aa4b04..487f068 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -36,16 +36,19 @@ #include <southbridge/amd/agesa/hudson/smbus.h> #include <stdint.h> #include <string.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> /* TODO: remove .c includes */ #include <drivers/pc80/i8254.c> #include <drivers/pc80/i8259.c> -#include <superio/ite/it8712f/early_serial.c> #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void sbxxx_enable_48mhzout(void) { /* most likely programming to 48MHz out signal */ @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* enable SIO clock */ sbxxx_enable_48mhzout(); it8712f_kill_watchdog(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_enable_3vsbsw(); console_init(); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 6892b28..d12b77c 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,6 +37,7 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -104,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); report_bist_failure(bist); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..0085bb4 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); console_init(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..acf8f91 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -46,6 +47,7 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define IT8712F_GPIO_BASE 0x0a20 @@ -163,15 +165,13 @@ static void m2v_it8712f_gpio_init(void) * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable */ - it8712f_enter_conf(); giv = gpio_init_data; while (giv->addr) { printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n", giv->addr, giv->val); - it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val); + ite_reg_write(IT8712F_GPIO, giv->addr, giv->val); giv++; } - it8712f_exit_conf(); printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n"); /* @@ -225,8 +225,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 18c6f18..93810d2 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 660ab0f..b360636 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 94a1e4e..9fca93f 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -41,6 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -100,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb800_clk_output_48Mhz(); - it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 1ebdedd..c014c57 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -30,13 +30,17 @@ #include "northbridge/intel/i82810/raminit.h" #include "drivers/pc80/udelay_io.c" #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <lib.h> +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) + void main(unsigned long bist) { - it8712f_24mhz_clkin(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 89761c9..1b2e29b 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -30,8 +30,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -void it8671f_48mhz_clkin(void); -#include "superio/ite/it8671f/early_serial.c" +#include <superio/ite/it8671f/it8671f.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 85a899a..c3926f0 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -30,8 +30,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -static void it8671f_48mhz_clkin(void); -#include "superio/ite/it8671f/early_serial.c" +#include <superio/ite/it8671f/it8671f.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 86158c8..10bbb6f 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,6 +38,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -125,8 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 44dda27..b2e1d70 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -35,6 +35,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -133,8 +134,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); #endif - it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index ecee35b..451cb79 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -37,7 +37,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -45,6 +46,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); console_init(); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index ecee35b..451cb79 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -37,7 +37,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -45,6 +46,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); console_init(); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bd9011e..bfc50b6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); console_init(); diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 95ea27d..063721b 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -35,9 +35,13 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 @@ -77,7 +81,6 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -101,13 +104,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -126,7 +126,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6edcf37..174620a 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -35,9 +35,13 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ #if CONFIG_ONBOARD_IDE_SLAVE #define SMC_CONFIG 0x03 @@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -143,13 +146,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -169,7 +169,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 68dcfc0..2642373 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -35,9 +35,13 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -53,7 +57,6 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset 0x9072, // watchdog triggers PWROK, counts seconds @@ -76,13 +79,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -101,7 +101,7 @@ void main(unsigned long bist) * Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 59bd618..9d5539e 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -35,9 +35,13 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ #if CONFIG_ONBOARD_IDE_SLAVE #define SMC_CONFIG 0x03 @@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -140,13 +143,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -166,7 +166,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6ae4989..b8af354 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -35,7 +35,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" @@ -45,6 +46,8 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -103,8 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0) check_cmos(); // rebooting in case of corrupted cmos !!!!! #endif - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 632a311..551c060 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -30,8 +30,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -void it8671f_48mhz_clkin(void); -#include "superio/ite/it8671f/early_serial.c" +#include <superio/ite/it8671f/it8671f.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index e6483c0..35351b1 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -32,12 +32,15 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -85,8 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 2f3ad71..7455df2 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -32,12 +32,15 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index e374cf9..b270350 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,6 +32,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <spd.h> @@ -59,7 +60,7 @@ void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); smbus_fixup(&ctrl); diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index 4c0f927..8a5378d 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,24 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic ITE romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_ITE_COMMON_ROMSTAGE + bool config SUPERIO_ITE_IT8661F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8671F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8712F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8716F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL bool depends on SUPERIO_ITE_IT8716F default n + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8718F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8721F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8728F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8772F bool + select SUPERIO_ITE_COMMON_ROMSTAGE diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 2b71521..7e1c81b 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic ite pre-ram stage driver +romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += it8661f subdirs-y += it8671f subdirs-y += it8712f diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c new file mode 100644 index 0000000..35fb59d --- /dev/null +++ b/src/superio/ite/common/early_serial.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "ite.h" + +/* Global configuration registers. */ +#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + +/* Helper procedure */ +static void ite_sio_write(device_t dev, u8 reg, u8 value) +{ + pnp_set_logical_device(dev); + pnp_write_config(dev, reg, value); +} + +/* Enable configuration */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +/* Disable configuration */ +static void pnp_exit_conf_state(device_t dev) +{ + ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); +} + +void ite_reg_write(device_t dev, u8 reg, u8 value) +{ + pnp_enter_conf_state(dev); + ite_sio_write(dev, reg, value); + pnp_exit_conf_state(dev); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) + * and pass: CLKIN_DEV + * ITE_UART_CLK_PREDIVIDE_24 + * ITE_UART_CLK_PREDIVIDE_48 (default) + */ +void ite_conf_clkin(device_t dev, u8 predivide) +{ + ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void ite_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h new file mode 100644 index 0000000..f21381d --- /dev/null +++ b/src/superio/ite/common/ite.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_COMMON_ROMSTAGE_H +#define SUPERIO_ITE_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define ITE_UART_CLK_PREDIVIDE_24 0x01 + +void ite_conf_clkin(device_t dev, u8 predivide); +void ite_enable_serial(device_t dev, u16 iobase); + +/* Some boards need to init wdt+gpio's very early */ +void ite_reg_write(device_t dev, u8 reg, u8 value); + +#endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */ diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc index bb370ae..a9a4008 100644 --- a/src/superio/ite/it8671f/Makefile.inc +++ b/src/superio/ite/it8671f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c - diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index c2ba6e0..9f35b8a 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "it8671f.h" /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ @@ -87,7 +89,7 @@ void it8671f_48mhz_clkin(void) } /* Enable the serial port(s). */ -static void it8671f_enable_serial(device_t dev, u16 iobase) +void it8671f_enable_serial(device_t dev, u16 iobase) { it8671f_enter_conf(); diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index 52669f4..c3865ff 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -18,8 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8671F_IT8671F_H -#define SUPERIO_ITE_IT8671F_IT8671F_H +#ifndef SUPERIO_ITE_IT8671F_H +#define SUPERIO_ITE_IT8671F_H + +#include <arch/io.h> +#include <stdint.h> /* Datasheet: Not available online, got it from ITE per request. */ @@ -30,4 +33,7 @@ #define IT8671F_KBCK 0x05 /* PS/2 keyboard */ #define IT8671F_KBCM 0x06 /* PS/2 mouse */ -#endif +void it8671f_48mhz_clkin(void); +void it8671f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_ITE_IT8671F__H */ diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 3c8a512..ce75645 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c - diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..d678f3f 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "it8712f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ @@ -30,7 +32,6 @@ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ @@ -58,14 +59,6 @@ static void it8712f_exit_conf(void) it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } -/* Select 24MHz CLKIN (48MHz is the default). */ -void it8712f_24mhz_clkin(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); - it8712f_exit_conf(); -} - /* * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! * @@ -88,30 +81,3 @@ void it8712f_kill_watchdog(void) it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); it8712f_exit_conf(); } - -/* Enable the serial port(s). */ -void it8712f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8712f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 5ec6188..b40e473 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8712F_IT8712F_H -#define SUPERIO_ITE_IT8712F_IT8712F_H +#ifndef SUPERIO_ITE_IT8712F_H +#define SUPERIO_ITE_IT8712F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */ @@ -36,7 +36,6 @@ #define IT8712F_IR 0x0a /* Consumer IR */ void it8712f_kill_watchdog(void); -void it8712f_enable_serial(device_t dev, u16 iobase); -void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); -#endif + +#endif /* SUPERIO_ITE_IT8712F_H */ diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 6b3c0ce..a11c2ab 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c deleted file mode 100644 index 2085a8f..0000000 --- a/src/superio/ite/it8716f/early_serial.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "it8716f.h" - -/* Global configuration registers. */ -#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8716f_enter_conf(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8716f_exit_conf(device_t dev) -{ - pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); -} - -static void it8716f_reg_write(device_t dev, u8 index, u8 value) -{ - it8716f_enter_conf(dev); - pnp_write_config(dev, index, value); - it8716f_exit_conf(dev); -} - - -/* - * in romstage.c - * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) - * and pass: CLKIN_DEV - * IT8716F_UART_CLK_PREDIVIDE_24 - * IT8716F_UART_CLK_PREDIVIDE_48 (default) - */ -void it8716f_conf_clkin(device_t dev, u8 predivide) -{ - it8716f_reg_write(dev, IT8716F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); -} - - -/* Enable the serial port(s). */ -void it8716f_enable_serial(device_t dev, u16 iobase) -{ - it8716f_enter_conf(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - it8716f_exit_conf(dev); -} diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 37b8b65..bbf5708 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -21,7 +21,6 @@ #ifndef SUPERIO_ITE_IT8716F_H #define SUPERIO_ITE_IT8716F_H -#include <device/pnp.h> #include <stdint.h> /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ @@ -39,12 +38,6 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ -#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */ -#define IT8716F_UART_CLK_PREDIVIDE_24 0x01 - -void it8716f_conf_clkin(device_t dev, u8 predivide); -void it8716f_enable_serial(device_t dev, u16 iobase); - #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc index c433e3c..14e2822 100644 --- a/src/superio/ite/it8718f/Makefile.inc +++ b/src/superio/ite/it8718f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c - diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 308b67c..deef840 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -30,7 +30,6 @@ #define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ static void it8718f_sio_write(u8 ldn, u8 index, u8 value) @@ -56,13 +55,6 @@ static void it8718f_exit_conf(void) it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); } -/* Select 24MHz CLKIN (48MHz default). */ -void it8718f_24mhz_clkin(void) -{ - it8718f_enter_conf(); - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); - it8718f_exit_conf(); -} /* * GIGABYTE uses a special Super I/O register to protect its Dual BIOS @@ -75,30 +67,3 @@ void it8718f_disable_reboot(void) it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); it8718f_exit_conf(); } - -/* Enable the serial port(s). */ -void it8718f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8718f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8718f_exit_conf(); -} diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 527d1c2..018f08a 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8718F_IT8718F_H -#define SUPERIO_ITE_IT8718F_IT8718F_H +#ifndef SUPERIO_ITE_IT8718F_H +#define SUPERIO_ITE_IT8718F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */ @@ -34,9 +34,7 @@ #define IT8718F_IR 0x0a /* Consumer IR */ #if defined(__PRE_RAM__) -void it8718f_24mhz_clkin(void); void it8718f_disable_reboot(void); -void it8718f_enable_serial(device_t dev, u16 iobase); #endif -#endif +#endif /* SUPERIO_ITE_IT8718F_H */ diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc index ef616f4..4b1aa96 100644 --- a/src/superio/ite/it8721f/Makefile.inc +++ b/src/superio/ite/it8721f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8721F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c deleted file mode 100644 index df66222..0000000 --- a/src/superio/ite/it8721f/early_serial.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include <stdint.h> -#include "it8721f.h" - -/* Global configuration registers. */ -#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8721f_sio_write(device_t dev, u8 index, u8 value) -{ - pnp_set_logical_device(dev); - pnp_write_config(dev, index, value); -} - -static void it8721f_enter_conf(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8721f_exit_conf(device_t dev) -{ - it8721f_sio_write(dev, IT8721F_CONFIG_REG_CC, 0x02); -} - -static void it8721f_reg_write(device_t dev, u8 index, u8 value) -{ - it8721f_enter_conf(dev); - it8721f_sio_write(dev, index, value); - it8721f_exit_conf(dev); -} - - -/* - * in romstage.c - * #define CLKIN_DEV PNP_DEV(0x2e, IT8721F_GPIO) - * and pass: CLKIN_DEV - * IT8721F_UART_CLK_PREDIVIDE_24 - * IT8721F_UART_CLK_PREDIVIDE_48 (default) - */ -void it8721f_conf_clkin(device_t dev, u8 predivide) -{ - it8721f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); -} - - -/* Enable the serial port(s). */ -void it8721f_enable_serial(device_t dev, u16 iobase) -{ - it8721f_enter_conf(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - it8721f_exit_conf(dev); -} diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index 9d5a528..ce794cf 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -36,10 +36,4 @@ #define IT8721F_GPIO 0x07 /* GPIO */ #define IT8721F_IR 0x0a /* Consumer IR */ -#define IT8721F_UART_CLK_PREDIVIDE_48 0x00 /* default */ -#define IT8721F_UART_CLK_PREDIVIDE_24 0x01 - -void it8721f_conf_clkin(device_t dev, u8 predivide); -void it8721f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_ITE_IT8721F_H */ diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc index a146db8..00cceeb 100644 --- a/src/superio/ite/it8728f/Makefile.inc +++ b/src/superio/ite/it8728f/Makefile.inc @@ -18,6 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += it8728f_hwm.c ramstage-$(CONFIG_SUPERIO_ITE_IT8728F) += superio.c diff --git a/src/superio/ite/it8728f/early_serial.c b/src/superio/ite/it8728f/early_serial.c deleted file mode 100644 index c2632ef..0000000 --- a/src/superio/ite/it8728f/early_serial.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2013 Damien Zammit <damien(a)zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "it8728f.h" - -/* Superio raw commands */ -static void it8728f_sio_write(device_t dev, u8 index, u8 value) -{ - pnp_set_logical_device(dev); - pnp_write_config(dev, index, value); -} - -static void it8728f_enter_conf(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8728f_exit_conf(device_t dev) -{ - it8728f_sio_write(dev, IT8728F_CONFIG_REG_CC, 0x02); -} - -/* Superio low level commands */ -void it8728f_reg_write(device_t dev, u8 index, u8 value) -{ - it8728f_enter_conf(dev); - it8728f_sio_write(dev, index, value); - it8728f_exit_conf(dev); -} - -void it8728f_24mhz_clkin(device_t dev) -{ - it8728f_reg_write(dev, IT8728F_CONFIG_REG_CLOCKSEL, 0x1); -} - -void it8728f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8728f_enter_conf(dev); - - /* (2) Modify the data of configuration registers. */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - - /* (3) Exit the configuration state (MB PnP mode). */ - it8728f_exit_conf(dev); -} diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 55bdf69..8a7e8b2 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -39,16 +39,4 @@ #define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */ -/* - * Superio low level commands - * Pass dev = PNP_DEV(superiobase, LDN) - */ -void it8728f_reg_write(device_t dev, u8 index, u8 value); - -/* Select 24MHz CLKIN (48MHz default). */ -void it8728f_24mhz_clkin(device_t dev); - -/* Enable the serial port(s). */ -void it8728f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_ITE_IT8728F_H */

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coreboot-gerrit May 2014