coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch set updated for coreboot: effdcb4 rambi: Move KBD_IRQ pin for Rambi 2.0 board
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5030 -gerrit commit effdcb4a64440a677a677d7b208f98707d089e96 Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Tue Jan 7 12:37:59 2014 -0800 rambi: Move KBD_IRQ pin for Rambi 2.0 board KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original SERIRQ function. Note that this change breaks Rambi 1.5 keyboard functionality. BUG=chrome-os-partner:24424 TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB interrupt toggling removed from EC code. BRANCH=Rambi, Glimmer, Clapper Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b Reviewed-on: https://chromium-review.googlesource.com/181757 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Randall Spangler <rspangler(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 4 ++-- src/mainboard/google/rambi/irqroute.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 235dc48..f1d9ef4 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -106,7 +106,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ - GPIO_DIRQ, /* S0-SC050 - IRQ_SERIRQ -- using for keyboard irq */ + GPIO_FUNC(1, PULL_UP, 10K), /* S0-SC050 - IRQ_SERIRQ */ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */ @@ -157,7 +157,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC098 - NC */ GPIO_NC, /* S0-SC099 - NC */ GPIO_NC, /* S0-SC100 - NC */ - GPIO_NC, /* S0-SC101 - NC*/ + GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */ GPIO_END }; diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index ddf6a76..3e1d1a9 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -53,4 +53,4 @@ /* Corresponding SCORE GPIO pins */ #define TPAD_IRQ_GPIO 55 #define TOUCH_IRQ_GPIO 72 -#define I8042_IRQ_GPIO 50 +#define I8042_IRQ_GPIO 101

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Patch set updated for coreboot: f15a86f rambi: Update the DPTF configuration
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5029 -gerrit commit f15a86f58746da8779d7ca88e7dfd91998996dbd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 6 12:35:36 2014 -0800 rambi: Update the DPTF configuration - Add passive thresholds for thermal participants - Disable the charger participant and remove from _TRT BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and start ESIF framework Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181663 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/acpi/dptf.asl | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/dptf.asl b/src/mainboard/google/rambi/acpi/dptf.asl index 0d5cd65..8dca454 100644 --- a/src/mainboard/google/rambi/acpi/dptf.asl +++ b/src/mainboard/google/rambi/acpi/dptf.asl @@ -1,11 +1,16 @@ #define DPTF_TSR0_SENSOR_ID 1 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" +#define DPTF_TSR0_PASSIVE 40 #define DPTF_TSR1_SENSOR_ID 2 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" +#define DPTF_TSR1_PASSIVE 45 #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" +#define DPTF_TSR2_PASSIVE 35 + +#undef DPTF_ENABLE_CHARGER Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ @@ -13,15 +18,12 @@ Name (DTRT, Package () { /* CPU and Charger Effect on Temp Sensor 0 */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 50, 0, 0, 0, 0 }, - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR0, 80, 300, 0, 0, 0, 0 }, /* CPU and Charger Effect on Temp Sensor 1 */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 50, 0, 0, 0, 0 }, - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 80, 300, 0, 0, 0, 0 }, /* CPU and Charger Effect on Temp Sensor 2 */ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 50, 0, 0, 0, 0 }, - Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 80, 300, 0, 0, 0, 0 }, }) /* Include Baytrail DPTF */

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Patch set updated for coreboot: efe7565 baytrail: Updates for DPTF ACPI framework
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5028 -gerrit commit efe7565c8331aec58d4618816323ae45e0e8c26c Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 6 12:33:59 2014 -0800 baytrail: Updates for DPTF ACPI framework - Remove some unused functions from CPU participant that were confusing the userland component since the CPU does not have an ACPI managed sensor. - Guard the charger participant with an ifdef so it can be left out if not supported. - Use the EC methods for setting auxiliary trip points and for handling the event when those trip points are crossed. - Add _NTT _DTI _SCP methods for thermal sensors. I'm not clear if these are required or not but they seem to be expected by the other DPTF framework components. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and load ESIF framework Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181662 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/acpi/dptf/cpu.asl | 54 ----------- src/soc/intel/baytrail/acpi/dptf/dptf.asl | 16 +++- src/soc/intel/baytrail/acpi/dptf/thermal.asl | 134 +++++++++++++++++++++++++++ 3 files changed, 146 insertions(+), 58 deletions(-) diff --git a/src/soc/intel/baytrail/acpi/dptf/cpu.asl b/src/soc/intel/baytrail/acpi/dptf/cpu.asl index 6e6c792..f82c348 100644 --- a/src/soc/intel/baytrail/acpi/dptf/cpu.asl +++ b/src/soc/intel/baytrail/acpi/dptf/cpu.asl @@ -9,7 +9,6 @@ Device (TCPU) { Name (_HID, EISAID ("INT3401")) Name (_UID, 0) - Name (CTYP, 0) /* Passive Cooling by default */ Method (_STA) { @@ -124,57 +123,4 @@ Device (TCPU) Return (0) } } - - /* - * DPTF - */ - - /* Convert from Degrees C to 1/10 Kelvin for ACPI */ - Method (CTOK, 1) { - /* 10th of Degrees C */ - Multiply (Arg0, 10, Local0) - - /* Convert to Kelvin */ - Add (Local0, 2732, Local0) - - Return (Local0) - } - - /* Critical temperature from NVS */ - Method (_CRT, 0, Serialized) - { - Return (CTOK (\TCRT)) - } - - /* Hot temperature is 3 less than critical temperature */ - Method (_HOT, 0, Serialized) - { - Return (CTOK (Subtract (\TCRT, 3))) - } - - Method (_PSV, 0, Serialized) - { - If (CTYP) { - Return (CTOK (\TACT)) - } Else { - Return (CTOK (\TPSV)) - } - } - - /* Set Cooling Policy - * Arg0 - Cooling policy mode, 1=active, 0=passive - * Arg1 - Acoustic Limit - * Arg2 - Power Limit - */ - Method (_SCP, 3, Serialized) - { - If (LEqual (Arg0, 0)) { - Store (0, CTYP) - } Else { - Store (1, CTYP) - } - - /* DPTF Thermal Trip Points Changed Event */ - Notify (TCPU, 0x91) - } } diff --git a/src/soc/intel/baytrail/acpi/dptf/dptf.asl b/src/soc/intel/baytrail/acpi/dptf/dptf.asl index b636886..6aebddc 100644 --- a/src/soc/intel/baytrail/acpi/dptf/dptf.asl +++ b/src/soc/intel/baytrail/acpi/dptf/dptf.asl @@ -8,7 +8,7 @@ Device (DPTF) /* DPPM Passive Policy 1.0 */ ToUUID("42A441D6-AE6A-462B-A84B-4A8CE79027D3"), - /* DPPM Critical Policy */ + /* DPPM Critical Policy */ ToUUID("97C68AE7-15FA-499c-B8C9-5DA81D606E0A"), /* DPPM Cooling Policy */ @@ -35,9 +35,15 @@ Device (DPTF) Return (\_SB.DTRT) } - /* Thermal Threshold Event Handler */ - Method (TEVT, 0, Serialized) - { + /* Convert from Degrees C to 1/10 Kelvin for ACPI */ + Method (CTOK, 1) { + /* 10th of Degrees C */ + Multiply (Arg0, 10, Local0) + + /* Convert to Kelvin */ + Add (Local0, 2732, Local0) + + Return (Local0) } /* Include CPU Participant */ @@ -46,6 +52,8 @@ Device (DPTF) /* Include Thermal Participants */ #include "thermal.asl" +#ifdef DPTF_ENABLE_CHARGER /* Include Charger Participant */ #include "charger.asl" +#endif } diff --git a/src/soc/intel/baytrail/acpi/dptf/thermal.asl b/src/soc/intel/baytrail/acpi/dptf/thermal.asl index 2a77e6a..33ec207 100644 --- a/src/soc/intel/baytrail/acpi/dptf/thermal.asl +++ b/src/soc/intel/baytrail/acpi/dptf/thermal.asl @@ -1,3 +1,20 @@ +/* Thermal Threshold Event Handler */ +Method (TEVT, 1, Serialized) +{ + Switch (ToInteger (Arg0)) + { +#ifdef DPTF_TSR0_SENSOR_ID + Case (DPTF_TSR0_SENSOR_ID) { Notify (^TSR0, 0x90) } +#endif +#ifdef DPTF_TSR1_SENSOR_ID + Case (DPTF_TSR1_SENSOR_ID) { Notify (^TSR1, 0x90) } +#endif +#ifdef DPTF_TSR2_SENSOR_ID + Case (DPTF_TSR2_SENSOR_ID) { Notify (^TSR2, 0x90) } +#endif + } +} + #ifdef DPTF_TSR0_SENSOR_ID Device (TSR0) { @@ -6,6 +23,10 @@ Device (TSR0) Name (PTYP, 0x03) Name (TMPI, DPTF_TSR0_SENSOR_ID) Name (_STR, Unicode (DPTF_TSR0_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + Name (NTTH, 5) /* 5 degree notification threshold */ + Name (LTM0, 0) /* Last recorded temperature */ + Name (CTYP, 0) /* Cooling policy */ Method (_STA) { @@ -21,6 +42,41 @@ Device (TSR0) Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) } + Method (_PSV) + { + Return (^^CTOK (DPTF_TSR0_PASSIVE)) + } + + /* Set Cooling Policy + * Arg0 - Cooling policy mode, 1=active, 0=passive + * Arg1 - Acoustic Limit + * Arg2 - Power Limit + */ + Method (_SCP, 3, Serialized) + { + If (LEqual (Arg0, 0)) { + Store (0, CTYP) + } Else { + Store (1, CTYP) + } + + /* DPTF Thermal Trip Points Changed Event */ + Notify (TSR0, 0x91) + } + + /* Device Temperature Indication */ + Method (_DTI, 1) + { + Store (Arg0, LTM0) + Notify (TSR0, 0x91) + } + + /* Notification Temperature Threshold */ + Method (_NTT) + { + Return (^^CTOK (NTTH)) + } + Name (PATC, 2) /* Set Aux Trip Point */ @@ -45,6 +101,10 @@ Device (TSR1) Name (PTYP, 0x03) Name (TMPI, DPTF_TSR1_SENSOR_ID) Name (_STR, Unicode (DPTF_TSR1_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + Name (NTTH, 5) /* 5 degree notification threshold */ + Name (LTM1, 0) + Name (CTYP, 0) /* Cooling policy */ Method (_STA) { @@ -60,6 +120,41 @@ Device (TSR1) Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) } + Method (_PSV) + { + Return (^^CTOK (DPTF_TSR1_PASSIVE)) + } + + /* Set Cooling Policy + * Arg0 - Cooling policy mode, 1=active, 0=passive + * Arg1 - Acoustic Limit + * Arg2 - Power Limit + */ + Method (_SCP, 3, Serialized) + { + If (LEqual (Arg0, 0)) { + Store (0, CTYP) + } Else { + Store (1, CTYP) + } + + /* DPTF Thermal Trip Points Changed Event */ + Notify (TSR1, 0x91) + } + + /* Device Temperature Indication */ + Method (_DTI, 1) + { + Store (Arg0, LTM1) + Notify (TSR1, 0x91) + } + + /* Notification Temperature Threshold */ + Method (_NTT) + { + Return (^^CTOK (NTTH)) + } + Name (PATC, 2) /* Set Aux Trip Point */ @@ -84,6 +179,10 @@ Device (TSR2) Name (PTYP, 0x03) Name (TMPI, DPTF_TSR2_SENSOR_ID) Name (_STR, Unicode (DPTF_TSR2_SENSOR_NAME)) + Name (GTSH, 20) /* 2 degree hysteresis */ + Name (NTTH, 5) /* 5 degree notification threshold */ + Name (LTM2, 0) + Name (CTYP, 0) /* Cooling policy */ Method (_STA) { @@ -99,6 +198,41 @@ Device (TSR2) Return (\_SB.PCI0.LPCB.EC0.TSRD (TMPI)) } + Method (_PSV) + { + Return (^^CTOK (DPTF_TSR2_PASSIVE)) + } + + /* Set Cooling Policy + * Arg0 - Cooling policy mode, 1=active, 0=passive + * Arg1 - Acoustic Limit + * Arg2 - Power Limit + */ + Method (_SCP, 3, Serialized) + { + If (LEqual (Arg0, 0)) { + Store (0, CTYP) + } Else { + Store (1, CTYP) + } + + /* DPTF Thermal Trip Points Changed Event */ + Notify (TSR2, 0x91) + } + + /* Device Temperature Indication */ + Method (_DTI, 1) + { + Store (Arg0, LTM2) + Notify (TSR2, 0x91) + } + + /* Notification Temperature Threshold */ + Method (_NTT) + { + Return (^^CTOK (NTTH)) + } + Name (PATC, 2) /* Set Aux Trip Point */

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Patch set updated for coreboot: d4a1786 baytrail: don't SMI on tco timer firing
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5035 -gerrit commit d4a17863b7e13b5505fae607c5e627b12ea56652 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 9 10:44:06 2014 -0600 baytrail: don't SMI on tco timer firing The SMI on TCO timer timeout policy was copied from other chipsets. However, it's not very advantageous to have the TCO timer timeout trigger an SMI unless the firmware was the one responsible for setting up the timer. BUG=chromium:321832 BRANCH=rambi,squawks TEST=Manually enabled TCO timer. TCO fires and logged in eventlog. Change-Id: I420b14d6aa778335a925784a64160fa885cba20f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181985 --- src/soc/intel/baytrail/smm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index 1fb35d7..d4b3d58 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -102,14 +102,14 @@ void southcluster_smm_enable_smi(void) southcluster_smm_route_gpios(); /* Enable SMI generation: - * - on TCO events * - on APMC writes (io 0xb2) * - on writes to SLP_EN (sleep states) * - on writes to GBL_RLS (bios commands) * No SMIs: + * - on TCO events * - on microcontroller writes (io 0x62/0x66) */ - enable_smi(TCO_EN | APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); + enable_smi(APMC_EN | SLP_SMI_EN | GBL_SMI_EN | EOS); } void smm_setup_structures(void *gnvs, void *tcg, void *smi1)

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Patch set updated for coreboot: a3b49b1 baytrail: clear the pmc wake status registers
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5034 -gerrit commit a3b49b188d3f4db6f3299b873620e82f96c0fe40 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 9 11:17:37 2014 -0600 baytrail: clear the pmc wake status registers The PMC in baytrail maintains an additional set wake status in memory-mapped registers. If these bits aren't cleared the device won't be able to go to S5 or S3 without being immediately woken up. Therefore clear these registers. BUG=chrome-os-partner:24913 BRANCH=rambi,squawks TEST=Ensured PRSTS bit 4 is cleared after a reboot and S3 and S5 work correctly. Change-Id: I356e00ece851961135b4760cebcdd34e8b9da027 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181984 --- src/soc/intel/baytrail/baytrail/pmc.h | 1 + src/soc/intel/baytrail/pmutil.c | 14 ++++++++++++++ src/soc/intel/baytrail/smm.c | 1 + 3 files changed, 16 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index 5013db8..ccbeed8 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -270,6 +270,7 @@ uint16_t clear_pm1_status(void); uint32_t clear_tco_status(void); uint32_t clear_gpe_status(void); uint32_t clear_alt_status(void); +void clear_pmc_status(void); void enable_smi(uint32_t mask); void disable_smi(uint32_t mask); void enable_pm1(uint16_t events); diff --git a/src/soc/intel/baytrail/pmutil.c b/src/soc/intel/baytrail/pmutil.c index ad37511..5d37a13 100644 --- a/src/soc/intel/baytrail/pmutil.c +++ b/src/soc/intel/baytrail/pmutil.c @@ -21,6 +21,7 @@ #include <arch/io.h> #include <console/console.h> +#include <baytrail/iomap.h> #include <baytrail/lpc.h> #include <baytrail/pci_devs.h> #include <baytrail/pmc.h> @@ -348,3 +349,16 @@ uint32_t clear_alt_status(void) { return print_alt_sts(reset_alt_status()); } + +void clear_pmc_status(void) +{ + uint32_t prsts; + uint32_t gen_pmcon1; + + prsts = read32(PMC_BASE_ADDRESS + PRSTS); + gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + + /* Clear the status bits. */ + write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1); + write32(PMC_BASE_ADDRESS + PRSTS, prsts); +} diff --git a/src/soc/intel/baytrail/smm.c b/src/soc/intel/baytrail/smm.c index e10c70b..1fb35d7 100644 --- a/src/soc/intel/baytrail/smm.c +++ b/src/soc/intel/baytrail/smm.c @@ -62,6 +62,7 @@ void southcluster_smm_clear_state(void) clear_tco_status(); clear_gpe_status(); clear_alt_status(); + clear_pmc_status(); } static void southcluster_smm_route_gpios(void)

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Patch set updated for coreboot: 9ea3f1b baytrail: log reset, power, and wake events in elog
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5033 -gerrit commit 9ea3f1b6a5e7fa34079f6ed5c8d909158cc6fbae Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 9 10:41:30 2014 -0600 baytrail: log reset, power, and wake events in elog When CONFIG_ELOG is selected the reset, power, and wake events are logged in the eventlog. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Various resets and wake sources. Interrogated eventlog to ensure results are expected. Change-Id: Ia68548562917be6c2a0d8d405a5b519102b8c563 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181983 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/elog.c | 118 ++++++++++++++++++++++++++++++++++++ 2 files changed, 119 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index aff09be..974d33d 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += sd.c ramstage-y += perf_power.c ramstage-y += stage_cache.c romstage-y += stage_cache.c +ramstage-$(CONFIG_ELOG) += elog.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c new file mode 100644 index 0000000..8c6be9f --- /dev/null +++ b/src/soc/intel/baytrail/elog.c @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/acpi.h> +#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <elog.h> +#include <baytrail/iomap.h> +#include <baytrail/pmc.h> + +static void log_power_and_resets(const struct chipset_power_state *ps) +{ + if (ps->gen_pmcon1 & PWR_FLR) { + elog_add_event(ELOG_TYPE_POWER_FAIL); + elog_add_event(ELOG_TYPE_PWROK_FAIL); + } + + if (ps->gen_pmcon1 & SUS_PWR_FLR) { + elog_add_event(ELOG_TYPE_SUS_POWER_FAIL); + } + + if (ps->tco_sts & SECOND_TO_STS) { + elog_add_event(ELOG_TYPE_TCO_RESET); + } + + if (ps->pm1_sts & PRBTNOR_STS) { + elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE); + } + + if (ps->gen_pmcon1 & SRS) { + elog_add_event(ELOG_TYPE_RESET_BUTTON); + } + + if (ps->gen_pmcon1 & GEN_RST_STS) { + elog_add_event(ELOG_TYPE_SYSTEM_RESET); + } +} + +static void log_wake_events(const struct chipset_power_state *ps) +{ + const uint32_t pcie_wake_mask = PCI_EXP_STS | PCIE_WAKE3_STS | + PCIE_WAKE2_STS | PCIE_WAKE1_STS | + PCIE_WAKE0_STS; + uint32_t gpe0_sts; + uint32_t gpio_mask; + int i; + + /* Mask off disabled events. */ + gpe0_sts = ps->gpe0_sts & ps->gpe0_en; + + if (ps->pm1_sts & WAK_STS) { + elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, + acpi_slp_type == 3 ? 3 : 5); + } + + if (ps->pm1_sts & PWRBTN_STS) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PWRBTN, 0); + } + + if (ps->pm1_sts & RTC_STS) { + elog_add_event_wake(ELOG_WAKE_SOURCE_RTC, 0); + } + + if (gpe0_sts & PME_B0_EN) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); + } + + if (gpe0_sts & pcie_wake_mask) { + elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); + } + + gpio_mask = SUS_GPIO_STS0; + i = 0; + while (gpio_mask) { + if (gpio_mask & gpe0_sts) { + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + } + gpio_mask <<= 1; + i++; + } +} + +void southcluster_log_state(void) +{ + struct chipset_power_state *ps = cbmem_find(CBMEM_ID_POWER_STATE); + + if (ps == NULL) { + printk(BIOS_DEBUG, "Not logging power state information. " + "Power state not found in cbmem.\n"); + return; + } + + log_power_and_resets(ps); + log_wake_events(ps); +}

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Patch set updated for coreboot: 45e117b Rambi: Enable 32k SUSCLK signal
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5019 -gerrit commit 45e117b05c05f36d8f5ceb0109874f8dec43766c Author: Bernie Thompson <bhthompson(a)chromium.org> Date: Fri Dec 13 15:30:57 2013 -0800 Rambi: Enable 32k SUSCLK signal The SoC needs to provide a 32k clock signal SUSCLK for some modems to work properly, so this enables the signal. BUG=chrome-os-partner:24425 TEST=Manual, check SUSCLK pin with a scope. Change-Id: I81fcc5a1fd27f4e1261fc761ea6eb017649acfa2 Reviewed-on: https://chromium-review.googlesource.com/180101 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Bernie Thompson <bhthompson(a)chromium.org> Tested-by: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index bbccaa9..235dc48 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -168,7 +168,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */

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Patch set updated for coreboot: 2737627 baytrail: snapshot power state in romstage
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5032 -gerrit commit 27376276e30956c7bb77f5d0ad35615c2182bfc2 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jan 9 10:33:23 2014 -0600 baytrail: snapshot power state in romstage The memory reference code doesn't maintain some of the registers which contain valuable information in order to log correct reset and wake events in the eventlog. Therefore snapshot the registers which matter in this area so that they can be consumed by ramstage. BUG=chrome-os-partner:24907 BRANCH=rambi,squawks TEST=Did various resets/wakes with logging patch which consumes this structure. Eventlog can pick up reset events and power failures. Change-Id: Id8d2d782dd4e1133113f5308c4ccfe79bc6d3e03 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181982 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + src/soc/intel/baytrail/baytrail/pmc.h | 66 +++++++++++++++++++++++++- src/soc/intel/baytrail/romstage/romstage.c | 76 +++++++++++++++++++++--------- 4 files changed, 121 insertions(+), 23 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index f103b30..beb626b 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -61,6 +61,7 @@ #define CBMEM_ID_EHCI_DEBUG 0xe4c1deb9 #define CBMEM_ID_REFCODE 0x04efc0de #define CBMEM_ID_REFCODE_CACHE 0x4efc0de5 +#define CBMEM_ID_POWER_STATE 0x50535454 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee #define CBMEM_ID_RAM_OOPS 0x05430095 #define CBMEM_ID_NONE 0x00000000 diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 42348e4..49724d6 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -52,6 +52,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_REFCODE, "REFCODE " }, { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, + { CBMEM_ID_POWER_STATE, "POWER STATE" }, { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, }; diff --git a/src/soc/intel/baytrail/baytrail/pmc.h b/src/soc/intel/baytrail/baytrail/pmc.h index ab2e169..5013db8 100644 --- a/src/soc/intel/baytrail/baytrail/pmc.h +++ b/src/soc/intel/baytrail/baytrail/pmc.h @@ -24,11 +24,51 @@ #define IOCOM1 0x3f8 /* Memory mapped IO registers behind PMC_BASE_ADDRESS */ +#define PRSTS 0x00 +# define PMC_WDT_STS (1 << 15) +# define SEC_GBLRST_STS (1 << 7) +# define SEC_WDT_STS (1 << 6) +# define WOL_OVR_WK_STS (1 << 5) +# define PMC_WAKE_STS (1 << 4) +#define PMC_CFG 0x08 +# define SPS (1 << 5) +# define NO_REBOOT (1 << 4) +# define SX_ENT_TO_EN (1 << 3) +# define TIMING_T581_SHIFT (0) +# define TIMING_T581_MASK (3 << TIMING_T581_SHIFT) +# define TIMING_T581_10uS (0 << TIMING_T581_SHIFT) +# define TIMING_T581_100uS (1 << TIMING_T581_SHIFT) +# define TIMING_T581_1mS (2 << TIMING_T581_SHIFT) +# define TIMING_T581_10mS (3 << TIMING_T581_SHIFT) +#define VLV_PM_STS 0x0c +# define PMC_MSG_FULL_STS (1 << 24) +# define PMC_MSG_4_FULL_STS (1 << 23) +# define PMC_MSG_3_FULL_STS (1 << 22) +# define PMC_MSG_2_FULL_STS (1 << 21) +# define PMC_MSG_1_FULL_STS (1 << 20) +# define CODE_REQ (1 << 8) +# define HPR_ENT_TO (1 << 2) +# define SX_ENT_TO (1 << 1) #define GEN_PMCON1 0x20 -# define AFTERG3_EN (1 << 0) # define UART_EN (1 << 24) +# define DISB (1 << 23) +# define MEM_SR (1 << 21) +# define SRS (1 << 20) +# define CTS (1 << 19) +# define MS4V (1 << 18) # define PWR_FLR (1 << 16) +# define PME_B0_S5_DIS (1 << 15) # define SUS_PWR_FLR (1 << 14) +# define WOL_EN_OVRD (1 << 13) +# define DIS_SLP_X_STRCH_SUS_UP (1 << 12) +# define GEN_RST_STS (1 << 9) +# define RPS (1 << 2) +# define AFTERG3_EN (1 << 0) +#define GEN_PMCON2 0x24 +# define SLPSX_STR_POL_LOCK (1 << 18) +# define BIOS_PCI_EXP_EN (1 << 10) +# define PWRBTN_LVL (1 << 9) +# define SMI_LOCK (1 << 4) #define ETR 0x48 # define CF9LOCK (1 << 31) # define LTR_DEF (1 << 22) @@ -84,6 +124,14 @@ # define CLK_CTL_D3_LPE (0x0 << 0) # define CLK_CTL_ON (0x1 << 0) # define CLK_CTL_OFF (0x2 << 0) +#define PME_STS 0xc0 +#define GPE_LEVEL_EDGE 0xc4 +# define GPE_EDGE 0 +# define GPE_LEVEL 1 +#define GPE_POLARITY 0xc8 +# define GPE_ACTIVE_HIGH 1 +# define GPE_ACTIVE_LOW 0 +#define LOCK 0xcc /* IO Mapped registers behind ACPI_BASE_ADDRESS */ #define PM1_STS 0x00 @@ -202,6 +250,18 @@ # define RST_CPU (1 << 2) # define SYS_RST (1 << 1) +/* Track power state from reset to log events. */ +struct chipset_power_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t pm1_cnt; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint32_t tco_sts; + uint32_t prsts; + uint32_t gen_pmcon1; + uint32_t gen_pmcon2; +} __attribute__((packed)); /* Power Management Utility Functions. */ uint16_t get_pmbase(void); @@ -219,6 +279,10 @@ void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +#if CONFIG_ELOG +void southcluster_log_state(void); +#else static inline void southcluster_log_state(void) {} +#endif #endif /* _BAYTRAIL_PMC_H_ */ diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index cb884bd..baa62a5 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -22,6 +22,7 @@ #include <arch/io.h> #include <arch/cbfs.h> #include <arch/stages.h> +#include <arch/early_variables.h> #include <console/console.h> #include <cbmem.h> #include <cpu/x86/mtrr.h> @@ -151,20 +152,56 @@ void * asmlinkage romstage_main(unsigned long bist, return setup_stack_and_mttrs(); } +static struct chipset_power_state power_state CAR_GLOBAL; + +static void migrate_power_state(void) +{ + struct chipset_power_state *ps_cbmem; + struct chipset_power_state *ps_car; + + ps_car = car_get_var_ptr(&power_state); + ps_cbmem = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*ps_cbmem)); + + if (ps_cbmem == NULL) { + printk(BIOS_DEBUG, "Not adding power state to cbmem!\n"); + return; + } + memcpy(ps_cbmem, ps_car, sizeof(*ps_cbmem)); +} +CAR_MIGRATE(migrate_power_state); + +static struct chipset_power_state *fill_power_state(void) +{ + struct chipset_power_state *ps = car_get_var_ptr(&power_state); + + ps->pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); + ps->pm1_en = inw(ACPI_BASE_ADDRESS + PM1_EN); + ps->pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); + ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS); + ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN); + ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS); + ps->prsts = read32(PMC_BASE_ADDRESS + PRSTS); + ps->gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); + ps->gen_pmcon2 = read32(PMC_BASE_ADDRESS + GEN_PMCON2); + + printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n", + ps->pm1_sts, ps->pm1_en, ps->pm1_cnt); + printk(BIOS_DEBUG, "gpe0_sts: %08x gpe0_en: %08x tco_sts: %08x\n", + ps->gpe0_sts, ps->gpe0_en, ps->tco_sts); + printk(BIOS_DEBUG, "prsts: %08x gen_pmcon1: %08x gen_pmcon2: %08x\n", + ps->prsts, ps->gen_pmcon1, ps->gen_pmcon2); + + return ps; +} + /* Return 0, 3, or 5 to indicate the previous sleep state. */ -static int chipset_prev_sleep_state(void) +static int chipset_prev_sleep_state(struct chipset_power_state *ps) { - uint16_t pm1_sts; - uint32_t pm1_cnt; - uint32_t gen_pmcon1; /* Default to S0. */ int prev_sleep_state = 0; - pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS); - pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT); - - if (pm1_sts & WAK_STS) { - switch ((pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { + if (ps->pm1_sts & WAK_STS) { + switch ((ps->pm1_cnt & SLP_TYP) >> SLP_TYP_SHIFT) { #if CONFIG_HAVE_ACPI_RESUME case SLP_TYP_S3: prev_sleep_state = 3; @@ -172,38 +209,32 @@ static int chipset_prev_sleep_state(void) #endif case SLP_TYP_S5: prev_sleep_state = 5; + break; } /* Clear SLP_TYP. */ - outl(pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); + outl(ps->pm1_cnt & ~(SLP_TYP), ACPI_BASE_ADDRESS + PM1_CNT); } - gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1); - if (gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { - /* Clear power failure bits. */ - write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1); + if (ps->gen_pmcon1 & (PWR_FLR | SUS_PWR_FLR)) { prev_sleep_state = 5; } - printk(BIOS_DEBUG, "pm1_sts = %04x pm1_cnt = %08x gen_pmcon1 = %08x\n", - pm1_sts, pm1_cnt, gen_pmcon1); - return prev_sleep_state; } -#if CONFIG_CHROMEOS static inline void chromeos_init(int prev_sleep_state) { +#if CONFIG_CHROMEOS /* Normalize the sleep state to what init_chromeos() wants for S3: 2. */ init_chromeos(prev_sleep_state == 3 ? 2 : 0); -} -#else -static inline void chromeos_init(int prev_sleep_state) {} #endif +} /* Entry from the mainboard. */ void romstage_common(struct romstage_params *params) { struct romstage_handoff *handoff; + struct chipset_power_state *ps; int prev_sleep_state; mark_ts(params, timestamp_get()); @@ -212,7 +243,8 @@ void romstage_common(struct romstage_params *params) boot_count_increment(); #endif - prev_sleep_state = chipset_prev_sleep_state(); + ps = fill_power_state(); + prev_sleep_state = chipset_prev_sleep_state(ps); printk(BIOS_DEBUG, "prev_sleep_state = S%d\n", prev_sleep_state);

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Patch set updated for coreboot: d23803d Rambi: Enable 32k SUSCLK signal
by Kyösti Mälkki 12 May '14

12 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5722 -gerrit commit d23803dcb4bf02b6cb5b5744d16695da529a299e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 12 23:16:18 2014 +0300 Rambi: Enable 32k SUSCLK signal The SoC needs to provide a 32k clock signal SUSCLK for some modems to work properly, so this enables the signal. BUG=chrome-os-partner:24425 TEST=Manual, check SUSCLK pin with a scope. Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c Reviewed-on: https://chromium-review.googlesource.com/180101 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Bernie Thompson <bhthompson(a)chromium.org> Tested-by: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/rambi/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index bbccaa9..235dc48 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -168,7 +168,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */

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New patch to review for coreboot: d83a328 Rambi: Enable 32k SUSCLK signal
by Kyösti Mälkki 12 May '14

12 May '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5722 -gerrit commit d83a3283873917c4ff923de77aa2ccc7569e3539 Author: Bernie Thompson <bhthompson(a)chromium.org> Date: Fri Dec 13 15:30:57 2013 -0800 Rambi: Enable 32k SUSCLK signal The SoC needs to provide a 32k clock signal SUSCLK for some modems to work properly, so this enables the signal. BUG=chrome-os-partner:24425 TEST=Manual, check SUSCLK pin with a scope. Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c Reviewed-on: https://chromium-review.googlesource.com/180101 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Bernie Thompson <bhthompson(a)chromium.org> Tested-by: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index bbccaa9..235dc48 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -168,7 +168,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */

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coreboot-gerrit May 2014