coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch set updated for coreboot: e040129 rambi: Make eMMC CLK pull-down and change pull strengths to 20K
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5026 -gerrit commit e040129f38e3d2344501d873c4a13e30e529f91a Author: Shawn Nematbakhsh <shawnn(a)chromium.org> Date: Fri Dec 20 13:27:56 2013 -0800 rambi: Make eMMC CLK pull-down and change pull strengths to 20K eMMC CLK was incorrectly configured as PULL_UP, but should have been PULL_DOWN. 2K pulls somehow masked this problem. BUG=chrome-os-partner:24353 TEST=Verify eMMC is bootable on Rambi on boards that previously failed with an all-20K, all-PU eMMC pin configuration. BRANCH=None Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6 Signed-off-by: Shawn Nematbakhsh <shawnn(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181034 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 3407bf3..235dc48 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -72,18 +72,17 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_NC, /* S0-SC013 - NC */ GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */ GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */ - /* TODO(shawnn): Investigate if these PUs can be weakened. */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC016 - MMC1_45_CLK */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC017 - MMC1_45_D[0] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC018 - MMC1_45_D[1] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC019 - MMC1_45_D[2] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC020 - MMC1_45_D[3] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC021 - MMC1_45_D[4] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC022 - MMC1_45_D[5] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC023 - MMC1_45_D[6] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC024 - MMC1_45_D[7] */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC025 - MMC1_45_CMD */ - GPIO_FUNC(3, PULL_UP, 2K), /* S0-SC026 - MMC1_45_RST */ + GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */ + GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */ GPIO_NC, /* S0-SC027 - NC */ GPIO_NC, /* S0-SC028 - NC */ GPIO_NC, /* S0-SC029 - NC */

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Patch set updated for coreboot: 598b005 baytrail: align with intel recommendations
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5025 -gerrit commit 598b0055ddb749e00df611ee4067c0cd974d4598 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Dec 18 14:37:31 2013 -0600 baytrail: align with intel recommendations The BISOC.EXIT_SELF_REFRESH_LATENCY field should not be updated from the default. BUG=chrome-os-partner:24345 BRANCH=None TEST=Built and booted. S3 resumed. Change-Id: I6e701a520513372318258648e998dd8c7ab29ea4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180730 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/perf_power.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index a577c6b..2cde77f 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -107,7 +107,6 @@ E(BUNIT, 0x11, MASK_VAL(31, 22, 0x20)), // BISOC.ENTER_SELF_REFRESH_THRSH E(BUNIT, 0x11, MASK_VAL(18, 18, 0x1)), // BISOC.SR_EXIT_SYNC_EN E(BUNIT, 0x11, MASK_VAL(17, 12, 0x4)), // BISOC.ENTER_SELF_REFRESH_DLY E(BUNIT, 0x11, MASK_VAL(11, 8, 0x8)), // BISOC.SCHEDULER_LATENCY -E(BUNIT, 0x11, MASK_VAL(6, 0, 0xC)), // BISOC.EXIT_SELF_REFRESH_LATENCY E(BUNIT, 0x12, MASK_VAL(31, 30, 0x0)), // BCOSCAT.COS_CAT_AGENT15 and BCOSCAT.BUS_LOCK_THROTTLE_ENABLE E(BUNIT, 0x12, MASK_VAL(29, 28, 0x0)), // BCOSCAT.COS_CAT_AGENT14 E(BUNIT, 0x12, MASK_VAL(27, 26, 0x0)), // BCOSCAT.COS_CAT_AGENT13

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Patch set updated for coreboot: 418af23 rambi: specify reference code index in vboot area
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5024 -gerrit commit 418af23be8ca84c1acee695580a1aec825ea24b4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 13 13:08:59 2013 -0800 rambi: specify reference code index in vboot area Rambi's reference code will live at slot 3 in the verified firmware section. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted. Verified correct area where reference code was loaded from. Change-Id: I8bee46600429ac8f732fe334852f69aff1324150 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180027 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/rambi/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/rambi/Kconfig b/src/mainboard/google/rambi/Kconfig index dc31541..f784aed 100644 --- a/src/mainboard/google/rambi/Kconfig +++ b/src/mainboard/google/rambi/Kconfig @@ -17,6 +17,10 @@ config VBOOT_RAMSTAGE_INDEX hex default 0x2 +config VBOOT_REFCODE_INDEX + hex + default 0x3 + config MAINBOARD_DIR string default google/rambi

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Patch set updated for coreboot: 957dae1 baytrail: Add header include wrapper and offset define
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5014 -gerrit commit 957dae114fcb689a29a8c0ce69fc61fa28cd6371 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 12 10:42:31 2013 -0800 baytrail: Add header include wrapper and offset define Since this file will get added to payloads it is useful if it exports what offset in NVS it lives. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi with emmc in ACPI mode Change-Id: I52860980c91dfe2525628e142b34ca192e69b258 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179848 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/baytrail/device_nvs.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/device_nvs.h b/src/soc/intel/baytrail/baytrail/device_nvs.h index dcb05d2..f8f831b 100644 --- a/src/soc/intel/baytrail/baytrail/device_nvs.h +++ b/src/soc/intel/baytrail/baytrail/device_nvs.h @@ -17,8 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef _BAYTRAIL_DEVICE_NVS_H_ +#define _BAYTRAIL_DEVICE_NVS_H_ + #include <stdint.h> +/* Offset in Global NVS where this structure lives */ +#define DEVICE_NVS_OFFSET 0x1000 + #define LPSS_NVS_SIO_DMA1 0 #define LPSS_NVS_I2C1 1 #define LPSS_NVS_I2C2 2 @@ -57,3 +63,5 @@ typedef struct { /* Extra */ u32 lpe_fw; /* LPE Firmware */ } __attribute__((packed)) device_nvs_t; + +#endif

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Patch set updated for coreboot: ac5d919 baytrail: Put devices in ACPI mode after setup
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5017 -gerrit commit ac5d9199850bf299e2a9e0ada339430b660761df Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 12 16:55:36 2013 -0800 baytrail: Put devices in ACPI mode after setup Make sure reg_script is executed before the device is put into ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot rambi from eMMC in ACPI mode Change-Id: I4090babbfc7fb0f3be4da869386e998d87a513ba Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179896 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/emmc.c | 5 +++-- src/soc/intel/baytrail/lpss.c | 3 +-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/baytrail/emmc.c b/src/soc/intel/baytrail/emmc.c index a724c4a..f88614b 100644 --- a/src/soc/intel/baytrail/emmc.c +++ b/src/soc/intel/baytrail/emmc.c @@ -53,10 +53,11 @@ static void emmc_init(device_t dev) { struct soc_intel_baytrail_config *config = dev->chip_info; - if (config->scc_acpi_mode) - scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); printk(BIOS_DEBUG, "eMMC init\n"); reg_script_run_on_dev(dev, emmc_ops); + + if (config->scc_acpi_mode) + scc_enable_acpi_mode(dev, SCC_MMC_CTL, SCC_NVS_MMC); } static struct device_operations device_ops = { diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index a543fd8..3ee648a 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -165,11 +165,10 @@ static void lpss_init(device_t dev) return; } dev_enable_snoop_and_pm(dev, iosf_reg); + i2c_disable_resets(dev); if (config->lpss_acpi_mode) dev_enable_acpi_mode(dev, iosf_reg, nvs_index); - - i2c_disable_resets(dev); } static struct device_operations device_ops = {

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Patch set updated for coreboot: 075fff6 rambi: Enable SCC devices in ACPI mode
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5018 -gerrit commit 075fff6b5a8da18d6c2f866c99c8b4a6ac8ba73e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Dec 12 15:51:52 2013 -0800 rambi: Enable SCC devices in ACPI mode With the ACPI GNVS exported and depthcharge changed to initialize eMMC in ACPI mode we can now put the SCC devices into ACPI mode. BUG=chrome-os-partner:24380 BRANCH=none TEST=build and boot on rambi, test eMMC and SD card Change-Id: I39716198f8227c0c3293ac23eb09660792e2c51b Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179901 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index bd54f00..bfb9e30 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -31,6 +31,9 @@ chip soc/intel/baytrail register "sdcard_cap_low" = "0x036864b2" register "sdcard_cap_high" = "0x0" + # Enable devices in ACPI mode + register "scc_acpi_mode" = "1" + # Enable PIPEA as DP_C register "gpu_pipea_hotplug" = "6" # 6ms Pulse register "gpu_pipea_port_select" = "2" # DP_C

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Patch set updated for coreboot: 23a9d09 Rambi: Enable 32k SUSCLK signal
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5019 -gerrit commit 23a9d0951a593cb07aee6f41e8b75acd520bac61 Author: Bernie Thompson <bhthompson(a)chromium.org> Date: Fri Dec 13 15:30:57 2013 -0800 Rambi: Enable 32k SUSCLK signal The SoC needs to provide a 32k clock signal SUSCLK for some modems to work properly, so this enables the signal. BUG=chrome-os-partner:24425 TEST=Manual, check SUSCLK pin with a scope. Change-Id: I81fcc5a1fd27f4e1261fc761ea6eb017649acfa2 Reviewed-on: https://chromium-review.googlesource.com/180101 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Commit-Queue: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Bernie Thompson <bhthompson(a)chromium.org> Tested-by: Bernie Thompson <bhthompson(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 6e6efe6..3407bf3 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -169,7 +169,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_FUNC6, /* S502 - TOUCH_INT# - INT */ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */ - GPIO_NC, /* S505 - SUS_CLK_WLAN (NC) */ + GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */

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Patch set updated for coreboot: 69b21ff rambi: Disable HSUART2 and SPI interfaces
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5020 -gerrit commit 69b21ffe6e4e5e9036e2200dd599c97e2a1a6a1b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Dec 13 16:01:56 2013 -0800 rambi: Disable HSUART2 and SPI interfaces Not used currently on rambi board. Disable in case it saves power. BUG=chrome-os-partner:23862 BRANCH=none TEST=build and boot on rambi Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180084 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rambi/devicetree.cb b/src/mainboard/google/rambi/devicetree.cb index bfb9e30..fe5ec7b 100644 --- a/src/mainboard/google/rambi/devicetree.cb +++ b/src/mainboard/google/rambi/devicetree.cb @@ -75,8 +75,8 @@ chip soc/intel/baytrail device pci 1e.1 off end # PWM1 device pci 1e.2 off end # PWM2 device pci 1e.3 off end # HSUART1 - device pci 1e.4 on end # HSUART2 - device pci 1e.5 on end # SPI + device pci 1e.4 off end # HSUART2 + device pci 1e.5 off end # SPI device pci 1f.0 on chip ec/google/chromeec # We only have one init function that

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Patch set updated for coreboot: 3082df6 baytrail: Expose IOSF as ACPI object
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5021 -gerrit commit 3082df6935c9b25b033b597d5f75d57a4cc81766 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Dec 13 16:43:11 2013 -0800 baytrail: Expose IOSF as ACPI object The kernel iosf driver uses HID INT33BD to probe and be provided the 12 bytes in PCI for access. BUG=chrome-os-partner:17279 BRANCH=none TEST=build and boot on rambi, load iosf_mbi driver and verify that it gets address 0xe00000d0 Change-Id: I865eafe664f00f21d1ebb967c291083830d895b9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180098 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/acpi/southcluster.asl | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index cf27a24..ced1618 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -228,6 +228,27 @@ Method (_OSC, 4) } } +/* IOSF MBI Interface for kernel access */ +Device (IOSF) +{ + Name (_HID, "INT33BD") + Name (_CID, "INT33BD") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + /* MCR / MDR / MCRX */ + Memory32Fixed (ReadWrite, 0, 12, RBAR) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^RBAR._BAS, RBAS) + Store (Add (MCFG_BASE_ADDRESS, 0xD0), RBAS) + Return (^RBUF) + } +} + // LPC Bridge 0:1f.0 #include "lpc.asl"

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Patch set updated for coreboot: 4b6afac baytrail: add way to load reference code from vboot area
by Aaron Durbin 12 May '14

12 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5023 -gerrit commit 4b6afac2d6d9ae2a13ff57e5b96575e735cfa94e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Dec 13 13:05:24 2013 -0800 baytrail: add way to load reference code from vboot area When employing vboot firmware verification the reference code loading should load from the verified firmware section. Add this ability. BUG=chrome-os-partner:22867 BRANCH=None TEST=Built and booted rambi. Noted firmware being loaded from rw verified area. Also noted S3 resume loading from cached area. Change-Id: I114de844f218b7573cf90107e174bf0962fdaa50 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180026 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/soc/intel/baytrail/refcode.c | 60 +++++++++++++++++++++++++++++++++------- 1 file changed, 50 insertions(+), 10 deletions(-) diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c index f746358..019e0a5 100644 --- a/src/soc/intel/baytrail/refcode.c +++ b/src/soc/intel/baytrail/refcode.c @@ -24,6 +24,7 @@ #include <cpu/x86/tsc.h> #include <rmodule.h> #include <ramstage_cache.h> +#include <vendorcode/google/chromeos/vboot_handoff.h> #include <baytrail/ramstage.h> #include <baytrail/efi_wrapper.h> @@ -105,20 +106,63 @@ static void cache_refcode(const struct rmod_stage_load *rsl) memcpy(&c->program[0], (void *)c->load_address, c->size); } -static efi_wrapper_entry_t load_refcode_from_cbfs(void) +static int load_refcode_from_vboot(struct rmod_stage_load *refcode, + struct cbfs_stage *stage) { + printk(BIOS_DEBUG, "refcode loading from vboot rw area.\n"); + + if (rmodule_stage_load(refcode, stage) || refcode->entry == NULL) { + printk(BIOS_DEBUG, "Error loading reference code.\n"); + return -1; + } + return 0; +} + +static int load_refcode_from_cbfs(struct rmod_stage_load *refcode) +{ + printk(BIOS_DEBUG, "refcode loading from cbfs.\n"); + + if (rmodule_stage_load_from_cbfs(refcode) || refcode->entry == NULL) { + printk(BIOS_DEBUG, "Error loading reference code.\n"); + return -1; + } + + return 0; +} + +static efi_wrapper_entry_t load_reference_code(void) +{ + struct vboot_handoff *vboot_handoff; + const struct firmware_component *fwc; struct rmod_stage_load refcode = { .cbmem_id = CBMEM_ID_REFCODE, .name = CONFIG_CBFS_PREFIX "/refcode", }; + int ret; - printk(BIOS_DEBUG, "refcode loading from cbfs.\n"); + if (is_s3_resume()) { + return load_refcode_from_cache(); + } - if (rmodule_stage_load_from_cbfs(&refcode) || refcode.entry == NULL) { - printk(BIOS_DEBUG, "Error loading reference code.\n"); - return NULL; + vboot_handoff = cbmem_find(CBMEM_ID_VBOOT_HANDOFF); + fwc = &vboot_handoff->components[CONFIG_VBOOT_REFCODE_INDEX]; + + if (vboot_handoff == NULL || + vboot_handoff->selected_firmware == VB_SELECT_FIRMWARE_READONLY || + CONFIG_VBOOT_REFCODE_INDEX >= MAX_PARSED_FW_COMPONENTS || + fwc->size == 0 || fwc->address == 0) { + ret = load_refcode_from_cbfs(&refcode); + } else { + ret = load_refcode_from_vboot(&refcode, (void *)fwc->address); + + if (ret < 0) + ret = load_refcode_from_cbfs(&refcode); } + if (ret < 0) + return NULL; + + /* Cache loaded reference code. */ cache_refcode(&refcode); return refcode.entry; @@ -133,11 +177,7 @@ void baytrail_run_reference_code(void) .console_out = send_to_console, }; - if (is_s3_resume()) { - entry = load_refcode_from_cache(); - } else { - entry = load_refcode_from_cbfs(); - } + entry = load_reference_code(); if (entry == NULL) return;

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coreboot-gerrit May 2014