coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch merged into coreboot/master: 946bee1 superio/ite/it8728f: RAMstage PNP configuration component
by gerrit＠coreboot.org 11 May '14

11 May '14

the following patch was just integrated into master: commit 946bee1c349db6bf88b4f6736dc910eb4890a74b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue May 6 18:00:07 2014 +1000 superio/ite/it8728f: RAMstage PNP configuration component Provide devicetree.cb RAMstage configuration of this superio component. Change-Id: I376d2fb6dafc301cbc437518012f8c43b0af4be2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5668 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek(a)assembler.cz> See http://review.coreboot.org/5668 for details. -gerrit

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Patch set updated for coreboot: d3f440d util/cbfstool: Make flat-binary Kconfig menu driven
by Edward O'Callaghan 11 May '14

11 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5716 -gerrit commit d3f440dd9b2963a0019e0e0f346616e62c946f0d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 11 08:45:39 2014 +1000 util/cbfstool: Make flat-binary Kconfig menu driven Make adding flat (non-segmented) binary payloads more user friendly. We have cbfstool support for this file type however do not expose it yet in the menu interface. Change-Id: I8c2994555fc80235848c46287df468d8725c5366 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 14 ++++++++++++++ src/Kconfig | 33 ++++++++++++++++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 3205a10..03b107a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -481,6 +481,16 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif +ifeq ($(CONFIG_PAYLOAD_FLATBIN),y) +FLATBIN_ADDITIONAL_CONFIG:= +ifneq ($(strip $(call strip_quotes,$(CONFIG_FLATBIN_LOAD_ADDR))),) + FLATBIN_ADDITIONAL_CONFIG+=-l $(CONFIG_FLATBIN_LOAD_ADDR) +endif +ifneq ($(strip $(call strip_quotes,$(CONFIG_FLATBIN_ENTRY_POINT))),) + FLATBIN_ADDITIONAL_CONFIG+=-e $(CONFIG_FLATBIN_ENTRY_POINT) +endif +endif + ifeq ($(CONFIG_PAYLOAD_LINUX),y) LINUX_ADDITIONAL_CONFIG:= ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),) @@ -508,6 +518,10 @@ ifeq ($(CONFIG_PAYLOAD_ELF),y) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif +ifeq ($(CONFIG_PAYLOAD_FLATBIN),y) + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-flat-binary -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(FLATBIN_ADDITIONAL_CONFIG) +endif ifeq ($(CONFIG_PAYLOAD_LINUX),y) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(LINUX_ADDITIONAL_CONFIG) diff --git a/src/Kconfig b/src/Kconfig index 30f996d..02dc77b 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -567,6 +567,16 @@ config PAYLOAD_ELF You will be able to specify the location and file name of the payload image later. +config PAYLOAD_FLATBIN + bool "A FLAT BIN executable payload" + help + Select this option if you have a payload image (a .bin file) + which coreboot should run as soon as the basic hardware + initialization is completed. + + You will be able to specify the load address, entry point address and + full file path of the payload image later. + config PAYLOAD_LINUX bool "A Linux payload" help @@ -686,6 +696,13 @@ config PAYLOAD_FILE The path and filename of the ELF executable file to use as payload. config PAYLOAD_FILE + string "Payload path and filename" + depends on PAYLOAD_FLATBIN + default "payload.bin" + help + The path and filename of the .bin executable file to use as payload. + +config PAYLOAD_FILE string "Linux path and filename" depends on PAYLOAD_LINUX default "bzImage" @@ -715,11 +732,25 @@ config PAYLOAD_FILE config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" default y - depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2 + depends on PAYLOAD_ELF || PAYLOAD_FLATBIN || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2 help In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. +config FLATBIN_LOAD_ADDR + string "Flat .bin Load Address" + depends on PAYLOAD_FLATBIN + default "" + help + The load address of the flat .bin binary + +config FLATBIN_ENTRY_POINT + string "Flat .bin Entry Point" + depends on PAYLOAD_FLATBIN + default "" + help + The entry point address of the flat .bin binary + config LINUX_COMMAND_LINE string "Linux command line" depends on PAYLOAD_LINUX

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Patch merged into coreboot/master: 31dbb53 SeaBIOS: Fix cpp use
by gerrit＠coreboot.org 11 May '14

11 May '14

the following patch was just integrated into master: commit 31dbb536fae937f9201312f2c47213c65ca9d939 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 10 14:21:38 2014 +0200 SeaBIOS: Fix cpp use No need to pass CPP down to SeaBIOS, it's not architecture specific and they define their own variable. Change-Id: I811aaf3929fa11cc01b7f168ccd310008e21e60c Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/5715 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5715 for details. -gerrit

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New patch to review for coreboot: 5328a11 util/cbfstool: Make flat-binary Kconfig menu driven
by Edward O'Callaghan 10 May '14

10 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5716 -gerrit commit 5328a11a6b19fedbc5bdf3a6bc26928de2f0ac5b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun May 11 08:45:39 2014 +1000 util/cbfstool: Make flat-binary Kconfig menu driven I like flowers... NOTFORMERGE yet Change-Id: I8c2994555fc80235848c46287df468d8725c5366 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- Makefile.inc | 14 ++++++++++++++ src/Kconfig | 33 ++++++++++++++++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 3205a10..03b107a 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -481,6 +481,16 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) mv $(obj)/coreboot.rom $@ endif +ifeq ($(CONFIG_PAYLOAD_FLATBIN),y) +FLATBIN_ADDITIONAL_CONFIG:= +ifneq ($(strip $(call strip_quotes,$(CONFIG_FLATBIN_LOAD_ADDR))),) + FLATBIN_ADDITIONAL_CONFIG+=-l $(CONFIG_FLATBIN_LOAD_ADDR) +endif +ifneq ($(strip $(call strip_quotes,$(CONFIG_FLATBIN_ENTRY_POINT))),) + FLATBIN_ADDITIONAL_CONFIG+=-e $(CONFIG_FLATBIN_ENTRY_POINT) +endif +endif + ifeq ($(CONFIG_PAYLOAD_LINUX),y) LINUX_ADDITIONAL_CONFIG:= ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),) @@ -508,6 +518,10 @@ ifeq ($(CONFIG_PAYLOAD_ELF),y) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) endif +ifeq ($(CONFIG_PAYLOAD_FLATBIN),y) + @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" + $(CBFSTOOL) $@.tmp add-flat-binary -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(FLATBIN_ADDITIONAL_CONFIG) +endif ifeq ($(CONFIG_PAYLOAD_LINUX),y) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(LINUX_ADDITIONAL_CONFIG) diff --git a/src/Kconfig b/src/Kconfig index 30f996d..892e202 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -567,6 +567,16 @@ config PAYLOAD_ELF You will be able to specify the location and file name of the payload image later. +config PAYLOAD_FLATBIN + bool "A FLAT BIN executable payload" + help + Select this option if you have a payload image (a .bin file) + which coreboot should run as soon as the basic hardware + initialization is completed. + + You will be able to specify the location and file name of the + payload image later. + config PAYLOAD_LINUX bool "A Linux payload" help @@ -686,6 +696,13 @@ config PAYLOAD_FILE The path and filename of the ELF executable file to use as payload. config PAYLOAD_FILE + string "Payload path and filename" + depends on PAYLOAD_FLATBIN + default "payload.bin" + help + The path and filename of the .bin executable file to use as payload. + +config PAYLOAD_FILE string "Linux path and filename" depends on PAYLOAD_LINUX default "bzImage" @@ -715,11 +732,25 @@ config PAYLOAD_FILE config COMPRESSED_PAYLOAD_LZMA bool "Use LZMA compression for payloads" default y - depends on PAYLOAD_ELF || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2 + depends on PAYLOAD_ELF || PAYLOAD_FLATBIN || PAYLOAD_SEABIOS || PAYLOAD_FILO || PAYLOAD_TIANOCORE || PAYLOAD_GRUB2 help In order to reduce the size payloads take up in the ROM chip coreboot can compress them using the LZMA algorithm. +config FLATBIN_LOAD_ADDR + string "Flat .bin Load Address" + depends on PAYLOAD_FLATBIN + default "" + help + The local address of the .bin binary + +config FLATBIN_ENTRY_POINT + string "Flat .bin Entry Point" + depends on PAYLOAD_FLATBIN + default "" + help + The entry point address of the .bin binary + config LINUX_COMMAND_LINE string "Linux command line" depends on PAYLOAD_LINUX

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Patch set updated for coreboot: 78508e0 cpu/intel: Add CPU socket rPGA988B
by Philipp Deppenwiese 10 May '14

10 May '14

Philipp Deppenwiese (zaolin(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5671 -gerrit commit 78508e099be271efdab8f724285e324c0591ebcb Author: Zaolin <zaolin(a)das-labor.org> Date: Tue May 6 21:30:54 2014 +0200 cpu/intel: Add CPU socket rPGA988B Used by the Lenovo ThinkPad T520 Change-Id: I1009616cc4c18ebd0e3be7ceb50398617b49e3a3 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/cpu/intel/Kconfig | 1 + src/cpu/intel/Makefile.inc | 1 + src/cpu/intel/socket_rPGA988B/Kconfig | 16 ++++++++++++++++ src/cpu/intel/socket_rPGA988B/Makefile.inc | 8 ++++++++ src/cpu/intel/socket_rPGA988B/socket_rPGA988B.c | 5 +++++ 5 files changed, 31 insertions(+) diff --git a/src/cpu/intel/Kconfig b/src/cpu/intel/Kconfig index af03619..fb4b023 100644 --- a/src/cpu/intel/Kconfig +++ b/src/cpu/intel/Kconfig @@ -34,6 +34,7 @@ source src/cpu/intel/socket_PGA370/Kconfig source src/cpu/intel/socket_441/Kconfig source src/cpu/intel/socket_LGA771/Kconfig source src/cpu/intel/socket_LGA775/Kconfig +source src/cpu/intel/socket_rPGA988B/Kconfig source src/cpu/intel/socket_rPGA989/Kconfig # Architecture specific features source src/cpu/intel/fit/Kconfig diff --git a/src/cpu/intel/Makefile.inc b/src/cpu/intel/Makefile.inc index 964369d..0392f69 100644 --- a/src/cpu/intel/Makefile.inc +++ b/src/cpu/intel/Makefile.inc @@ -14,6 +14,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA603) += socket_mPGA603 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604 subdirs-$(CONFIG_CPU_INTEL_SOCKET_PGA370) += socket_PGA370 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA988B) += socket_rPGA988B subdirs-$(CONFIG_CPU_INTEL_SOCKET_RPGA989) += socket_rPGA989 subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax diff --git a/src/cpu/intel/socket_rPGA988B/Kconfig b/src/cpu/intel/socket_rPGA988B/Kconfig new file mode 100644 index 0000000..7e74f89 --- /dev/null +++ b/src/cpu/intel/socket_rPGA988B/Kconfig @@ -0,0 +1,16 @@ +config CPU_INTEL_SOCKET_RPGA988B + bool + +if CPU_INTEL_SOCKET_RPGA988B + +config SOCKET_SPECIFIC_OPTIONS # dummy + def_bool y + select MMX + select SSE + select CACHE_AS_RAM + +config CACHE_MRC_BIN + bool + default n + +endif diff --git a/src/cpu/intel/socket_rPGA988B/Makefile.inc b/src/cpu/intel/socket_rPGA988B/Makefile.inc new file mode 100644 index 0000000..d8036d1 --- /dev/null +++ b/src/cpu/intel/socket_rPGA988B/Makefile.inc @@ -0,0 +1,8 @@ +ramstage-y += socket_rPGA988B.c +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode +subdirs-y += ../turbo diff --git a/src/cpu/intel/socket_rPGA988B/socket_rPGA988B.c b/src/cpu/intel/socket_rPGA988B/socket_rPGA988B.c new file mode 100644 index 0000000..9a18e61 --- /dev/null +++ b/src/cpu/intel/socket_rPGA988B/socket_rPGA988B.c @@ -0,0 +1,5 @@ +#include <device/device.h> + +struct chip_operations cpu_intel_socket_rPGA988B_ops = { + CHIP_NAME("Socket rPGA988B CPU") +};

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Patch set updated for coreboot: 2b83801 mainboard/lenovo: Add Lenovo Thinkpad T520 support
by Philipp Deppenwiese 10 May '14

10 May '14

Philipp Deppenwiese (zaolin(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5672 -gerrit commit 2b83801021a5564cc3bee8b28ebc924fe44816c5 Author: Zaolin <zaolin(a)das-labor.org> Date: Tue May 6 21:31:45 2014 +0200 mainboard/lenovo: Add Lenovo Thinkpad T520 support Short list of known issues for this patchset: * Suspend/Resume - does not work * Combi pci card for SD/MMC card reader with IEEE1394 - not found * Shutdown - sometimes does not work as expected * At least mysterious harddrive i/o Change-Id: Iaba8d1f5e471cfeca20d82f4e1b416641e1f2ae9 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/lenovo/Kconfig | 6 + src/mainboard/lenovo/t520/Kconfig | 83 ++++++ src/mainboard/lenovo/t520/Makefile.inc | 20 ++ src/mainboard/lenovo/t520/acpi/ec.asl | 26 ++ src/mainboard/lenovo/t520/acpi/gpe.asl | 13 + src/mainboard/lenovo/t520/acpi/platform.asl | 74 +++++ .../lenovo/t520/acpi/sandybridge_pci_irqs.asl | 65 +++++ src/mainboard/lenovo/t520/acpi/superio.asl | 1 + src/mainboard/lenovo/t520/acpi/video.asl | 115 ++++++++ src/mainboard/lenovo/t520/acpi_tables.c | 256 +++++++++++++++++ src/mainboard/lenovo/t520/board_info.txt | 6 + src/mainboard/lenovo/t520/cmos.default | 18 ++ src/mainboard/lenovo/t520/cmos.layout | 158 ++++++++++ src/mainboard/lenovo/t520/devicetree.cb | 139 +++++++++ src/mainboard/lenovo/t520/dsdt.asl | 60 ++++ src/mainboard/lenovo/t520/fadt.c | 160 +++++++++++ src/mainboard/lenovo/t520/hda_verb.h | 317 +++++++++++++++++++++ src/mainboard/lenovo/t520/mainboard.c | 194 +++++++++++++ src/mainboard/lenovo/t520/romstage.c | 295 +++++++++++++++++++ src/mainboard/lenovo/t520/smi.h | 20 ++ src/mainboard/lenovo/t520/smihandler.c | 169 +++++++++++ src/mainboard/lenovo/t520/thermal.h | 30 ++ 22 files changed, 2225 insertions(+) diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index 9410e90..c1dec85 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -22,6 +22,11 @@ config BOARD_LENOVO_X230 help Lenovo X230 laptop. Consult wiki for details. +config BOARD_LENOVO_T520 + bool "ThinkPad T520" + help + Lenovo T520 laptop. Consult wiki for details. + config BOARD_LENOVO_T530 bool "ThinkPad T530" help @@ -40,6 +45,7 @@ endchoice source "src/mainboard/lenovo/x60/Kconfig" source "src/mainboard/lenovo/x201/Kconfig" source "src/mainboard/lenovo/x230/Kconfig" +source "src/mainboard/lenovo/t520/Kconfig" source "src/mainboard/lenovo/t530/Kconfig" source "src/mainboard/lenovo/t60/Kconfig" diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig new file mode 100644 index 0000000..196d73d --- /dev/null +++ b/src/mainboard/lenovo/t520/Kconfig @@ -0,0 +1,83 @@ +if BOARD_LENOVO_T520 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_INTEL_SOCKET_RPGA988B + select NORTHBRIDGE_INTEL_SANDYBRIDGE + select SOUTHBRIDGE_INTEL_BD82X6X + select EC_LENOVO_PMH7 + select EC_LENOVO_H8 + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select HAVE_ACPI_RESUME + select HAVE_SMI_HANDLER + select GFXUMA + select EARLY_CBMEM_INIT + + # Workaround for EC/KBC IRQ1. + select SERIRQ_CONTINUOUS_MODE + +config HAVE_MRC_CACHE + bool + default n + +config HAVE_IFD_BIN + bool + default n + +config HAVE_ME_BIN + bool + default n + +config MAINBOARD_DIR + string + default lenovo/t520 + +config MAINBOARD_PART_NUMBER + string + default "XXXXXXX" + +config MMCONF_BASE_ADDRESS + hex + default 0xf0000000 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x800000 + +config IRQ_SLOT_COUNT + int + default 18 + +config MAX_CPUS + int + default 8 + +config USBDEBUG_HCD_INDEX + int + default 2 + +config DRAM_GATE_GPIO + int + default 10 + +config VGA_BIOS_FILE + string + default "pci8086,0126.rom" + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x17aa + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x21cf + +config MAINBOARD_VENDOR + string + default "LENOVO" + +endif # BOARD_LENOVO_T520 diff --git a/src/mainboard/lenovo/t520/Makefile.inc b/src/mainboard/lenovo/t520/Makefile.inc new file mode 100644 index 0000000..d514d4b --- /dev/null +++ b/src/mainboard/lenovo/t520/Makefile.inc @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c diff --git a/src/mainboard/lenovo/t520/acpi/ec.asl b/src/mainboard/lenovo/t520/acpi/ec.asl new file mode 100644 index 0000000..4b3e72c --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <ec/lenovo/h8/acpi/ec.asl> + +Scope(\_SB.PCI0.LPCB.EC) +{ +} diff --git a/src/mainboard/lenovo/t520/acpi/gpe.asl b/src/mainboard/lenovo/t520/acpi/gpe.asl new file mode 100644 index 0000000..eb489d5 --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/gpe.asl @@ -0,0 +1,13 @@ + Method (_L01, 0, NotSerialized) + { + If (\_SB.PCI0.RP03.HPCS) + { + Sleep (100) + Store (0x01, \_SB.PCI0.RP03.HPCS) + If (\_SB.PCI0.RP03.PDC) + { + Store (0x01, \_SB.PCI0.RP03.PDC) + Notify (\_SB.PCI0.RP03, 0x00) + } + } + } diff --git a/src/mainboard/lenovo/t520/acpi/platform.asl b/src/mainboard/lenovo/t520/acpi/platform.asl new file mode 100644 index 0000000..73478ea --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/platform.asl @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) // SMI Function + Store (0, TRP0) // Generate trap + Return (SMIF) // Return value of SMI handler +} + +/* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + +Method(_PIC, 1) +{ + // Remember the OS' IRQ routing choice. + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ + +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + /* Not implemented. */ + Return(Package(){0,0}) +} + diff --git a/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl new file mode 100644 index 0000000..ba725ac --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/sandybridge_pci_irqs.asl @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This is board specific information: IRQ routing for Sandybridge */ + +// PCI Interrupt Routing +Method(_PRT) +{ + If (PICM) { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB + Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF + Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF + // LPC devices 0:1f.0 + Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) + Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH + Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA + }) + } Else { + Return (Package() { + // Onboard graphics (IGD) 0:2.0 + Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // High Definition Audio 0:1b.0 + Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, + // PCIe Root Ports 0:1c.x + Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, + Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #1 0:1d.0 + Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, + // EHCI #2 0:1a.0 + Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, + // LPC device 0:1f.0 + Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, + Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, + Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, + }) + } +} + diff --git a/src/mainboard/lenovo/t520/acpi/superio.asl b/src/mainboard/lenovo/t520/acpi/superio.asl new file mode 100644 index 0000000..a2657f1 --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/superio.asl @@ -0,0 +1 @@ +#include "../../../../drivers/pc80/ps2_controller.asl" diff --git a/src/mainboard/lenovo/t520/acpi/video.asl b/src/mainboard/lenovo/t520/acpi/video.asl new file mode 100644 index 0000000..12a268b --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi/video.asl @@ -0,0 +1,115 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (c) 2011 Sven Schnelle <svens(a)stackframe.org> + * Copyright (c) 2013 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include "smi.h" + +Scope (\_SB.PCI0.GFX0) +{ + Device (LCD0) + { + Name (_ADR, 0x0400) + Name (BRCT, 0) + + Name (BRIG, Package (0x12) + { + 0x61, + 0x61, + 0x2, + 0x4, + 0x5, + 0x7, + 0x9, + 0xb, + 0xd, + 0x11, + 0x14, + 0x17, + 0x1c, + 0x20, + 0x27, + 0x31, + 0x41, + 0x61, + }) + + Method (_BCL, 0, NotSerialized) + { + Store (1, BRCT) + Return (BRIG) + } + + Method (_BCM, 1, NotSerialized) + { + Store (ShiftLeft (Arg0, 4), ^^BCLV) + Store (0x80000000, ^^CR1) + Store (0x061a061a, ^^CR2) + } + Method (_BQC, 0, NotSerialized) + { + Store (^^BCLV, Local0) + ShiftRight (Local0, 4, Local0) + Return (Local0) + } + + Method(BRID, 1, NotSerialized) + { + Store (Match (BRIG, MEQ, Arg0, MTR, Zero, 2), Local0) + If (LEqual (Local0, Ones)) + { + Return (0x11) + } + Return (Local0) + } + + /* Using Notify is the right way. But Windows doesn't handle + it well. So use both method in a way to avoid double action. + */ + Method (DECB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x87) + } Else { + Store (BRID (_BQC ()), Local0) + If (LNotEqual (Local0, 2)) + { + Decrement (Local0) + } + _BCM (DerefOf (Index (BRIG, Local0))) + } + } + Method (INCB, 0, NotSerialized) + { + If (BRCT) + { + Notify (LCD0, 0x86) + } Else { + Store (BRID (_BQC ()), Local0) + If (LNotEqual (Local0, 0x11)) + { + Increment (Local0) + } + _BCM (DerefOf (Index (BRIG, Local0))) + } + } + } +} diff --git a/src/mainboard/lenovo/t520/acpi_tables.c b/src/mainboard/lenovo/t520/acpi_tables.c new file mode 100644 index 0000000..6ee2df8 --- /dev/null +++ b/src/mainboard/lenovo/t520/acpi_tables.c @@ -0,0 +1,256 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <cbmem.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/ioapic.h> +#include <arch/acpigen.h> +#include <arch/smp/mpspec.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> + +extern const unsigned char AmlCode[]; +#if CONFIG_HAVE_ACPI_SLIC +unsigned long acpi_create_slic(unsigned long current); +#endif + +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include "thermal.h" + +static void acpi_update_thermal_table(global_nvs_t *gnvs) +{ + gnvs->tcrt = CRITICAL_TEMPERATURE; + gnvs->tpsv = PASSIVE_TEMPERATURE; +} + +static void acpi_create_gnvs(global_nvs_t *gnvs) +{ + memset((void *)gnvs, 0, sizeof(*gnvs)); + gnvs->apic = 1; + gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); + + /* Disable USB ports in S3 by default */ + gnvs->s3u0 = 0; + gnvs->s3u1 = 0; + + /* Disable USB ports in S5 by default */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* CBMEM TOC */ + gnvs->cmem = (u32)get_cbmem_toc(); + + /* IGD Displays */ + gnvs->ndid = 3; + gnvs->did[0] = 0x80000100; + gnvs->did[1] = 0x80000240; + gnvs->did[2] = 0x80000410; + gnvs->did[3] = 0x80000410; + gnvs->did[4] = 0x00000005; + + // the lid is open by default. + gnvs->lids = 1; + + acpi_update_thermal_table(gnvs); +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* Local APICs */ + current = acpi_create_madt_lapics(current); + + /* IOAPIC */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + 2, IO_APIC_ADDR, 0); + + /* INT_SRC_OVR */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id) +{ + generate_cpu_entries(); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long acpi_fill_slit(unsigned long current) +{ + // Not implemented + return current; +} + +unsigned long acpi_fill_srat(unsigned long current) +{ + /* No NUMA, no SRAT */ + return current; +} + +#define ALIGN_CURRENT current = (ALIGN(current, 16)) +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + int i; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_xsdt_t *xsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_mcfg_t *mcfg; + acpi_fadt_t *fadt; + acpi_facs_t *facs; +#if CONFIG_HAVE_ACPI_SLIC + acpi_header_t *slic; +#endif + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + current = start; + + /* Align ACPI tables to 16byte */ + ALIGN_CURRENT; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx.\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + ALIGN_CURRENT; + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + ALIGN_CURRENT; + xsdt = (acpi_xsdt_t *) current; + current += sizeof(acpi_xsdt_t); + ALIGN_CURRENT; + + /* clear all table memory */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, xsdt); + acpi_write_rsdt(rsdt); + acpi_write_xsdt(xsdt); + + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + ALIGN_CURRENT; + acpi_create_facs(facs); + + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + ALIGN_CURRENT; + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + /* + * We explicitly add these tables later on: + */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + ALIGN_CURRENT; + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + ALIGN_CURRENT; + acpi_add_table(rsdp, mcfg); + + /* Pack GNVS into the ACPI table area */ + for (i=0; i < dsdt->length; i++) { + if (*(u32*)(((u32)dsdt) + i) == 0xC0DEBABE) { + printk(BIOS_DEBUG, "ACPI: Patching up global NVS in " + "DSDT at offset 0x%04x -> 0x%08lx\n", i, current); + *(u32*)(((u32)dsdt) + i) = current; // 0x92 bytes + acpi_save_gnvs(current); + break; + } + } + + /* And fill it */ + acpi_create_gnvs((global_nvs_t *)current); + + /* And tell SMI about it */ + smm_setup_structures((void *)current, NULL, NULL); + + current += sizeof(global_nvs_t); + ALIGN_CURRENT; + + /* We patched up the DSDT, so we need to recalculate the checksum */ + dsdt->checksum = 0; + dsdt->checksum = acpi_checksum((void *)dsdt, dsdt->length); + + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + +#if CONFIG_HAVE_ACPI_SLIC + printk(BIOS_DEBUG, "ACPI: * SLIC\n"); + slic = (acpi_header_t *)current; + current += acpi_create_slic(current); + ALIGN_CURRENT; + acpi_add_table(rsdp, slic); +#endif + + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + ALIGN_CURRENT; + + printk(BIOS_DEBUG, "current = %lx\n", current); + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} diff --git a/src/mainboard/lenovo/t520/board_info.txt b/src/mainboard/lenovo/t520/board_info.txt new file mode 100644 index 0000000..8d44122 --- /dev/null +++ b/src/mainboard/lenovo/t520/board_info.txt @@ -0,0 +1,6 @@ +Category: laptop +Board name: T520 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default new file mode 100644 index 0000000..137f482 --- /dev/null +++ b/src/mainboard/lenovo/t520/cmos.default @@ -0,0 +1,18 @@ +boot_option=Fallback +last_boot=Fallback +baud_rate=115200 +debug_level=Spew +power_on_after_fail=Enable +nmi=Enable +volume=0x3 +first_battery=Primary +bluetooth=Enable +wwan=Enable +wlan=Enable +touchpad=Enable +sata_mode=AHCI +fn_ctrl_swap=Disable +sticky_fn=Disable +trackpoint=Enable +hyper_threading=Enable +backlight=Both \ No newline at end of file diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout new file mode 100644 index 0000000..6f8822f --- /dev/null +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -0,0 +1,158 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## Copyright (C) 2014 Vladimir Serbinenko +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +400 8 h 0 volume + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail + +# coreboot config options: EC +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +#419 2 r 0 unused +421 1 e 9 sata_mode +422 2 e 10 backlight + +# coreboot config options: cpu +424 1 e 2 hyper_threading + +#425 559 r 0 unused + +# SandyBridge MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 + + diff --git a/src/mainboard/lenovo/t520/devicetree.cb b/src/mainboard/lenovo/t520/devicetree.cb new file mode 100644 index 0000000..475e49c --- /dev/null +++ b/src/mainboard/lenovo/t520/devicetree.cb @@ -0,0 +1,139 @@ +chip northbridge/intel/sandybridge + + # Enable DisplayPort Hotplug with 6ms pulse + register "gpu_dp_d_hotplug" = "0x06" + + # Enable Panel as LVDS and configure power delays + register "gpu_panel_port_select" = "0" # LVDS + register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms + register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms + register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms + register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms + register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms + + device cpu_cluster 0 on + chip cpu/intel/socket_rPGA988B + device lapic 0 on end + end + chip cpu/intel/model_206ax + # Magic APIC ID to locate this chip + device lapic 0xACAC off end + + # Coordinate with HW_ALL + register "pstate_coord_type" = "0xfe" + + register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7) + + register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1) + register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3) + register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7) + end + end + + device domain 0 on + device pci 00.0 on end # host bridge + device pci 02.0 on end # vga controller + + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "pirqa_routing" = "0x8b" + register "pirqb_routing" = "0x8a" + register "pirqc_routing" = "0x8b" + register "pirqd_routing" = "0x8b" + register "pirqe_routing" = "0x80" + register "pirqf_routing" = "0x80" + register "pirqg_routing" = "0x80" + register "pirqh_routing" = "0x80" + + # GPI routing + # 0 No effect (default) + # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) + # 2 SCI (if corresponding GPIO_EN bit is also set) + register "alt_gp_smi_en" = "0x0000" + register "gpi1_routing" = "2" + register "gpi8_routing" = "2" + + # Enable SATA ports 0 + register "sata_port_map" = "0x1f" + # Set max SATA speed to 6.0 Gb/s + register "sata_interface_speed_support" = "0x3" + + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen4_dec" = "0x0c06a1" + + # Enable zero-based linear PCIe root port functions + register "pcie_port_coalesce" = "1" + + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end + device pci 16.2 off end + device pci 16.3 off end + device pci 19.0 on end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.1 on end # PCIe Port #2 Integrated Wireless LAN + device pci 1c.2 off end + device pci 1c.3 on end # PCIe Port #3 Express Card + device pci 1c.4 on end # PCIe Port #4 MMC/SDXC + IEEE1394 + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1f.0 on #LPC bridge + chip ec/lenovo/pmh7 + device pnp ff.1 on # dummy + end + register "backlight_enable" = "0x01" + register "dock_event_enable" = "0x01" + end + + chip ec/lenovo/h8 + device pnp ff.2 on # dummy + io 0x60 = 0x62 + io 0x62 = 0x66 + io 0x64 = 0x1600 + io 0x66 = 0x1604 + end + + register "config0" = "0xa7" + register "config1" = "0x09" + register "config2" = "0xa0" + register "config3" = "0xc2" + + register "has_keyboard_backlight" = "1" + + register "beepmask0" = "0x00" + register "beepmask1" = "0x86" + register "has_power_management_beeps" = "0" + register "event2_enable" = "0xff" + register "event3_enable" = "0xff" + register "event4_enable" = "0xd0" + register "event5_enable" = "0xfc" + register "event6_enable" = "0x00" + register "event7_enable" = "0x01" + register "event8_enable" = "0x7b" + register "event9_enable" = "0xff" + register "eventa_enable" = "0x01" + register "eventb_enable" = "0x00" + register "eventc_enable" = "0xff" + register "eventd_enable" = "0xff" + register "evente_enable" = "0x0d" + end + end # LPC bridge + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on # SMBUS controller + # eeprom, 8 virtual devices, same chip + chip drivers/i2c/at24rf08c + device i2c 54 on end + device i2c 55 on end + device i2c 56 on end + device i2c 57 on end + device i2c 5c on end + device i2c 5d on end + device i2c 5e on end + device i2c 5f on end + end + end # SMBus + end + end +end diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl new file mode 100644 index 0000000..1dc3a66 --- /dev/null +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define THINKPAD_EC_GPE 17 +#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB +#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB +#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define RP03_IS_EXPRESSCARD 1 + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include "acpi/platform.asl" + + // global NVS and variables + #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> + + // General Purpose Events + //#include "acpi/gpe.asl" + + #include <cpu/intel/model_206ax/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> + #include <southbridge/intel/bd82x6x/acpi/pch.asl> + } + } + + #include "acpi/video.asl" + + /* Chipset specific sleep states */ + #include <southbridge/intel/bd82x6x/acpi/sleepstates.asl> +} diff --git a/src/mainboard/lenovo/t520/fadt.c b/src/mainboard/lenovo/t520/fadt.c new file mode 100644 index 0000000..27e6303 --- /dev/null +++ b/src/mainboard/lenovo/t520/fadt.c @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <device/pci.h> +#include <arch/acpi.h> +#include <cpu/x86/smm.h> + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), + 0x40) & 0xfffe; + + memset((void *) fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = 3; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, "CORE", 4); + header->asl_compiler_revision = 1; + + fadt->firmware_ctrl = (unsigned long) facs; + fadt->dsdt = (unsigned long) dsdt; + fadt->model = 1; + fadt->preferred_pm_profile = PM_MOBILE; + + fadt->sci_int = 0x9; + fadt->smi_cmd = APM_CNT; + fadt->acpi_enable = APM_CNT_ACPI_ENABLE; + fadt->acpi_disable = APM_CNT_ACPI_DISABLE; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0; + + fadt->pm1a_evt_blk = pmbase; + fadt->pm1b_evt_blk = 0x0; + fadt->pm1a_cnt_blk = pmbase + 0x4; + fadt->pm1b_cnt_blk = 0x0; + fadt->pm2_cnt_blk = pmbase + 0x50; + fadt->pm_tmr_blk = pmbase + 0x8; + fadt->gpe0_blk = pmbase + 0x20; + fadt->gpe1_blk = 0; + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 16; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + fadt->cst_cnt = 0; + fadt->p_lvl2_lat = 101; /* c2 not supported */ + fadt->p_lvl3_lat = 87; + fadt->flush_size = 1024; + fadt->flush_stride = 16; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0xd; + fadt->mon_alrm = 0x00; + fadt->century = 0x00; + fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; + + fadt->flags = ACPI_FADT_WBINVD | + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_SEALED_CASE | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_PLATFORM_CLOCK; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (unsigned long)facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (unsigned long)dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = pmbase; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 8; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = pmbase + 0x50; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = pmbase + 0x8; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 128; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = pmbase + 0x20; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0x0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = + acpi_checksum((void *) fadt, header->length); +} diff --git a/src/mainboard/lenovo/t520/hda_verb.h b/src/mainboard/lenovo/t520/hda_verb.h new file mode 100644 index 0000000..7999932 --- /dev/null +++ b/src/mainboard/lenovo/t520/hda_verb.h @@ -0,0 +1,317 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Vendor Name : IDT + * Vendor ID : 0x10ec0269 + * Subsystem ID : 0x17aa21fa + * Revision ID : 0x100303 + */ + + +static const u32 mainboard_cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC + 0x17aa21fa, // Subsystem ID + 0x0000007d, // Number of 4 dword sets + +/* Bits 31:28 - Codec Address */ +/* Bits 27:20 - NID */ +/* Bits 19:8 - Verb ID */ +/* Bits 7:0 - Payload */ + +/* NID 0x01 - NodeInfo */ + 0x001720FA, + 0x00172121, + 0x001722AA, + 0x00172317, + +/* NID 0x0A - External Microphone Connector + * Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq) + */ + 0x00A71C20, + 0x00A71D10, + 0x00A71EA1, + 0x00A71F04, + +/* NID 0x0B - Headphone Connector + * Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq) + */ + 0x00B71C1F, + 0x00B71D10, + 0x00B71E21, + 0x00B71F04, + +/* NID 0x0C - Not connected + * Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq) + */ + 0x00C71CF0, + 0x00C71D00, + 0x00C71EF0, + 0x00C71F40, + +/* NID 0x0D - Internal Speakers + * Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq) + */ + 0x00D71C10, + 0x00D71D01, + 0x00D71E17, + 0x00D71F90, + +/* NID 0x0F - Not connected + * Config=0x40F000F0 + */ + 0x00F71CF0, + 0x00F71D00, + 0x00F71EF0, + 0x00F71F40, + +/* NID 0x11 - Internal Microphone + * Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq) + */ + 0x01171C40, + 0x01171D01, + 0x01171EA3, + 0x01171FD5, + + 0x01271C40, + 0x01271D01, + 0x01271EA6, + 0x01271F90, + + 0x01471C10, + 0x01471D01, + 0x01471E17, + 0x01471F90, + + 0x01571C20, + 0x01571D10, + 0x01571E21, + 0x01571F03, + + 0x01871C30, + 0x01871D18, + 0x01871EA1, + 0x01871F03, + + 0x01971CF0, + 0x01971D11, + 0x01971E11, + 0x01971F41, + + 0x01970804, + 0x01870803, + 0x01470740, + 0x00970600, + + 0x00370600, + 0x00270600, + 0x00270600, + 0x00270600, + + 0x01A71CF0, + 0x01A71D11, + 0x01A71E11, + 0x01A71F41, + + 0x01D71C05, + 0x01D71D82, + 0x01D71E13, + 0x01D71F40, + + 0x01E71CF0, + 0x01E71D11, + 0x01E71E11, + 0x01E71F41, + + /* + * Hardware EQ Parameters + * Sample Rate 88200 + */ + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC00, 0x0227AD80, + 0x0227A681, 0x0227A782, 0x0227A829, 0x0227A981, + 0x0227AA82, 0x0227AB29, 0x0227AC01, 0x0227AD80, + 0x0227A63F, 0x0227A73E, 0x0227A8EB, 0x0227A93F, + 0x0227AA3E, 0x0227ABEB, 0x0227AC02, 0x0227AD80, + 0x0227A67E, 0x0227A77B, 0x0227A846, 0x0227A97E, + 0x0227AA7B, 0x0227AB46, 0x0227AC03, 0x0227AD80, + 0x0227A6C1, 0x0227A77F, 0x0227A898, 0x0227A9C1, + 0x0227AA7F, 0x0227AB98, 0x0227AC04, 0x0227AD80, + 0x0227A63E, 0x0227A7D1, 0x0227A84F, 0x0227A93E, + 0x0227AAD1, 0x0227AB4F, 0x0227AC05, 0x0227AD80, + 0x0227A683, 0x0227A7BE, 0x0227A855, 0x0227A983, + 0x0227AABE, 0x0227AB55, 0x0227AC06, 0x0227AD80, + 0x0227A63D, 0x0227A7B9, 0x0227A856, 0x0227A93D, + 0x0227AAB9, 0x0227AB56, 0x0227AC07, 0x0227AD80, + 0x0227A67C, 0x0227A741, 0x0227A8AB, 0x0227A97C, + 0x0227AA41, 0x0227ABAB, 0x0227AC08, 0x0227AD80, + 0x0227A6C3, 0x0227A775, 0x0227A85A, 0x0227A9C3, + 0x0227AA75, 0x0227AB5A, 0x0227AC09, 0x0227AD80, + 0x0227A63F, 0x0227A79E, 0x0227A829, 0x0227A93F, + 0x0227AA9E, 0x0227AB29, 0x0227AC0A, 0x0227AD80, + 0x0227A682, 0x0227A7E3, 0x0227A867, 0x0227A982, + 0x0227AAE3, 0x0227AB67, 0x0227AC0B, 0x0227AD80, + 0x0227A63E, 0x0227A74F, 0x0227A89D, 0x0227A93E, + 0x0227AA4F, 0x0227AB9D, 0x0227AC0C, 0x0227AD80, + 0x0227A67D, 0x0227A71C, 0x0227A899, 0x0227A97D, + 0x0227AA1C, 0x0227AB99, 0x0227AC0D, 0x0227AD80, + 0x0227A6C2, 0x0227A712, 0x0227A839, 0x0227A9C2, + 0x0227AA12, 0x0227AB39, 0x0227AC0E, 0x0227AD80, + 0x0227A63F, 0x0227A708, 0x0227A856, 0x0227A93F, + 0x0227AA08, 0x0227AB56, 0x0227AC0F, 0x0227AD80, + 0x0227A68E, 0x0227A7ED, 0x0227A89D, 0x0227A98E, + 0x0227AAED, 0x0227AB9D, 0x0227AC10, 0x0227AD80, + 0x0227A637, 0x0227A78F, 0x0227A853, 0x0227A937, + 0x0227AA8F, 0x0227AB53, 0x0227AC11, 0x0227AD80, + 0x0227A671, 0x0227A712, 0x0227A863, 0x0227A971, + 0x0227AA12, 0x0227AB63, 0x0227AC12, 0x0227AD80, + 0x0227A6C9, 0x0227A768, 0x0227A856, 0x0227A9C9, + 0x0227AA68, 0x0227AB56, 0x0227AC13, 0x0227AD80, + 0x0227A642, 0x0227A709, 0x0227A838, 0x0227A942, + 0x0227AA09, 0x0227AB38, 0x0227AC14, 0x0227AD80, + 0x0227A69C, 0x0227A78A, 0x0227A867, 0x0227A99C, + 0x0227AA8A, 0x0227AB67, 0x0227AC15, 0x0227AD80, + 0x0227A634, 0x0227A717, 0x0227A8E3, 0x0227A934, + 0x0227AA17, 0x0227ABE3, 0x0227AC16, 0x0227AD80, + 0x0227A663, 0x0227A775, 0x0227A899, 0x0227A963, + 0x0227AA75, 0x0227AB99, 0x0227AC17, 0x0227AD80, + 0x0227A6C9, 0x0227A7DE, 0x0227A8E5, 0x0227A9C9, + 0x0227AADE, 0x0227ABE5, 0x0227AC18, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC19, 0x0227AD80, + + /* + * Hardware EQ Parameters + * Sample Rate 96000 + */ + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1A, 0x0227AD80, + 0x0227A681, 0x0227A762, 0x0227A8EE, 0x0227A981, + 0x0227AA62, 0x0227ABEE, 0x0227AC1B, 0x0227AD80, + 0x0227A63F, 0x0227A74E, 0x0227A888, 0x0227A93F, + 0x0227AA4E, 0x0227AB88, 0x0227AC1C, 0x0227AD80, + 0x0227A67E, 0x0227A79A, 0x0227A8E7, 0x0227A97E, + 0x0227AA9A, 0x0227ABE7, 0x0227AC1D, 0x0227AD80, + 0x0227A6C1, 0x0227A760, 0x0227A8C3, 0x0227A9C1, + 0x0227AA60, 0x0227ABC3, 0x0227AC1E, 0x0227AD80, + 0x0227A63E, 0x0227A7E9, 0x0227A84B, 0x0227A93E, + 0x0227AAE9, 0x0227AB4B, 0x0227AC1F, 0x0227AD80, + 0x0227A683, 0x0227A76C, 0x0227A8F2, 0x0227A983, + 0x0227AA6C, 0x0227ABF2, 0x0227AC20, 0x0227AD80, + 0x0227A63D, 0x0227A7E7, 0x0227A880, 0x0227A93D, + 0x0227AAE7, 0x0227AB80, 0x0227AC21, 0x0227AD80, + 0x0227A67C, 0x0227A793, 0x0227A80E, 0x0227A97C, + 0x0227AA93, 0x0227AB0E, 0x0227AC22, 0x0227AD80, + 0x0227A6C3, 0x0227A72F, 0x0227A835, 0x0227A9C3, + 0x0227AA2F, 0x0227AB35, 0x0227AC23, 0x0227AD80, + 0x0227A63F, 0x0227A7A5, 0x0227A8FE, 0x0227A93F, + 0x0227AAA5, 0x0227ABFE, 0x0227AC24, 0x0227AD80, + 0x0227A682, 0x0227A798, 0x0227A89D, 0x0227A982, + 0x0227AA98, 0x0227AB9D, 0x0227AC25, 0x0227AD80, + 0x0227A63E, 0x0227A772, 0x0227A839, 0x0227A93E, + 0x0227AA72, 0x0227AB39, 0x0227AC26, 0x0227AD80, + 0x0227A67D, 0x0227A767, 0x0227A863, 0x0227A97D, + 0x0227AA67, 0x0227AB63, 0x0227AC27, 0x0227AD80, + 0x0227A6C1, 0x0227A7E7, 0x0227A8C8, 0x0227A9C1, + 0x0227AAE7, 0x0227ABC8, 0x0227AC28, 0x0227AD80, + 0x0227A63F, 0x0227A71B, 0x0227A81A, 0x0227A93F, + 0x0227AA1B, 0x0227AB1A, 0x0227AC29, 0x0227AD80, + 0x0227A68D, 0x0227A763, 0x0227A872, 0x0227A98D, + 0x0227AA63, 0x0227AB72, 0x0227AC2A, 0x0227AD80, + 0x0227A638, 0x0227A733, 0x0227A809, 0x0227A938, + 0x0227AA33, 0x0227AB09, 0x0227AC2B, 0x0227AD80, + 0x0227A672, 0x0227A79C, 0x0227A88E, 0x0227A972, + 0x0227AA9C, 0x0227AB8E, 0x0227AC2C, 0x0227AD80, + 0x0227A6C8, 0x0227A7B1, 0x0227A8DD, 0x0227A9C8, + 0x0227AAB1, 0x0227ABDD, 0x0227AC2D, 0x0227AD80, + 0x0227A641, 0x0227A7E1, 0x0227A8D8, 0x0227A941, + 0x0227AAE1, 0x0227ABD8, 0x0227AC2E, 0x0227AD80, + 0x0227A699, 0x0227A70D, 0x0227A820, 0x0227A999, + 0x0227AA0D, 0x0227AB20, 0x0227AC2F, 0x0227AD80, + 0x0227A634, 0x0227A7FE, 0x0227A823, 0x0227A934, + 0x0227AAFE, 0x0227AB23, 0x0227AC30, 0x0227AD80, + 0x0227A666, 0x0227A7F2, 0x0227A8E0, 0x0227A966, + 0x0227AAF2, 0x0227ABE0, 0x0227AC31, 0x0227AD80, + 0x0227A6C9, 0x0227A720, 0x0227A804, 0x0227A9C9, + 0x0227AA20, 0x0227AB04, 0x0227AC32, 0x0227AD80, + 0x0227A640, 0x0227A700, 0x0227A800, 0x0227A940, + 0x0227AA00, 0x0227AB00, 0x0227AC33, 0x0227AD80, + + /* SAFEDSP Parameters */ + 0x022782C1, 0x02277127, 0x02277227, 0x02278801, + 0x02278C58, 0x02278E90, 0x0227890A, 0x02278A14, + 0x02278B0F, 0x0017B008, + + /* Misc entries */ + 0x00B707C0, /* Enable PortB as Output with HP amp */ + 0x00D70740, /* Enable PortD as Output */ + 0x0017A200, /* Disable ClkEn of PortSenseTst */ + 0x0017C621, /* Slave Port - Port A used as microphone input for + combo Jack + Master Port - Port B used for Jack Presence Detect + Enable Combo Jack Detection */ + 0x0017A208, /* Enable ClkEn of PortSenseTst */ + 0x00170500, /* Set power state to D0 */ + + /* --- Next Codec --- */ + +/* Vendor Name : Intel + * Vendor ID : 0x80862806 + * Subsystem ID : 0x80860101 + * Revision ID : 0x100000 + */ + /* coreboot specific header */ + 0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI + 0x80860101, // Subsystem ID + 0x00000004, // Number of IDs + + /* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */ + 0x30172001, + 0x30172101, + 0x30172286, + 0x30172380, + + /* Pin Complex (NID 0x05) Digital Out at Int HDMI */ + 0x30571c10, + 0x30571d00, + 0x30571e56, + 0x30571f18, + + /* Pin Complex (NID 0x06) Digital Out at Int HDMI */ + 0x30671c20, + 0x30671d00, + 0x30671e56, + 0x30671f18, + + /* Pin Complex (NID 0x07) Digital Out at Int HDMI */ + 0x30771c30, + 0x30771d00, + 0x30771e56, + 0x30771f18 +}; + +static const u32 mainboard_pc_beep_verbs[] = { + 0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */ +}; + +static const u32 mainboard_pc_beep_verbs_size = + ARRAY_SIZE(mainboard_pc_beep_verbs); + + diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c new file mode 100644 index 0000000..e387a9f --- /dev/null +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -0,0 +1,194 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011-2012 Google Inc. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> +#include "hda_verb.h" +#include <southbridge/intel/bd82x6x/pch.h> +#include <smbios.h> +#include <device/pci.h> +#include <cbfs.h> +#include <pc80/keyboard.h> + +void mainboard_suspend_resume(void) +{ + /* Call SMM finalize() handlers before resume */ + outb(0xcb, 0xb2); +} + +#if CONFIG_VGA_ROM_RUN +static int int15_handler(void) +{ + int res = 0; + + printk(BIOS_DEBUG, "%s: INT15 function %04x!\n", + __func__, X86_AX); + + switch (X86_AX) { + case 0x5f34: + /* + * Set Panel Fitting Hook: + * bit 2 = Graphics Stretching + * bit 1 = Text Stretching + * bit 0 = Centering (do not set with bit1 or bit2) + * 0 = video bios default + */ + X86_AX = 0x005f; + X86_CL = 0x00; /* Use video bios default */ + res = 1; + break; + case 0x5f35: + /* + * Boot Display Device Hook: + * bit 0 = CRT + * bit 1 = TV (eDP) + * bit 2 = EFP + * bit 3 = LFP + * bit 4 = CRT2 + * bit 5 = TV2 (eDP) + * bit 6 = EFP2 + * bit 7 = LFP2 + */ + X86_AX = 0x005f; + X86_CX = 0x0000; /* Use video bios default */ + res = 1; + break; + case 0x5f51: + /* + * Hook to select active LFP configuration: + * 00h = No LVDS, VBIOS does not enable LVDS + * 01h = Int-LVDS, LFP driven by integrated LVDS decoder + * 02h = SVDO-LVDS, LFP driven by SVDO decoder + * 03h = eDP, LFP Driven by Int-DisplayPort encoder + */ + X86_AX = 0x005f; + X86_CX = 0x0001; /* Int-LVDS */ + res = 1; + break; + case 0x5f70: + switch (X86_CH) { + case 0: + /* Get Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 1: + /* Set Mux */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + case 2: + /* Get SG/Non-SG mode */ + X86_AX = 0x005f; + X86_CX = 0x0000; + res = 1; + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 5f70 function: 0x%02x\n", + X86_CH); + break; + } + break; + + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + break; + } + return res; +} +#endif + +const char *smbios_mainboard_version(void) +{ + return "ThinkPad T520"; +} + +/* Audio Setup */ + +extern const u32 *cim_verb_data; +extern u32 cim_verb_data_size; +extern const u32 *pc_beep_verbs; +extern u32 pc_beep_verbs_size; + +static void verb_setup(void) +{ + cim_verb_data = mainboard_cim_verb_data; + cim_verb_data_size = sizeof(mainboard_cim_verb_data); + pc_beep_verbs = mainboard_pc_beep_verbs; + pc_beep_verbs_size = mainboard_pc_beep_verbs_size; + +} + +static void mainboard_init(device_t dev) +{ + RCBA32(0x38c8) = 0x00002005; + RCBA32(0x38c4) = 0x00802005; + RCBA32(0x38c0) = 0x00000007; + + pc_keyboard_init(0); + + /* Enable expresscard hotplug events. */ + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), + 0xd8, + pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), 0xd8) + | (1 << 30)); + + pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 2)), + 0x42, 0x142); +} + +/* mainboard_enable is executed as first thing after +enumerate_buses(). */ +static void mainboard_enable(device_t dev) +{ + dev->ops->init = mainboard_init; +#if CONFIG_VGA_ROM_RUN + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + verb_setup(); +} + +void h8_mainboard_init_dock (void); + +void h8_mainboard_init_dock (void) +{ + return; +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c new file mode 100644 index 0000000..a2c3778 --- /dev/null +++ b/src/mainboard/lenovo/t520/romstage.c @@ -0,0 +1,295 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <lib.h> +#include <timestamp.h> +#include <arch/byteorder.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <device/pnp_def.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <cbmem.h> +#include <console/console.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <northbridge/intel/sandybridge/raminit.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/gpio.h> +#include <arch/cpu.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/msr.h> +#include <cbfs.h> + +static void pch_enable_lpc(void) +{ + /* T520 EC Decode Range Port60/64, Port62/66 */ + /* Enable EC, PS/2 Keyboard/Mouse */ + pci_write_config16(PCH_LPC_DEV, LPC_EN, + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | + COMA_LPC_EN); + + pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); + pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); + pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); + + pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); + + pci_write_config32(PCH_LPC_DEV, 0xac, + 0x80010000); +} + +static void rcba_config(void) +{ + /* + * GFX INTA -> PIRQA (MSI) + * D28IP_P1IP WLAN INTA -> PIRQB + * D28IP_P2IP ETH0 INTB -> PIRQF + * D28IP_P3IP SDCARD INTC -> PIRQD + * D29IP_E1P EHCI1 INTA -> PIRQD + * D26IP_E2P EHCI2 INTA -> PIRQF + * D31IP_SIP SATA INTA -> PIRQB (MSI) + * D31IP_SMIP SMBUS INTB -> PIRQH + * D31IP_TTIP THRT INTC -> PIRQA + * D27IP_ZIP HDA INTA -> PIRQA (MSI) + * + * Trackpad interrupt is edge triggered and cannot be shared. + * TRACKPAD -> PIRQG + + */ + + /* Device interrupt pin register (board specific) */ + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTB << D28IP_P2IP) | + (INTC << D28IP_P3IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + + /* Device interrupt route registers */ + DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC); + DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG); + DIR_ROUTE(D28IR, PIRQB, PIRQF, PIRQD, PIRQE); + DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB); + DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH); + DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD); + DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD); + + /* Enable IOAPIC (generic) */ + RCBA16(OIC) = 0x0100; + /* PCH BWG says to read back the IOAPIC enable register */ + (void) RCBA16(OIC); + + /* Disable unused devices (board specific) */ + RCBA32(FD) = 0x17f81fe3; + RCBA32(BUC) = 0; +} + +void main(unsigned long bist) +{ + int boot_mode = 0; + int cbmem_was_initted; + u32 pm1_cnt; + u16 pm1_sts; + + if (MCHBAR16(SSKPD) == 0xCAFE) { + outb(0x6, 0xcf9); + hlt (); + } + + struct pei_data pei_data = { + .pei_version = PEI_VERSION, + .mchbar = DEFAULT_MCHBAR, + .dmibar = DEFAULT_DMIBAR, + .epbar = DEFAULT_EPBAR, + .pciexbar = CONFIG_MMCONF_BASE_ADDRESS, + .smbusbar = SMBUS_IO_BASE, + .wdbbar = 0x4000000, + .wdbsize = 0x1000, + .hpet_address = CONFIG_HPET_ADDRESS, + .rcba = DEFAULT_RCBABASE, + .pmbase = DEFAULT_PMBASE, + .gpiobase = DEFAULT_GPIOBASE, + .thermalbase = 0xfed08000, + .system_type = 0, // 0 Mobile, 1 Desktop/Server + .tseg_size = CONFIG_SMM_TSEG_SIZE, + .spd_addresses = { 0xA0, 0x00,0xA2,0x00 }, + .ts_addresses = { 0x00, 0x00, 0x00, 0x00 }, + .ec_present = 1, + .gbe_enable = 1, + .ddr3lv_support = 0, + // 0 = leave channel enabled + // 1 = disable dimm 0 on channel + // 2 = disable dimm 1 on channel + // 3 = disable dimm 0+1 on channel + .dimm_channel0_disabled = 2, + .dimm_channel1_disabled = 2, + .max_ddr3_freq = 1600, + .usb_port_config = { + /* enabled usb oc pin length */ + { 1, 0, 0x0080 }, /* P0 (left, fan side), OC 0 */ + { 1, 1, 0x0080 }, /* P1 (left touchpad side), OC 1 */ + { 1, 0, 0x0040 }, /* P2: dock, OC 3 */ + { 1, 0, 0x0040 }, /* P3: wwan, no OC */ + { 1, 0, 0x0080 }, /* P4: Wacom tablet on X230t, otherwise empty */ + { 1, 0, 0x0080 }, /* P5: Expresscard, no OC */ + { 0, 0, 0x0000 }, /* P6: Empty */ + { 1, 0, 0x0080 }, /* P7: dock, no OC */ + { 1, 4, 0x0080 }, /* P8: Empty */ + { 1, 5, 0x0080 }, /* P9: Right (EHCI debug), OC 5 */ + { 1, 0, 0x0040 }, /* P10: fingerprint reader, no OC */ + { 1, 0, 0x0040 }, /* P11: bluetooth, no OC. */ + { 1, 0, 0x0040 }, /* P12: wlan, no OC */ + { 1, 0, 0x0080 }, /* P13: webcam, no OC */ + }, + .ddr_refresh_rate_config = 2, /* Force double refresh rate */ + }; + + timestamp_init(get_initial_timestamp()); + timestamp_add_now(TS_START_ROMSTAGE); + + if (bist == 0) + enable_lapic(); + + pch_enable_lpc(); + + /* Enable GPIOs */ + pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE|1); + pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); + + outl(0x3962a5ff, DEFAULT_GPIOBASE); + outl(0x8ebf6aff, DEFAULT_GPIOBASE + 4); + outl(0x66957f3b, DEFAULT_GPIOBASE + 0xc); + outl(0x00080000, DEFAULT_GPIOBASE + 0x20); + outl(0x00002082, DEFAULT_GPIOBASE + 0x2c); + outl(0x02ff06de, DEFAULT_GPIOBASE + 0x30); + outl(0x1f47f9f5, DEFAULT_GPIOBASE + 0x34); + outl(0xbdbffd47, DEFAULT_GPIOBASE + 0x38); + outl(0x000000f0, DEFAULT_GPIOBASE + 0x40); + outl(0x00000ff0, DEFAULT_GPIOBASE + 0x44); + outl(0x00000f4f, DEFAULT_GPIOBASE + 0x48); + outl(0x01000000, DEFAULT_GPIOBASE + 0x60); + + /* Initialize console device(s) */ + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Perform some early chipset initialization required + * before RAM initialization can work + */ + sandybridge_early_initialization(SANDYBRIDGE_MOBILE); + printk(BIOS_DEBUG, "Back from sandybridge_early_initialization()\n"); + + /* Check PM1_STS[15] to see if we are waking from Sx */ + pm1_sts = inw(DEFAULT_PMBASE + PM1_STS); + + /* Read PM1_CNT[12:10] to determine which Sx state */ + pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); + + if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { +#if CONFIG_HAVE_ACPI_RESUME + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + boot_mode = 2; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + PM1_CNT); +#else + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); +#endif + } + + post_code(0x38); + /* Enable SPD ROMs and DDR-III DRAM */ + enable_smbus(); + + /* Prepare USB controller early in S3 resume */ + if (boot_mode == 2) + enable_usb_bar(); + + post_code(0x39); + post_code(0x3a); + + pei_data.boot_mode = boot_mode; + timestamp_add_now(TS_BEFORE_INITRAM); + + /* MRC.bin has a bug and sometimes halts (instead of reboot?). + */ + if (boot_mode != 2) { + RCBA32(GCS) = RCBA32(GCS) & ~(1 << 5); /* reset */ + outw((0 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* let timer go */ + } + + sdram_initialize(&pei_data); + + if (boot_mode != 2) { + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + } + + timestamp_add_now(TS_AFTER_INITRAM); + post_code(0x3c); + + rcba_config(); + post_code(0x3d); + + quick_ram_check(); + post_code(0x3e); + + MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_recovery(boot_mode == 2); + if (boot_mode != 2) { + save_mrc_data(&pei_data); + } + +#if CONFIG_HAVE_ACPI_RESUME + /* If there is no high memory area, we didn't boot before, so + * this is not a resume. In that case we just create the cbmem toc. + */ + + *(u32 *)CBMEM_BOOT_MODE = 0; + *(u32 *)CBMEM_RESUME_BACKUP = 0; + + if ((boot_mode == 2) && cbmem_was_initted) { + void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + if (resume_backup_memory) { + *(u32 *)CBMEM_BOOT_MODE = boot_mode; + *(u32 *)CBMEM_RESUME_BACKUP = (u32)resume_backup_memory; + } + /* Magic for S3 resume */ + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); + } else if (boot_mode == 2) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + hlt(); + } else { + pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); + } +#endif + post_code(0x3f); + timestamp_add_now(TS_END_ROMSTAGE); +} diff --git a/src/mainboard/lenovo/t520/smi.h b/src/mainboard/lenovo/t520/smi.h new file mode 100644 index 0000000..f7ffb41 --- /dev/null +++ b/src/mainboard/lenovo/t520/smi.h @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2010 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ \ No newline at end of file diff --git a/src/mainboard/lenovo/t520/smihandler.c b/src/mainboard/lenovo/t520/smihandler.c new file mode 100644 index 0000000..f4ed367 --- /dev/null +++ b/src/mainboard/lenovo/t520/smihandler.c @@ -0,0 +1,169 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <ec/acpi/ec.h> +#include <pc80/mc146818rtc.h> +#include <ec/lenovo/h8/h8.h> +#include <delay.h> +#include <southbridge/intel/bd82x6x/nvs.h> +#include <southbridge/intel/bd82x6x/pch.h> +#include <southbridge/intel/bd82x6x/me.h> +#include <northbridge/intel/sandybridge/sandybridge.h> +#include <cpu/intel/model_206ax/model_206ax.h> + +/* The southbridge SMI handler checks whether gnvs has a + * valid pointer before calling the trap handler + */ +extern global_nvs_t *gnvs; + +static void mainboard_smm_init(void) +{ + printk(BIOS_DEBUG, "initializing SMI\n"); + /* Enable 0x1600/0x1600 register pair */ + ec_set_bit(0x00, 0x05); +} + +int mainboard_io_trap_handler(int smif) +{ + static int smm_initialized; + + if (!smm_initialized) { + mainboard_smm_init(); + smm_initialized = 1; + } + + /* On success, the IO Trap Handler returns 1 + * On failure, the IO Trap Handler returns a value != 1 */ + return 0; +} + +static void mainboard_smi_brightness_up(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf); +} + +static void mainboard_smi_brightness_down(void) +{ + u8 value; + + if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10) + pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, + (value - 0x10) & 0xf0); +} + +static void mainboard_smi_handle_ec_sci(void) +{ + u8 status = inb(EC_SC); + u8 event; + + if (!(status & EC_SCI_EVT)) + return; + + event = ec_query(); + printk(BIOS_DEBUG, "EC event %02x\n", event); + + switch (event) { + case 0x14: + /* brightness up */ + mainboard_smi_brightness_up(); + break; + case 0x15: + /* brightness down */ + mainboard_smi_brightness_down(); + break; + default: + break; + } +} + +void mainboard_smi_gpi(u32 gpi_sts) +{ + if (gpi_sts & (1 << 12)) + mainboard_smi_handle_ec_sci(); +} + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 data) +{ + u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; + u8 tmp; + + printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, + data); + + if (!pmbase) + return 0; + + switch (data) { + case APM_CNT_ACPI_ENABLE: + /* use 0x1600/0x1604 to prevent races with userspace */ + ec_set_ports(0x1604, 0x1600); + /* route H8SCI to SCI */ + outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x02; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_ACPI_DISABLE: + /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't + provide a EC query function */ + ec_set_ports(0x66, 0x62); + /* route H8SCI# to SMI */ + outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, + pmbase + ALT_GP_SMI_EN); + tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); + tmp &= ~0x03; + tmp |= 0x01; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); + /* discard all events, and enable attention */ + ec_write(0x80, 0x01); + break; + case APM_CNT_FINALIZE: + printk(BIOS_DEBUG, "APMC: FINALIZE\n"); + if (mainboard_finalized) { + printk(BIOS_DEBUG, "APMC#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + + default: + break; + } + return 0; +} diff --git a/src/mainboard/lenovo/t520/thermal.h b/src/mainboard/lenovo/t520/thermal.h new file mode 100644 index 0000000..23bdb76 --- /dev/null +++ b/src/mainboard/lenovo/t520/thermal.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The Chromium OS Authors. All rights reserved. + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef T520_THERMAL_H +#define T520_THERMAL_H + + /* Temperature which OS will shutdown at */ + #define CRITICAL_TEMPERATURE 100 + + /* Temperature which OS will throttle CPU */ + #define PASSIVE_TEMPERATURE 90 + +#endif /* T520_THERMAL_H */

1 0

Patch set updated for coreboot: 67d1c2f util/sconfig: Fix missing prototype issue with bison/flex.
by Edward O'Callaghan 10 May '14

10 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5274 -gerrit commit 67d1c2f9fcf894acc386a60671ea98631c6b6972 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Feb 20 19:42:59 2014 +1100 util/sconfig: Fix missing prototype issue with bison/flex. Clang throws missing prototype warnings where GCC does not. Shift around prototype declarations a little. Change-Id: I929085e5ed87452e77409889e04b05d32e5f356c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- util/sconfig/sconfig.h | 20 ++++++++++++++++++++ util/sconfig/sconfig.tab.c_shipped | 17 +---------------- 2 files changed, 21 insertions(+), 16 deletions(-) diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index b8a231a..1aef26d 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -100,3 +100,23 @@ void alias_siblings(struct device *d); void add_resource(struct device *dev, int type, int index, int base); void add_register(struct device *dev, char *name, char *val); void add_pci_subsystem_ids(struct device *dev, int vendor, int device, int inherit); + +void add_ioapic_info(struct device *, int, const char *, int); + +void yyerror (const char *); +void yyrestart (FILE *input_file ); + +/* Prevent warnings from -Wmissing-prototypes. */ +#ifdef YYPARSE_PARAM +#if defined __STDC__ || defined __cplusplus +int yyparse (void *YYPARSE_PARAM); +#else +int yyparse (); +#endif +#else /* ! YYPARSE_PARAM */ +#if defined __STDC__ || defined __cplusplus +int yyparse (void); +#else +int yyparse (); +#endif +#endif /* ! YYPARSE_PARAM */ diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 3a56ac8..56045d0 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -673,6 +673,7 @@ while (YYID (0)) #ifdef YYLEX_PARAM # define YYLEX yylex (YYLEX_PARAM) #else +int yylex(void); # define YYLEX yylex () #endif @@ -1127,22 +1128,6 @@ yydestruct (yymsg, yytype, yyvaluep) } -/* Prevent warnings from -Wmissing-prototypes. */ -#ifdef YYPARSE_PARAM -#if defined __STDC__ || defined __cplusplus -int yyparse (void *YYPARSE_PARAM); -#else -int yyparse (); -#endif -#else /* ! YYPARSE_PARAM */ -#if defined __STDC__ || defined __cplusplus -int yyparse (void); -#else -int yyparse (); -#endif -#endif /* ! YYPARSE_PARAM */ - - /* The lookahead symbol. */ int yychar;

1 0

Patch set updated for coreboot: f74882d superio/ite/*: Factor out generic romstage component
by Edward O'Callaghan 10 May '14

10 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5585 -gerrit commit f74882dfe36081a51de16c6ad2554e54b3961db8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Apr 27 00:41:50 2014 +1000 superio/ite/*: Factor out generic romstage component Following the reasoning of: cf7b498 superio/fintek/*: Factor out generic romstage component Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/amd/dbm690t/romstage.c | 8 ++- src/mainboard/amd/mahogany/romstage.c | 7 +- src/mainboard/amd/mahogany_fam10/romstage.c | 7 +- src/mainboard/amd/tilapia_fam10/romstage.c | 7 +- src/mainboard/asus/a8n_e/romstage.c | 10 +-- src/mainboard/asus/f2a85-m/romstage.c | 7 +- src/mainboard/asus/m2n-e/romstage.c | 5 +- src/mainboard/asus/m2v-mx_se/romstage.c | 5 +- src/mainboard/asus/m2v/romstage.c | 12 ++-- src/mainboard/asus/m4a78-em/romstage.c | 7 +- src/mainboard/asus/m4a785-m/romstage.c | 7 +- src/mainboard/asus/m5a88-v/romstage.c | 3 +- src/mainboard/ecs/p6iwp-fe/romstage.c | 10 ++- src/mainboard/gigabyte/ga-6bxc/romstage.c | 3 +- src/mainboard/gigabyte/ga-6bxe/romstage.c | 3 +- src/mainboard/gigabyte/ga_2761gxdk/romstage.c | 5 +- src/mainboard/gigabyte/m57sli/romstage.c | 5 +- src/mainboard/gigabyte/ma785gm/romstage.c | 7 +- src/mainboard/gigabyte/ma785gmt/romstage.c | 7 +- src/mainboard/gigabyte/ma78gm/romstage.c | 7 +- src/mainboard/lippert/hurricane-lx/romstage.c | 16 ++--- src/mainboard/lippert/literunner-lx/romstage.c | 16 ++--- src/mainboard/lippert/roadrunner-lx/romstage.c | 16 ++--- src/mainboard/lippert/spacerunner-lx/romstage.c | 16 ++--- src/mainboard/siemens/sitemp_g1p1/romstage.c | 8 ++- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c | 3 +- src/mainboard/technexion/tim5690/romstage.c | 8 ++- src/mainboard/technexion/tim8690/romstage.c | 8 ++- src/mainboard/via/pc2500e/romstage.c | 3 +- src/superio/ite/Kconfig | 22 +++++++ src/superio/ite/Makefile.inc | 3 + src/superio/ite/common/early_serial.c | 86 +++++++++++++++++++++++++ src/superio/ite/common/ite.h | 36 +++++++++++ src/superio/ite/it8671f/Makefile.inc | 2 +- src/superio/ite/it8671f/early_serial.c | 4 +- src/superio/ite/it8671f/it8671f.h | 12 +++- src/superio/ite/it8712f/Makefile.inc | 2 +- src/superio/ite/it8712f/early_serial.c | 38 +---------- src/superio/ite/it8712f/it8712f.h | 9 ++- src/superio/ite/it8716f/Makefile.inc | 1 - src/superio/ite/it8716f/early_serial.c | 79 ----------------------- src/superio/ite/it8716f/it8716f.h | 7 -- src/superio/ite/it8718f/Makefile.inc | 2 +- src/superio/ite/it8718f/early_serial.c | 35 ---------- src/superio/ite/it8718f/it8718f.h | 8 +-- src/superio/ite/it8721f/Makefile.inc | 1 - src/superio/ite/it8721f/early_serial.c | 85 ------------------------ src/superio/ite/it8721f/it8721f.h | 6 -- src/superio/ite/it8728f/Makefile.inc | 21 ------ src/superio/ite/it8728f/early_serial.c | 74 --------------------- src/superio/ite/it8728f/it8728f.h | 12 ---- 51 files changed, 306 insertions(+), 465 deletions(-) diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 7a0c8f9..c9a04f5 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -30,7 +30,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <spd.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -38,6 +39,8 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 93870c5..00223ae 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -31,7 +31,8 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -39,6 +40,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -81,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 06deb18..278a3bd 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -50,6 +51,8 @@ #include "northbridge/amd/amdfam10/debug.c" #include <spd.h> +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 30e56d4..6e28cbd 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 29f425a..c0fa6a5 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -21,8 +21,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Used by it8712f_enable_serial(). */ +/* Used by ite_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) #include <stdint.h> #include <string.h> @@ -33,7 +34,8 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -103,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 4aa4b04..487f068 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -36,16 +36,19 @@ #include <southbridge/amd/agesa/hudson/smbus.h> #include <stdint.h> #include <string.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> /* TODO: remove .c includes */ #include <drivers/pc80/i8254.c> #include <drivers/pc80/i8259.c> -#include <superio/ite/it8712f/early_serial.c> #define MMIO_NON_POSTED_START 0xfed00000 #define MMIO_NON_POSTED_END 0xfedfffff #define SB_MMIO 0xFED80000 #define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void sbxxx_enable_48mhzout(void) { /* most likely programming to 48MHz out signal */ @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* enable SIO clock */ sbxxx_enable_48mhzout(); it8712f_kill_watchdog(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_enable_3vsbsw(); console_init(); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 6892b28..d12b77c 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -37,6 +37,7 @@ #include <spd.h> #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -104,8 +105,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_24); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); report_bist_failure(bist); diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index ef0ce87..0085bb4 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -127,7 +128,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); console_init(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 1ca145d..acf8f91 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -38,7 +38,8 @@ unsigned int get_sbdn(unsigned bus); #include "lib/delay.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -46,6 +47,7 @@ unsigned int get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) +#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define IT8712F_GPIO_BASE 0x0a20 @@ -163,15 +165,13 @@ static void m2v_it8712f_gpio_init(void) * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable */ - it8712f_enter_conf(); giv = gpio_init_data; while (giv->addr) { printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n", giv->addr, giv->val); - it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val); + ite_reg_write(IT8712F_GPIO, giv->addr, giv->val); giv++; } - it8712f_exit_conf(); printk(BIOS_INFO, "it8712f gpio: Setting DDR2 voltage to 1.80V\n"); /* @@ -225,8 +225,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) int needs_reset = 0; struct sys_info *sysinfo = &sysinfo_car; - it8712f_24mhz_clkin(); - it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 18c6f18..93810d2 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index 660ab0f..b360636 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m5a88-v/romstage.c b/src/mainboard/asus/m5a88-v/romstage.c index 94a1e4e..9fca93f 100644 --- a/src/mainboard/asus/m5a88-v/romstage.c +++ b/src/mainboard/asus/m5a88-v/romstage.c @@ -41,6 +41,7 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" +#include <superio/ite/common/ite.h> #include <superio/ite/it8721f/it8721f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -100,7 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb800_clk_output_48Mhz(); - it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); printk(BIOS_DEBUG, "\n"); diff --git a/src/mainboard/ecs/p6iwp-fe/romstage.c b/src/mainboard/ecs/p6iwp-fe/romstage.c index 1ebdedd..c014c57 100644 --- a/src/mainboard/ecs/p6iwp-fe/romstage.c +++ b/src/mainboard/ecs/p6iwp-fe/romstage.c @@ -30,13 +30,17 @@ #include "northbridge/intel/i82810/raminit.h" #include "drivers/pc80/udelay_io.c" #include "cpu/x86/bist.h" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include <lib.h> +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) + void main(unsigned long bist) { - it8712f_24mhz_clkin(); - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); report_bist_failure(bist); enable_smbus(); diff --git a/src/mainboard/gigabyte/ga-6bxc/romstage.c b/src/mainboard/gigabyte/ga-6bxc/romstage.c index 89761c9..1b2e29b 100644 --- a/src/mainboard/gigabyte/ga-6bxc/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxc/romstage.c @@ -30,8 +30,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -void it8671f_48mhz_clkin(void); -#include "superio/ite/it8671f/early_serial.c" +#include <superio/ite/it8671f/it8671f.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) diff --git a/src/mainboard/gigabyte/ga-6bxe/romstage.c b/src/mainboard/gigabyte/ga-6bxe/romstage.c index 85a899a..c3926f0 100644 --- a/src/mainboard/gigabyte/ga-6bxe/romstage.c +++ b/src/mainboard/gigabyte/ga-6bxe/romstage.c @@ -30,8 +30,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -static void it8671f_48mhz_clkin(void); -#include "superio/ite/it8671f/early_serial.c" +#include <superio/ite/it8671f/it8671f.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x3f0, IT8671F_SP1) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 86158c8..10bbb6f 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -38,6 +38,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -125,8 +126,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index 44dda27..b2e1d70 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -35,6 +35,7 @@ #include "lib/delay.c" #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" @@ -133,8 +134,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); #endif - it8716f_conf_clkin(CLKIN_DEV, IT8716F_UART_CLK_PREDIVIDE_48); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_48); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); setup_mb_resource_map(); diff --git a/src/mainboard/gigabyte/ma785gm/romstage.c b/src/mainboard/gigabyte/ma785gm/romstage.c index ecee35b..451cb79 100644 --- a/src/mainboard/gigabyte/ma785gm/romstage.c +++ b/src/mainboard/gigabyte/ma785gm/romstage.c @@ -37,7 +37,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -45,6 +46,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); console_init(); diff --git a/src/mainboard/gigabyte/ma785gmt/romstage.c b/src/mainboard/gigabyte/ma785gmt/romstage.c index ecee35b..451cb79 100644 --- a/src/mainboard/gigabyte/ma785gmt/romstage.c +++ b/src/mainboard/gigabyte/ma785gmt/romstage.c @@ -37,7 +37,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -45,6 +46,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -91,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); console_init(); diff --git a/src/mainboard/gigabyte/ma78gm/romstage.c b/src/mainboard/gigabyte/ma78gm/romstage.c index bd9011e..bfc50b6 100644 --- a/src/mainboard/gigabyte/ma78gm/romstage.c +++ b/src/mainboard/gigabyte/ma78gm/romstage.c @@ -41,7 +41,8 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> #include "cpu/x86/bist.h" -#include "superio/ite/it8718f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8718f/it8718f.h> #include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/early_setup.c" @@ -49,6 +50,8 @@ #include "southbridge/amd/sb700/smbus.h" #include "northbridge/amd/amdfam10/debug.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) + static void activate_spd_rom(const struct mem_controller *ctrl) { } static int spd_read_byte(u32 device, u32 address) @@ -95,7 +98,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs780_dev8(); sb7xx_51xx_lpc_init(); - it8718f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8718f_disable_reboot(); console_init(); diff --git a/src/mainboard/lippert/hurricane-lx/romstage.c b/src/mainboard/lippert/hurricane-lx/romstage.c index 95ea27d..063721b 100644 --- a/src/mainboard/lippert/hurricane-lx/romstage.c +++ b/src/mainboard/lippert/hurricane-lx/romstage.c @@ -35,9 +35,13 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + /* Bit0 enables Spread Spectrum. */ #define SMC_CONFIG 0x01 @@ -77,7 +81,6 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x042C, // disable ATXPG; VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 enabled 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -101,13 +104,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -126,7 +126,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/literunner-lx/romstage.c b/src/mainboard/lippert/literunner-lx/romstage.c index 6edcf37..174620a 100644 --- a/src/mainboard/lippert/literunner-lx/romstage.c +++ b/src/mainboard/lippert/literunner-lx/romstage.c @@ -35,9 +35,13 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + /* Bit0 enables Spread Spectrum, bit1 makes on-board CF slot act as IDE slave. */ #if CONFIG_ONBOARD_IDE_SLAVE #define SMC_CONFIG 0x03 @@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -143,13 +146,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -169,7 +169,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/roadrunner-lx/romstage.c b/src/mainboard/lippert/roadrunner-lx/romstage.c index 68dcfc0..2642373 100644 --- a/src/mainboard/lippert/roadrunner-lx/romstage.c +++ b/src/mainboard/lippert/roadrunner-lx/romstage.c @@ -35,9 +35,13 @@ #include <spd.h> #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) @@ -53,7 +57,6 @@ int spd_read_byte(unsigned int device, unsigned int address) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x1E2C, // disable ATXPG; VIN6,FAN4/5,VIN3 enabled, VIN7 internal 0x1423, // don't delay PoWeROK1/2 - triggers 2nd reset 0x9072, // watchdog triggers PWROK, counts seconds @@ -76,13 +79,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -101,7 +101,7 @@ void main(unsigned long bist) * Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/lippert/spacerunner-lx/romstage.c b/src/mainboard/lippert/spacerunner-lx/romstage.c index 59bd618..9d5539e 100644 --- a/src/mainboard/lippert/spacerunner-lx/romstage.c +++ b/src/mainboard/lippert/spacerunner-lx/romstage.c @@ -35,9 +35,13 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "northbridge/amd/lx/raminit.h" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) + /* Bit0 enables Spread Spectrum, bit1 makes on-board SSD act as IDE slave. */ #if CONFIG_ONBOARD_IDE_SLAVE #define SMC_CONFIG 0x03 @@ -118,7 +122,6 @@ static int smc_send_config(unsigned char config_data) #include "cpu/amd/geode_lx/msrinit.c" static const u16 sio_init_table[] = { // hi=data, lo=index - 0x0707, // select LDN 7 (GPIO, SPI, watchdog, ...) 0x072C, // VIN6 enabled, FAN4/5 disabled, VIN7,VIN3 internal 0x1423, // don't delay PoWeROK1/2 0x9072, // watchdog triggers PWROK, counts seconds @@ -140,13 +143,10 @@ static void mb_gpio_init(void) int i; /* Init Super I/O WDT, GPIOs. Done early, WDT init may trigger reset! */ - it8712f_enter_conf(); for (i = 0; i < ARRAY_SIZE(sio_init_table); i++) { - u16 val = sio_init_table[i]; - outb((u8)val, SIO_INDEX); - outb(val >> 8, SIO_DATA); + u16 reg = sio_init_table[i]; + ite_reg_write(GPIO_DEV, (u8) reg, (reg >> 8)); } - it8712f_exit_conf(); } void main(unsigned long bist) @@ -166,7 +166,7 @@ void main(unsigned long bist) * Note: Must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); mb_gpio_init(); console_init(); diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index 6ae4989..b8af354 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -35,7 +35,8 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" @@ -45,6 +46,8 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -103,8 +106,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if defined(DUMP_CMOS_RAM) && (DUMP_CMOS_RAM == 0) check_cmos(); // rebooting in case of corrupted cmos !!!!! #endif - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c index 632a311..551c060 100644 --- a/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c +++ b/src/mainboard/soyo/sy-6ba-plus-iii/romstage.c @@ -30,8 +30,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "cpu/x86/bist.h" -void it8671f_48mhz_clkin(void); -#include "superio/ite/it8671f/early_serial.c" +#include <superio/ite/it8671f/it8671f.h> #include <lib.h> #define SERIAL_DEV PNP_DEV(0x370, IT8671F_SP1) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index e6483c0..35351b1 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -32,12 +32,15 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -85,8 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 2f3ad71..7455df2 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -32,12 +32,15 @@ #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" -#include "superio/ite/it8712f/early_serial.c" +#include <superio/ite/common/ite.h> +#include <superio/ite/it8712f/it8712f.h> #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -80,8 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enable_rs690_dev8(); sb600_lpc_init(); - /* it8712f_enable_serial does not use its 1st parameter. */ - it8712f_enable_serial(0, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); console_init(); diff --git a/src/mainboard/via/pc2500e/romstage.c b/src/mainboard/via/pc2500e/romstage.c index e374cf9..b270350 100644 --- a/src/mainboard/via/pc2500e/romstage.c +++ b/src/mainboard/via/pc2500e/romstage.c @@ -32,6 +32,7 @@ #include "drivers/pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/via/vt8237r/early_smbus.c" +#include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <spd.h> @@ -59,7 +60,7 @@ void main(unsigned long bist) /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); - it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); smbus_fixup(&ctrl); diff --git a/src/superio/ite/Kconfig b/src/superio/ite/Kconfig index 4c0f927..8a5378d 100644 --- a/src/superio/ite/Kconfig +++ b/src/superio/ite/Kconfig @@ -2,6 +2,7 @@ ## This file is part of the coreboot project. ## ## Copyright (C) 2009 Ronald G. Minnich +## Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -17,24 +18,45 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +# Generic ITE romstage driver - Just enough UART initialisation code for +# romstage. +config SUPERIO_ITE_COMMON_ROMSTAGE + bool config SUPERIO_ITE_IT8661F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8671F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8712F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8716F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL bool depends on SUPERIO_ITE_IT8716F default n + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8718F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8721F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8728F bool + select SUPERIO_ITE_COMMON_ROMSTAGE + config SUPERIO_ITE_IT8772F bool + select SUPERIO_ITE_COMMON_ROMSTAGE diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index 2b71521..7e1c81b 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -17,6 +17,9 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +## include generic ite pre-ram stage driver +romstage-$(CONFIG_SUPERIO_ITE_COMMON_ROMSTAGE) += common/early_serial.c + subdirs-y += it8661f subdirs-y += it8671f subdirs-y += it8712f diff --git a/src/superio/ite/common/early_serial.c b/src/superio/ite/common/early_serial.c new file mode 100644 index 0000000..35fb59d --- /dev/null +++ b/src/superio/ite/common/early_serial.c @@ -0,0 +1,86 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> +#include "ite.h" + +/* Global configuration registers. */ +#define ITE_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ +#define ITE_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ +#define ITE_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ +#define ITE_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ + +/* Helper procedure */ +static void ite_sio_write(device_t dev, u8 reg, u8 value) +{ + pnp_set_logical_device(dev); + pnp_write_config(dev, reg, value); +} + +/* Enable configuration */ +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); +} + +/* Disable configuration */ +static void pnp_exit_conf_state(device_t dev) +{ + ite_sio_write(dev, ITE_CONFIG_REG_CC, 0x02); +} + +void ite_reg_write(device_t dev, u8 reg, u8 value) +{ + pnp_enter_conf_state(dev); + ite_sio_write(dev, reg, value); + pnp_exit_conf_state(dev); +} + + +/* + * in romstage.c + * #define CLKIN_DEV PNP_DEV(0x2e, ITE_GPIO) + * and pass: CLKIN_DEV + * ITE_UART_CLK_PREDIVIDE_24 + * ITE_UART_CLK_PREDIVIDE_48 (default) + */ +void ite_conf_clkin(device_t dev, u8 predivide) +{ + ite_reg_write(dev, ITE_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); +} + +/* Bring up early serial debugging output before the RAM is initialized. */ +void ite_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} diff --git a/src/superio/ite/common/ite.h b/src/superio/ite/common/ite.h new file mode 100644 index 0000000..f21381d --- /dev/null +++ b/src/superio/ite/common/ite.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_ITE_COMMON_ROMSTAGE_H +#define SUPERIO_ITE_COMMON_ROMSTAGE_H + +#include <arch/io.h> +#include <stdint.h> + +#define ITE_UART_CLK_PREDIVIDE_48 0x00 /* default */ +#define ITE_UART_CLK_PREDIVIDE_24 0x01 + +void ite_conf_clkin(device_t dev, u8 predivide); +void ite_enable_serial(device_t dev, u16 iobase); + +/* Some boards need to init wdt+gpio's very early */ +void ite_reg_write(device_t dev, u8 reg, u8 value); + +#endif /* SUPERIO_ITE_COMMON_ROMSTAGE_H */ diff --git a/src/superio/ite/it8671f/Makefile.inc b/src/superio/ite/it8671f/Makefile.inc index bb370ae..a9a4008 100644 --- a/src/superio/ite/it8671f/Makefile.inc +++ b/src/superio/ite/it8671f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8671F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c - diff --git a/src/superio/ite/it8671f/early_serial.c b/src/superio/ite/it8671f/early_serial.c index c2ba6e0..9f35b8a 100644 --- a/src/superio/ite/it8671f/early_serial.c +++ b/src/superio/ite/it8671f/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "it8671f.h" /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ @@ -87,7 +89,7 @@ void it8671f_48mhz_clkin(void) } /* Enable the serial port(s). */ -static void it8671f_enable_serial(device_t dev, u16 iobase) +void it8671f_enable_serial(device_t dev, u16 iobase) { it8671f_enter_conf(); diff --git a/src/superio/ite/it8671f/it8671f.h b/src/superio/ite/it8671f/it8671f.h index 52669f4..c3865ff 100644 --- a/src/superio/ite/it8671f/it8671f.h +++ b/src/superio/ite/it8671f/it8671f.h @@ -18,8 +18,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8671F_IT8671F_H -#define SUPERIO_ITE_IT8671F_IT8671F_H +#ifndef SUPERIO_ITE_IT8671F_H +#define SUPERIO_ITE_IT8671F_H + +#include <arch/io.h> +#include <stdint.h> /* Datasheet: Not available online, got it from ITE per request. */ @@ -30,4 +33,7 @@ #define IT8671F_KBCK 0x05 /* PS/2 keyboard */ #define IT8671F_KBCM 0x06 /* PS/2 mouse */ -#endif +void it8671f_48mhz_clkin(void); +void it8671f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_ITE_IT8671F__H */ diff --git a/src/superio/ite/it8712f/Makefile.inc b/src/superio/ite/it8712f/Makefile.inc index 3c8a512..ce75645 100644 --- a/src/superio/ite/it8712f/Makefile.inc +++ b/src/superio/ite/it8712f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8712F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c - diff --git a/src/superio/ite/it8712f/early_serial.c b/src/superio/ite/it8712f/early_serial.c index 51564fc..d678f3f 100644 --- a/src/superio/ite/it8712f/early_serial.c +++ b/src/superio/ite/it8712f/early_serial.c @@ -19,6 +19,8 @@ */ #include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> #include "it8712f.h" /* The base address is 0x2e or 0x4e, depending on config bytes. */ @@ -30,7 +32,6 @@ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ @@ -58,14 +59,6 @@ static void it8712f_exit_conf(void) it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } -/* Select 24MHz CLKIN (48MHz is the default). */ -void it8712f_24mhz_clkin(void) -{ - it8712f_enter_conf(); - it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); - it8712f_exit_conf(); -} - /* * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! * @@ -88,30 +81,3 @@ void it8712f_kill_watchdog(void) it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); it8712f_exit_conf(); } - -/* Enable the serial port(s). */ -void it8712f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8712f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8712f_exit_conf(); -} diff --git a/src/superio/ite/it8712f/it8712f.h b/src/superio/ite/it8712f/it8712f.h index 5ec6188..b40e473 100644 --- a/src/superio/ite/it8712f/it8712f.h +++ b/src/superio/ite/it8712f/it8712f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8712F_IT8712F_H -#define SUPERIO_ITE_IT8712F_IT8712F_H +#ifndef SUPERIO_ITE_IT8712F_H +#define SUPERIO_ITE_IT8712F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */ @@ -36,7 +36,6 @@ #define IT8712F_IR 0x0a /* Consumer IR */ void it8712f_kill_watchdog(void); -void it8712f_enable_serial(device_t dev, u16 iobase); -void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); -#endif + +#endif /* SUPERIO_ITE_IT8712F_H */ diff --git a/src/superio/ite/it8716f/Makefile.inc b/src/superio/ite/it8716f/Makefile.inc index 6b3c0ce..a11c2ab 100644 --- a/src/superio/ite/it8716f/Makefile.inc +++ b/src/superio/ite/it8716f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8716F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c diff --git a/src/superio/ite/it8716f/early_serial.c b/src/superio/ite/it8716f/early_serial.c deleted file mode 100644 index 2085a8f..0000000 --- a/src/superio/ite/it8716f/early_serial.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2007 AMD Written by Yinghai Lu <yinghai.lu(a)amd.com> for AMD. - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "it8716f.h" - -/* Global configuration registers. */ -#define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8716F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8716F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8716f_enter_conf(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8716f_exit_conf(device_t dev) -{ - pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); -} - -static void it8716f_reg_write(device_t dev, u8 index, u8 value) -{ - it8716f_enter_conf(dev); - pnp_write_config(dev, index, value); - it8716f_exit_conf(dev); -} - - -/* - * in romstage.c - * #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) - * and pass: CLKIN_DEV - * IT8716F_UART_CLK_PREDIVIDE_24 - * IT8716F_UART_CLK_PREDIVIDE_48 (default) - */ -void it8716f_conf_clkin(device_t dev, u8 predivide) -{ - it8716f_reg_write(dev, IT8716F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); -} - - -/* Enable the serial port(s). */ -void it8716f_enable_serial(device_t dev, u16 iobase) -{ - it8716f_enter_conf(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - it8716f_exit_conf(dev); -} diff --git a/src/superio/ite/it8716f/it8716f.h b/src/superio/ite/it8716f/it8716f.h index 37b8b65..bbf5708 100644 --- a/src/superio/ite/it8716f/it8716f.h +++ b/src/superio/ite/it8716f/it8716f.h @@ -21,7 +21,6 @@ #ifndef SUPERIO_ITE_IT8716F_H #define SUPERIO_ITE_IT8716F_H -#include <device/pnp.h> #include <stdint.h> /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ @@ -39,12 +38,6 @@ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ -#define IT8716F_UART_CLK_PREDIVIDE_48 0x00 /* default */ -#define IT8716F_UART_CLK_PREDIVIDE_24 0x01 - -void it8716f_conf_clkin(device_t dev, u8 predivide); -void it8716f_enable_serial(device_t dev, u16 iobase); - #if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL /* Provided by mainboard, called by IT8716F superio.c. */ void init_ec(u16 base); diff --git a/src/superio/ite/it8718f/Makefile.inc b/src/superio/ite/it8718f/Makefile.inc index c433e3c..14e2822 100644 --- a/src/superio/ite/it8718f/Makefile.inc +++ b/src/superio/ite/it8718f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_ITE_IT8718F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c - diff --git a/src/superio/ite/it8718f/early_serial.c b/src/superio/ite/it8718f/early_serial.c index 308b67c..deef840 100644 --- a/src/superio/ite/it8718f/early_serial.c +++ b/src/superio/ite/it8718f/early_serial.c @@ -30,7 +30,6 @@ #define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ #define IT8718F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ #define IT8718F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */ -#define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ static void it8718f_sio_write(u8 ldn, u8 index, u8 value) @@ -56,13 +55,6 @@ static void it8718f_exit_conf(void) it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); } -/* Select 24MHz CLKIN (48MHz default). */ -void it8718f_24mhz_clkin(void) -{ - it8718f_enter_conf(); - it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); - it8718f_exit_conf(); -} /* * GIGABYTE uses a special Super I/O register to protect its Dual BIOS @@ -75,30 +67,3 @@ void it8718f_disable_reboot(void) it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); it8718f_exit_conf(); } - -/* Enable the serial port(s). */ -void it8718f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8718f_enter_conf(); - - /* (2) Modify the data of configuration registers. */ - - /* - * Select the chip to configure (if there's more than one). - * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - * If this register is not written, both chips are configured. - */ - - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ - - /* Enable serial port(s). */ - it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Clear software suspend mode (clear bit 0). TODO: Needed? */ - /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ - - /* (3) Exit the configuration state (MB PnP mode). */ - it8718f_exit_conf(); -} diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 527d1c2..018f08a 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_ITE_IT8718F_IT8718F_H -#define SUPERIO_ITE_IT8718F_IT8718F_H +#ifndef SUPERIO_ITE_IT8718F_H +#define SUPERIO_ITE_IT8718F_H /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */ @@ -34,9 +34,7 @@ #define IT8718F_IR 0x0a /* Consumer IR */ #if defined(__PRE_RAM__) -void it8718f_24mhz_clkin(void); void it8718f_disable_reboot(void); -void it8718f_enable_serial(device_t dev, u16 iobase); #endif -#endif +#endif /* SUPERIO_ITE_IT8718F_H */ diff --git a/src/superio/ite/it8721f/Makefile.inc b/src/superio/ite/it8721f/Makefile.inc index ef616f4..4b1aa96 100644 --- a/src/superio/ite/it8721f/Makefile.inc +++ b/src/superio/ite/it8721f/Makefile.inc @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -romstage-$(CONFIG_SUPERIO_ITE_IT8721F) += early_serial.c ramstage-$(CONFIG_SUPERIO_ITE_IT8721F) += superio.c diff --git a/src/superio/ite/it8721f/early_serial.c b/src/superio/ite/it8721f/early_serial.c deleted file mode 100644 index df66222..0000000 --- a/src/superio/ite/it8721f/early_serial.c +++ /dev/null @@ -1,85 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2011 QingPei Wang <wangqingpei(a)gmail.com> - * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include <stdint.h> -#include "it8721f.h" - -/* Global configuration registers. */ -#define IT8721F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8721F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8721F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ -#define IT8721F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ - -static void it8721f_sio_write(device_t dev, u8 index, u8 value) -{ - pnp_set_logical_device(dev); - pnp_write_config(dev, index, value); -} - -static void it8721f_enter_conf(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8721f_exit_conf(device_t dev) -{ - it8721f_sio_write(dev, IT8721F_CONFIG_REG_CC, 0x02); -} - -static void it8721f_reg_write(device_t dev, u8 index, u8 value) -{ - it8721f_enter_conf(dev); - it8721f_sio_write(dev, index, value); - it8721f_exit_conf(dev); -} - - -/* - * in romstage.c - * #define CLKIN_DEV PNP_DEV(0x2e, IT8721F_GPIO) - * and pass: CLKIN_DEV - * IT8721F_UART_CLK_PREDIVIDE_24 - * IT8721F_UART_CLK_PREDIVIDE_48 (default) - */ -void it8721f_conf_clkin(device_t dev, u8 predivide) -{ - it8721f_reg_write(dev, IT8721F_CONFIG_REG_CLOCKSEL, (0x1 & predivide)); -} - - -/* Enable the serial port(s). */ -void it8721f_enable_serial(device_t dev, u16 iobase) -{ - it8721f_enter_conf(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - it8721f_exit_conf(dev); -} diff --git a/src/superio/ite/it8721f/it8721f.h b/src/superio/ite/it8721f/it8721f.h index 9d5a528..ce794cf 100644 --- a/src/superio/ite/it8721f/it8721f.h +++ b/src/superio/ite/it8721f/it8721f.h @@ -36,10 +36,4 @@ #define IT8721F_GPIO 0x07 /* GPIO */ #define IT8721F_IR 0x0a /* Consumer IR */ -#define IT8721F_UART_CLK_PREDIVIDE_48 0x00 /* default */ -#define IT8721F_UART_CLK_PREDIVIDE_24 0x01 - -void it8721f_conf_clkin(device_t dev, u8 predivide); -void it8721f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_ITE_IT8721F_H */ diff --git a/src/superio/ite/it8728f/Makefile.inc b/src/superio/ite/it8728f/Makefile.inc deleted file mode 100644 index d8d4f6a..0000000 --- a/src/superio/ite/it8728f/Makefile.inc +++ /dev/null @@ -1,21 +0,0 @@ -## -## This file is part of the coreboot project. -## -## Copyright (C) 2013 Damien Zammit <damien(a)zamaudio.com> -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; either version 2 of the License, or -## (at your option) any later version. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -romstage-$(CONFIG_SUPERIO_ITE_IT8728F) += early_serial.c diff --git a/src/superio/ite/it8728f/early_serial.c b/src/superio/ite/it8728f/early_serial.c deleted file mode 100644 index c2632ef..0000000 --- a/src/superio/ite/it8728f/early_serial.c +++ /dev/null @@ -1,74 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2006 Uwe Hermann <uwe(a)hermann-uwe.de> - * Copyright (C) 2013 Damien Zammit <damien(a)zamaudio.com> - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <arch/io.h> -#include <device/pnp.h> -#include "it8728f.h" - -/* Superio raw commands */ -static void it8728f_sio_write(device_t dev, u8 index, u8 value) -{ - pnp_set_logical_device(dev); - pnp_write_config(dev, index, value); -} - -static void it8728f_enter_conf(device_t dev) -{ - u16 port = dev >> 8; - - outb(0x87, port); - outb(0x01, port); - outb(0x55, port); - outb((port == 0x4e) ? 0xaa : 0x55, port); -} - -static void it8728f_exit_conf(device_t dev) -{ - it8728f_sio_write(dev, IT8728F_CONFIG_REG_CC, 0x02); -} - -/* Superio low level commands */ -void it8728f_reg_write(device_t dev, u8 index, u8 value) -{ - it8728f_enter_conf(dev); - it8728f_sio_write(dev, index, value); - it8728f_exit_conf(dev); -} - -void it8728f_24mhz_clkin(device_t dev) -{ - it8728f_reg_write(dev, IT8728F_CONFIG_REG_CLOCKSEL, 0x1); -} - -void it8728f_enable_serial(device_t dev, u16 iobase) -{ - /* (1) Enter the configuration state (MB PnP mode). */ - it8728f_enter_conf(dev); - - /* (2) Modify the data of configuration registers. */ - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_set_iobase(dev, PNP_IDX_IO0, iobase); - pnp_set_enable(dev, 1); - - /* (3) Exit the configuration state (MB PnP mode). */ - it8728f_exit_conf(dev); -} diff --git a/src/superio/ite/it8728f/it8728f.h b/src/superio/ite/it8728f/it8728f.h index 55bdf69..8a7e8b2 100644 --- a/src/superio/ite/it8728f/it8728f.h +++ b/src/superio/ite/it8728f/it8728f.h @@ -39,16 +39,4 @@ #define IT8728F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8728F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. 'Special register' */ -/* - * Superio low level commands - * Pass dev = PNP_DEV(superiobase, LDN) - */ -void it8728f_reg_write(device_t dev, u8 index, u8 value); - -/* Select 24MHz CLKIN (48MHz default). */ -void it8728f_24mhz_clkin(device_t dev); - -/* Enable the serial port(s). */ -void it8728f_enable_serial(device_t dev, u16 iobase); - #endif /* SUPERIO_ITE_IT8728F_H */

1 0

Patch merged into coreboot/master: a3b06c9 Arch-level Kconfig menu cleanup
by gerrit＠coreboot.org 10 May '14

10 May '14

the following patch was just integrated into master: commit a3b06c99d066600c3462fe5fdebc5006cb9631ea Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 6 18:00:19 2014 -0700 Arch-level Kconfig menu cleanup Remove arch-level Kconfig menu option as it shows all available architectures in make menuconfig. Instead pull the bootblock options for choice and update image to top-level Kconfig since it is already present for both x86 and arm. Change-Id: Iab9c4539f05cd54a7f751565fefcaf7b6f0edc86 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: http://review.coreboot.org/5673 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5673 for details. -gerrit

1 0

Patch set updated for coreboot: 429a6bb buildsystem: use more granular dependencies
by Patrick Georgi 10 May '14

10 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5485 -gerrit commit 429a6bbc087b6d791d4269afb3d9ed34da1cbf54 Author: Patrick Georgi <patrick.georgi(a)secunet.com> Date: Fri Apr 11 13:25:48 2014 +0200 buildsystem: use more granular dependencies Filter generated dependencies so they don't point to config.h but to individual files for each Kconfig symbol (as emitted by the kconf tools). FIXME: uses $(CC) which might not be what we want anymore. Also: create separate dependency files for rom/ramstage/smm/...? Change-Id: I061bcef62fd9b556be84557080a47766981cffaf Signed-off-by: Patrick Georgi <patrick.georgi(a)secunet.com> --- Makefile | 7 ++++++- Makefile.inc | 33 ++++++++++++++++++++++++++++++--- util/fixdep/fixdep | 19 +++++++++++++++++++ util/fixdep/gen_fixdep_cache | 27 +++++++++++++++++++++++++++ 4 files changed, 82 insertions(+), 4 deletions(-) diff --git a/Makefile b/Makefile index c9648c0..a8dcda0 100644 --- a/Makefile +++ b/Makefile @@ -240,9 +240,14 @@ define create_cc_template # $4 additional dependencies ifn$(EMPTY)def $(1)-objs_$(2)_template de$(EMPTY)fine $(1)-objs_$(2)_template +$(obj)/$$(1).$(1).d: src/$$(1).$(2) $(obj)/config.h $(4) + mkdir -p $$$$(dir $$$$@) + $(CC) $(3) $$$$(CFLAGS) -MM $$$$< | \ + util/fixdep/fixdep $(FIXDEP_CACHE) $(obj)/config.h $(obj)/config/ > $$$$@ + $(obj)/$$(1).$(1).o: src/$$(1).$(2) $(obj)/config.h $(4) @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" - $(CC_$(1)) $(3) -MMD $$$$(CFLAGS_$(1)) -c -o $$$$@ $$$$< + $(CC_$(1)) $(3) $$$$(CFLAGS_$(1)) -c -o $$$$@ $$$$< en$(EMPTY)def end$(EMPTY)if endef diff --git a/Makefile.inc b/Makefile.inc index 3205a10..7949b35 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -309,9 +309,36 @@ $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devi ramstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c romstage-y+=$(obj)/mainboard/$(MAINBOARDDIR)/static.c +FIXDEP_CACHE = .fixdep_cache + +-include $(FIXDEP_CACHE).d + +$(FIXDEP_CACHE): + util/fixdep/gen_fixdep_cache Kconfig $@ "" > $@.d + +$(objutil)/%.d: $(objutil)/%.c $(FIXDEP_CACHE) + mkdir -p $(dir $@) + $(HOSTCC) -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -MM $< | \ + util/fixdep/fixdep $(FIXDEP_CACHE) $(obj)/config.h $(obj)/config/ > $@ + +$(obj)/%.ramstage.d $(abspath $(obj))/%.ramstage.d: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + mkdir -p $(dir $@) + $(CC) $(CFLAGS) -MM $< | \ + util/fixdep/fixdep $(FIXDEP_CACHE) $(obj)/config.h $(obj)/config/ > $@ + +$(obj)/%.romstage.d $(abspath $(obj))/%.romstage.d: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + mkdir -p $(dir $@) + $(CC) $(CFLAGS) -MM $< | \ + util/fixdep/fixdep $(FIXDEP_CACHE) $(obj)/config.h $(obj)/config/ > $@ + +$(obj)/%.bootblock.d $(abspath $(obj))/%.bootblock.d: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + mkdir -p $(dir $@) + $(CC) $(bootblock-c-ccopts) $(CFLAGS) -MM $< | \ + util/fixdep/fixdep $(FIXDEP_CACHE) $(obj)/config.h $(obj)/config/ > $@ + $(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" - $(HOSTCC) -MMD -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $< + $(HOSTCC) -I$(subst $(objutil)/,util/,$(dir $<)) -I$(dir $<) $(HOSTCFLAGS) -c -o $@ $< $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" @@ -319,11 +346,11 @@ $(obj)/%.ramstage.o $(abspath $(obj))/%.ramstage.o: $(obj)/%.c $(obj)/config.h $ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_romstage) -MMD -D__PRE_RAM__ $(CFLAGS_romstage) -c -o $@ $< + $(CC_romstage) -D__PRE_RAM__ $(CFLAGS_romstage) -c -o $@ $< $(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC_bootblock) -MMD $(bootblock-c-ccopts) $(CFLAGS_bootblock) -c -o $@ $< + $(CC_bootblock) $(bootblock-c-ccopts) $(CFLAGS_bootblock) -c -o $@ $< ####################################################################### # Clean up rules diff --git a/util/fixdep/fixdep b/util/fixdep/fixdep new file mode 100755 index 0000000..b20c1e6 --- /dev/null +++ b/util/fixdep/fixdep @@ -0,0 +1,19 @@ +#!/bin/bash +# copyright (C) 2014 secunet Security Networks AG +# written by Patrick Georgi <patrick.georgi(a)secunet.com> +# Licensed under GPL-v2 +# +# $1: fixdep cache +# $2: config header to prune +# $3: prefix to kconfig includes +# stdin: dependency rule to prune +# stdout: pruned dependency rule + +source $1 + +LINE=$(cat | sed 's,\\$,,' |tr -d '\012') +PRE=$(echo $LINE|cut -d: -f1) +POST=$(echo $LINE|cut -d: -f2- | sed "s,\<$2\>,,") + +printf "$PRE: $POST " +grep -whEo "$SYMBOL_RULE" $POST |sed "s,^$KCONFIG_PREFIX,," |sort -u |tr 'A-Z_' 'a-z/' | sed "s,^.*\$,$3&.h," | tr '\012' ' ' diff --git a/util/fixdep/gen_fixdep_cache b/util/fixdep/gen_fixdep_cache new file mode 100755 index 0000000..0923147 --- /dev/null +++ b/util/fixdep/gen_fixdep_cache @@ -0,0 +1,27 @@ +#!/bin/bash +# copyright (C) 2014 secunet Security Networks AG +# written by Patrick Georgi <patrick.georgi(a)secunet.com> +# Licensed under GPL-v2 +# +# $1: root Kconfig file +# $2: cache filename +# $3: Kconfig prefix (normally CONFIG_) +# stdout: rule to regenerate cache +OLD_KCONFIGS="" +KCONFIGS=$1 + +# collect all Kconfig files, avoid endless loops +while [ "$OLD_KCONFIGS" != "$KCONFIGS" ]; do + OLD_KCONFIGS=$KCONFIGS + KCONFIGS="$KCONFIGS $(sed '/\<source\>/ {s,.*\<source\> \"*$[^ \"]*$.*,\1,; p}; d' $OLD_KCONFIGS)" + KCONFIGS="$(echo $KCONFIGS |tr ' ' '\012' |sort -u)" + KCONFIGS="$(ls -d $KCONFIGS 2>/dev/null )" +done +SYMBOLS=$(sed "{s,#.*$,,; /^[[:space:]]*config[[:space:]]*[[:alnum:]_][[:alnum:]_]*[[:space:]]*$/ {s,^[[:space:]]*config[[:space:]]*,$3,; p} };d" $KCONFIGS | sort -u) + +echo "KCONFIG_PREFIX=$3" > $2 +printf "SYMBOL_RULE='($SYMBOLS)'" |tr '\012' '|' >> $2 +echo "" >> $2 + +echo "$2: $KCONFIGS" | tr '\012' ' ' +echo ""

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coreboot-gerrit May 2014