coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch set updated for coreboot: 2b6d7da baytrail: Enable PCIe common clock and ASPM
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5051 -gerrit commit 2b6d7daec5b83c49a254aadcb8d7e9e3ddca1562 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jan 16 11:18:36 2014 -0800 baytrail: Enable PCIe common clock and ASPM Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints. BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock: lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182860 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 9a3fa92..a93b487 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -24,6 +24,8 @@ config CPU_SPECIFIC_OPTIONS select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK select SMM_MODULES select SMM_TSEG select SMP

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Patch set updated for coreboot: 2acfe31 baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5048 -gerrit commit 2acfe314b1cdafaf494afd8878618bb98646a68c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 14 17:34:10 2014 -0600 baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED On baytrail, it appears that the turbo disable setting is actually building-block scoped. One can see this on quad core parts where if enable_turbo() is called only on the BSP then only cpus 0 and 1 have turbo enabled. Fix this by calling enable_turbo() on all non-bsp cpus. BUG=chrome-os-partner:25014 BRANCH=baytrail TEST=Built and booted rambi. All cpus have bit 38 set to 0 in msr 0x1a0. Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182406 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Kconfig | 1 + src/soc/intel/baytrail/cpu.c | 9 ++++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 969fa15..9a3fa92 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -14,6 +14,7 @@ config CPU_SPECIFIC_OPTIONS select CACHE_MRC_SETTINGS select CAR_MIGRATION select COLLECT_TIMESTAMPS + select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select CPU_MICROCODE_IN_CBFS select DYNAMIC_CBMEM select HAVE_MONOTONIC_TIMER diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 3ae297c..15efab9 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -92,7 +92,7 @@ void baytrail_init_cpus(device_t dev) /* Set package MSRs */ reg_script_run(package_msr_script); - /* Enable Turbo/Burst Mode */ + /* Enable Turbo Mode on BSP and siblings of the BSP's building block. */ enable_turbo(); if (mp_init(cpu_bus, &mp_params)) { @@ -104,6 +104,13 @@ static void baytrail_core_init(device_t cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); + /* On bay trail the turbo disable bit is actually scoped at building + * block level -- not package. For non-bsp cores that are within a + * building block enable turbo. The cores within the BSP's building + * block will just see it already enabled and move on. */ + if (lapicid()) + enable_turbo(); + /* Set core MSRs */ reg_script_run(core_msr_script);

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Patch set updated for coreboot: 891a151 rambi: Add ACPI devices and interrupts for codec and ALS
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5049 -gerrit commit 891a1519bb4b863d8b70708a95ad420b6796050a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 13 16:37:51 2014 -0800 rambi: Add ACPI devices and interrupts for codec and ALS The Codec and ALS both have interrupt sources that can be configured. The ALS kernel driver currently does not try to use it but the codec driver does for things like jack detect. ACPI Devices are added, but as with other ACPI devices the HID may need to be updated once more official strings are decided. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual: build and boot on rambi and check for functional lightsensor Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182366 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/acpi/mainboard.asl | 80 +++++++++++++++++++++++++++ src/mainboard/google/rambi/gpio.c | 6 +- src/mainboard/google/rambi/irqroute.h | 7 +++ src/mainboard/google/rambi/onboard.h | 2 + 4 files changed, 93 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 9b16272..501bbf7 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -205,6 +205,86 @@ Scope (\_SB.I2C1) } } +Scope (\_SB.I2C2) +{ + Device (CODC) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Maxim Integrated + * PCI Vendor ID 193Ch and a shortened device identifier. + */ + Name (_HID, "193C9890") + Name (_DDN, "Maxim 98090 Codec") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x10, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.I2C2", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_CODEC_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S2EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + +Scope (\_SB.I2C5) +{ + Device (ALSI) + { + /* + * TODO(dlaurie): Need official HID. + * + * The current HID is created from the Intersil PNP + * Vendor ID "LSD" and a shortened device identifier. + */ + Name (_HID, EisaId ("LSD2918")) + Name (_DDN, "Intersil 29018 Ambient Light Sensor") + Name (_UID, 1) + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x44, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.I2C5", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_ALS_IRQ + } + }) + + Method (_STA) + { + If (LEqual (\S5EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + } +} + Scope (\_SB.I2C6) { Device (ATSB) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index 281709a..d551a15 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -126,7 +126,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */ GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */ GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */ - GPIO_INPUT, /* S0-SC070 - ALS_INT_L - INT */ + GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */ GPIO_NC, /* S0-SC071 - NC */ GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */ GPIO_NC, /* S0-SC073 - NC */ @@ -172,7 +172,7 @@ static const struct soc_gpio_map gpssus_gpio_map[] = { GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */ GPIO_NC, /* S508 - NC */ - GPIO_NC, /* S509 - MUX_AUD_INT1# (NC) */ + GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */ GPIO_FUNC0, /* S511 - SUSPWRDNACK */ GPIO_FUNC0, /* S512 - WIFI_SUSCLK */ @@ -214,9 +214,11 @@ static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = { [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO, [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO, [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO, + [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO, }; static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = { + [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO, }; static struct soc_gpio_config gpio_config = { diff --git a/src/mainboard/google/rambi/irqroute.h b/src/mainboard/google/rambi/irqroute.h index 3e1d1a9..7339793 100644 --- a/src/mainboard/google/rambi/irqroute.h +++ b/src/mainboard/google/rambi/irqroute.h @@ -50,7 +50,14 @@ #define TPAD_IRQ_OFFSET 0 #define TOUCH_IRQ_OFFSET 1 #define I8042_IRQ_OFFSET 2 +#define ALS_IRQ_OFFSET 3 /* Corresponding SCORE GPIO pins */ #define TPAD_IRQ_GPIO 55 #define TOUCH_IRQ_GPIO 72 #define I8042_IRQ_GPIO 101 +#define ALS_IRQ_GPIO 70 + +/* SUS bank DIRQs - up to 16 supported */ +#define CODEC_IRQ_OFFSET 0 +/* Corresponding SUS GPIO pins */ +#define CODEC_IRQ_GPIO 9 diff --git a/src/mainboard/google/rambi/onboard.h b/src/mainboard/google/rambi/onboard.h index 7f5d885..8fb7a3f 100644 --- a/src/mainboard/google/rambi/onboard.h +++ b/src/mainboard/google/rambi/onboard.h @@ -35,5 +35,7 @@ #define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */ #define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET) +#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET) +#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET) #endif

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Patch set updated for coreboot: f7020c7 baytrail: Add SOC thermal settings
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5052 -gerrit commit f7020c7525dd97ea4e5b860058dfa05dbed84e37 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jan 16 09:47:39 2014 -0800 baytrail: Add SOC thermal settings Apply the SOC thermal settings from DPTF reference code for SdpProfile=4 and adjust graphics PUNIT setting to match. BUG=chrome-os-partner:17279 BRANCH=baytrail TEST=boot on rambi and check for valid GPU power values from DPTF Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182786 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/baytrail/iosf.h | 18 ++++++++++++ src/soc/intel/baytrail/dptf.c | 54 ++++++++++++++++++++++++++++++++++ src/soc/intel/baytrail/gfx.c | 2 +- 4 files changed, 74 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index 974d33d..f93435b 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -44,6 +44,7 @@ ramstage-y += emmc.c ramstage-y += lpss.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += dptf.c ramstage-y += perf_power.c ramstage-y += stage_cache.c romstage-y += stage_cache.c diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 8cbe67a..e936072 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -240,6 +240,24 @@ void iosf_ssus_write(int reg, uint32_t val); #define PUNIT_PWRGT_STATUS 0x61 #define PUNIT_GPU_EC_VIRUS 0xd2 +#define PUNIT_SOC_POWER_BUDGET 0x02 +#define PUNIT_SOC_ENERGY_CREDIT 0x03 +#define PUNIT_PTMC 0x80 +#define PUNIT_GFXT 0x88 +#define PUNIT_VEDT 0x89 +#define PUNIT_ISPT 0x8c +#define PUNIT_PTPS 0xb2 +#define PUNIT_TE_AUX0 0xb5 +#define PUNIT_TE_AUX1 0xb6 +#define PUNIT_TE_AUX2 0xb7 +#define PUNIT_TE_AUX3 0xb8 +#define PUNIT_TTE_VRIccMax 0xb9 +#define PUNIT_TTE_VRHot 0xba +#define PUNIT_TTE_XXPROCHOT 0xbb +#define PUNIT_TTE_SLM0 0xbc +#define PUNIT_TTE_SLM1 0xbd +#define PUNIT_TTE_SWT 0xbf + /* * LPSS Registers */ diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c new file mode 100644 index 0000000..691e220 --- /dev/null +++ b/src/soc/intel/baytrail/dptf.c @@ -0,0 +1,54 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <bootstate.h> +#include <console/console.h> +#include <reg_script.h> +#include <baytrail/iosf.h> + +static const struct reg_script dptf_init_settings[] = { + /* SocThermInit */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029), + /* ratio 10 = 1333mhz for 2.5W fanless */ + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000A00), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002), + REG_SCRIPT_END, +}; + +static void dptf_init(void *unused) +{ + printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n"); + reg_script_run(dptf_init_settings); +} + +BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { + BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), +}; diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 4ed08c9..9207cfe 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -142,7 +142,7 @@ static const struct reg_script gfx_init_script[] = { /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ /* SDP Profile 4 == 0x11940, others 0xcf08 */ - REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0x11940), /* GfxPause */ REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),

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Patch merged into coreboot/master: f6ba9f6 mainboard/lenovo/t520: too many arguments to pc_keyboard_init
by gerrit＠coreboot.org 14 May '14

14 May '14

the following patch was just integrated into master: commit f6ba9f6a65cb737ed59d72cf2cdc6c942036fdb6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 20:49:43 2014 +1000 mainboard/lenovo/t520: too many arguments to pc_keyboard_init Fix build regression introduced in: a823f9b mainboard/lenovo: Add Lenovo Thinkpad T520 support Change-Id: I60d92f8cceda6427f43e6be9d78c2af82af4b061 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/5738 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5738 for details. -gerrit

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New patch to review for coreboot: 0077bfc mainboard/lenovo/t520: too many arguments to pc_keyboard_init
by Edward O'Callaghan 14 May '14

14 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5738 -gerrit commit 0077bfc00c4823abdd619cb287b019cf2e1c8b8e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 20:49:43 2014 +1000 mainboard/lenovo/t520: too many arguments to pc_keyboard_init Fix build regression introduced in: a823f9b mainboard/lenovo: Add Lenovo Thinkpad T520 support Change-Id: I60d92f8cceda6427f43e6be9d78c2af82af4b061 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/t520/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/t520/mainboard.c b/src/mainboard/lenovo/t520/mainboard.c index e387a9f..c213791 100644 --- a/src/mainboard/lenovo/t520/mainboard.c +++ b/src/mainboard/lenovo/t520/mainboard.c @@ -158,7 +158,7 @@ static void mainboard_init(device_t dev) RCBA32(0x38c4) = 0x00802005; RCBA32(0x38c0) = 0x00000007; - pc_keyboard_init(0); + pc_keyboard_init(); /* Enable expresscard hotplug events. */ pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 2)),

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New patch to review for coreboot: aa6848f mainboard/*: Convert to generic ITE superio romstage component
by Edward O'Callaghan 14 May '14

14 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5737 -gerrit commit aa6848f086609ae7e7ba9b8c02155cc4d287e64a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 19:15:08 2014 +1000 mainboard/*: Convert to generic ITE superio romstage component NOTFORMERGE Convert mainboard's that use model specific romstage functions of it8712f to the generic framework by following the reasoning of: HASHHERE ite/common: Introduce common watchdog and 3.3V VSB helpers Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/m2v-mx_se/romstage.c | 4 ++-- src/mainboard/asus/m2v/romstage.c | 4 ++-- src/mainboard/asus/m4a78-em/romstage.c | 2 +- src/mainboard/asus/m4a785-m/romstage.c | 2 +- src/mainboard/technexion/tim5690/romstage.c | 2 +- src/mainboard/technexion/tim8690/romstage.c | 2 +- 6 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index 0085bb4..92ff34e 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -129,8 +129,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); - it8712f_enable_3vsbsw(); + ite_kill_watchdog(); + ite_enable_3vsbsw(); console_init(); enable_rom_decode(); diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index acf8f91..3bbfb28 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -227,12 +227,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) ite_conf_clkin(CLKIN_DEV, ITE_UART_CLK_PREDIVIDE_24); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); enable_rom_decode(); m2v_bus_init(); m2v_it8712f_gpio_init(); - it8712f_enable_3vsbsw(); + ite_enable_3vsbsw(); printk(BIOS_INFO, "now booting... \n"); diff --git a/src/mainboard/asus/m4a78-em/romstage.c b/src/mainboard/asus/m4a78-em/romstage.c index 93810d2..38f97b0 100644 --- a/src/mainboard/asus/m4a78-em/romstage.c +++ b/src/mainboard/asus/m4a78-em/romstage.c @@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); diff --git a/src/mainboard/asus/m4a785-m/romstage.c b/src/mainboard/asus/m4a785-m/romstage.c index b360636..14665eb 100644 --- a/src/mainboard/asus/m4a785-m/romstage.c +++ b/src/mainboard/asus/m4a785-m/romstage.c @@ -99,7 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb7xx_51xx_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 35351b1..fa37395 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -89,7 +89,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init(); diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index 7455df2..9010c4b 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -84,7 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb600_lpc_init(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); + ite_kill_watchdog(); console_init();

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Patch merged into coreboot/master: a6130fc intel: Drop obsolete comments on MTRR usage
by gerrit＠coreboot.org 14 May '14

14 May '14

the following patch was just integrated into master: commit a6130fc8f9c00e0c545389b4e407f0b745435a56 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 12 15:00:03 2014 +0300 intel: Drop obsolete comments on MTRR usage Problem with UMA region allocation was fixed when MTRRs changed to use memrange implementation. Change-Id: I420dac30de2836a91596d81f88bb45b46f248532 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/5719 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)google.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5719 for details. -gerrit

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New patch to review for coreboot: 0aa879e vendorcode/.../fsp/baytrail: remove duplicate prototype
by Martin Roth 13 May '14

13 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5736 -gerrit commit 0aa879ee4bef5b18d61aa3c4a1024ce8a4e4a5dc Author: Martin Roth <gaumless(a)gmail.com> Date: Tue May 13 14:33:37 2014 -0600 vendorcode/.../fsp/baytrail: remove duplicate prototype There were two copies of the GetFspReservedMemoryFromGuid prototype in the fspplatform.h file for some reason. Change-Id: Id121f1e3ddf5aad28b954c873c93f921ce35624f Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/vendorcode/intel/fsp/baytrail/include/fspplatform.h | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h index 1b5fca1..97845d4 100644 --- a/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h +++ b/src/vendorcode/intel/fsp/baytrail/include/fspplatform.h @@ -75,11 +75,4 @@ GetLowMemorySize ( uint32_t *LowMemoryLength ); -void -GetFspReservedMemoryFromGuid ( - uint32_t *FspMemoryBase, - uint32_t *FspMemoryLength, - EFI_GUID FspReservedMemoryGuid - ); - #endif \ No newline at end of file

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New patch to review for coreboot: 0a65c6a add rtc_init() to romstage
by Martin Roth 13 May '14

13 May '14

Martin Roth (martin.roth(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5735 -gerrit commit 0a65c6a9e204fdfa24fb4da0e84e38b9d269ba39 Author: Martin Roth <gaumless(a)gmail.com> Date: Mon May 12 21:52:54 2014 -0600 add rtc_init() to romstage The FSP clears the bit that tells us whether or not the RTC has lost power when it sets up memory. Because of this, we need to initialize the RTC in romstage instead of ramstage. Change-Id: I158e4339fc539d32cfb2428042df6156d312a5f4 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- src/drivers/pc80/Kconfig | 6 ++++++ src/drivers/pc80/Makefile.inc | 1 + 2 files changed, 7 insertions(+) diff --git a/src/drivers/pc80/Kconfig b/src/drivers/pc80/Kconfig index 485dd64..aa605cc 100644 --- a/src/drivers/pc80/Kconfig +++ b/src/drivers/pc80/Kconfig @@ -23,3 +23,9 @@ config TPM Enable this option to enable TPM support in coreboot. If unsure, say N. + +config ROMSTAGE_RTC_INIT + bool + default n + help + Enable this option to use rtc_init() in romstage diff --git a/src/drivers/pc80/Makefile.inc b/src/drivers/pc80/Makefile.inc index 4d0a280..2e264ab 100644 --- a/src/drivers/pc80/Makefile.inc +++ b/src/drivers/pc80/Makefile.inc @@ -1,4 +1,5 @@ ramstage-y += mc146818rtc.c +romstage-$(CONFIG_ROMSTAGE_RTC_INIT) += mc146818rtc.c ramstage-y += isa-dma.c ramstage-y += i8254.c ramstage-y += i8259.c

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coreboot-gerrit May 2014