Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5040
-gerrit
commit 4ddf62c203bd28b8dcdaf5644609cf2f7b526fa7
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 9 14:35:41 2014 -0600
baytrail: reboot with EC in S0 with no MRC cache and EC in RW
This improves boot time in 2 ways for a firmware upgrade:
1. Normally MRC would detect the S0 state without an MRC cache
even though it's told to the S5 path. When it observes this
state a cold reset occurs. The cold reset stays in S5 for
at least 4 seconds which is time observed by the end user.
2. As the EC was running RW code before the reset after firmware
upgrade it will still be running the older RW code. Vboot will
then reboot the EC and the whole system to put the EC into RO
mode so it can handle the RW update.
The issues are mitigated by detecting the system is in S0 with
no MRC cache and the EC isn't in RO mode. Therefore we can do the
reboot without waiting the 4 secs and the EC is running RO so
the 2nd reboot is not necessary.
BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Booted. Updated firmware while in OS. Rebooted. Noted the
EC reboot before MRC execution.
Change-Id: I1c53d334a5e18c237a74ffbe96f263a7540cd8fe
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182061
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/soc/intel/baytrail/romstage/raminit.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c
index 352b86f..752a49b 100644
--- a/src/soc/intel/baytrail/romstage/raminit.c
+++ b/src/soc/intel/baytrail/romstage/raminit.c
@@ -32,6 +32,8 @@
#include <baytrail/pci_devs.h>
#include <baytrail/reset.h>
#include <baytrail/romstage.h>
+#include <ec/google/chromeec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
static void reset_system(void)
{
@@ -131,6 +133,12 @@ void raminit(struct mrc_params *mp, int prev_sleep_state)
reset_system();
} else {
printk(BIOS_DEBUG, "No MRC cache found.\n");
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ if (prev_sleep_state == 0) {
+ /* Ensure EC is running RO firmware. */
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+#endif
}
mrc_entry = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab,
Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5039
-gerrit
commit bbde1bc8635afb952735cae45eff6903aed1a506
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jan 9 14:28:05 2014 -0600
chromeec: add function to reboot on unexpected image
It's helpful to have a generic function that will tell
the EC to reboot if the EC isn't running a specified
image. Add that and implement google_chromeec_early_init()
to utilize the new function still maintaing its semantics
of if recvoery mode is enabled the EC should be running its
RO image. There is a slight change in that no communication
is done with the EC if not in recovery mode.
BUG=chrome-os-partner:24133
BRANCH=rambi,squawks
TEST=Built and boot with recovery request. Noted EC reboot.
Change-Id: I22240f6a11231e39c33fd79796a52ec76b119397
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182060
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/ec/google/chromeec/ec.c | 16 +++++++++++-----
src/ec/google/chromeec/ec.h | 3 +++
2 files changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c
index c57e18b..6e7ecdf 100644
--- a/src/ec/google/chromeec/ec.c
+++ b/src/ec/google/chromeec/ec.c
@@ -100,8 +100,7 @@ u32 google_chromeec_get_events_b(void)
}
#ifndef __SMM__
-/* Check for recovery mode and ensure EC is in RO */
-void google_chromeec_early_init(void)
+void google_chromeec_check_ec_image(int expected_type)
{
struct chromeec_command cec_cmd;
struct ec_response_get_version cec_resp = {{0}};
@@ -113,9 +112,7 @@ void google_chromeec_early_init(void)
cec_cmd.cmd_size_out = sizeof(cec_resp);
google_chromeec_command(&cec_cmd);
- if (cec_cmd.cmd_code ||
- (recovery_mode_enabled() &&
- (cec_resp.current_image != EC_IMAGE_RO))) {
+ if (cec_cmd.cmd_code || cec_resp.current_image != expected_type) {
struct ec_params_reboot_ec reboot_ec;
/* Reboot the EC and make it come back in RO mode */
reboot_ec.cmd = EC_REBOOT_COLD;
@@ -133,6 +130,15 @@ void google_chromeec_early_init(void)
}
}
+/* Check for recovery mode and ensure EC is in RO */
+void google_chromeec_early_init(void)
+{
+ /* If in recovery ensure EC is running RO firmware. */
+ if (recovery_mode_enabled()) {
+ google_chromeec_check_ec_image(EC_IMAGE_RO);
+ }
+}
+
u16 google_chromeec_get_board_version(void)
{
struct chromeec_command cmd;
diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h
index a037d01..d033bab 100644
--- a/src/ec/google/chromeec/ec.h
+++ b/src/ec/google/chromeec/ec.h
@@ -36,7 +36,10 @@ int google_ec_running_ro(void);
void google_chromeec_init(void);
#endif
+/* If recovery mode is enabled and EC is not running RO firmware reboot. */
void google_chromeec_early_init(void);
+/* Reboot if EC firmware is not expected type. */
+void google_chromeec_check_ec_image(int expected_type);
uint8_t google_chromeec_calc_checksum(const uint8_t *data, int size);
u16 google_chromeec_get_board_version(void);
u32 google_chromeec_get_events_b(void);
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5725
-gerrit
commit 835b89826fb11923a8705266894cca7ec915cc60
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Tue May 13 23:52:30 2014 +1000
superio/winbond/w83627uhg: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.
Convert dependent board to generic winbond serial init. Note the clock
function is actually invalid since it never enters into PNP config mode
to twiddle the register. Further, 48MHz is the default (page 9 of
data-sheet) and so romstage.c need not do anything to the clock rate
hence why it presumably works with this invalid function.
Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/asrock/imb-a180/romstage.c | 8 ++--
src/superio/winbond/w83627uhg/Makefile.inc | 1 -
src/superio/winbond/w83627uhg/early_serial.c | 57 ----------------------------
src/superio/winbond/w83627uhg/w83627uhg.h | 2 +-
4 files changed, 5 insertions(+), 63 deletions(-)
diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c
index 5b64cf9..8ce496b 100644
--- a/src/mainboard/asrock/imb-a180/romstage.c
+++ b/src/mainboard/asrock/imb-a180/romstage.c
@@ -35,7 +35,8 @@
#include "southbridge/amd/agesa/hudson/hudson.h"
#include "cpu/amd/agesa/s3_resume.h"
#include "cbmem.h"
-#include "superio/winbond/w83627uhg/early_serial.c"
+#include <superio/winbond/common/winbond.h>
+#include <superio/winbond/w83627uhg/w83627uhg.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627UHG_SP1)
@@ -80,9 +81,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
post_code(0x30);
post_code(0x31);
- /* Set w83627uhg to 48MHz and enable w83627uhg */
- w83627uhg_set_input_clk_sel(SERIAL_DEV, 0);
- w83627uhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */
+ winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
}
diff --git a/src/superio/winbond/w83627uhg/Makefile.inc b/src/superio/winbond/w83627uhg/Makefile.inc
index f3d04b9..7bb23c0 100644
--- a/src/superio/winbond/w83627uhg/Makefile.inc
+++ b/src/superio/winbond/w83627uhg/Makefile.inc
@@ -19,4 +19,3 @@
##
ramstage-$(CONFIG_SUPERIO_WINBOND_W83627UHG) += superio.c
-
diff --git a/src/superio/winbond/w83627uhg/early_serial.c b/src/superio/winbond/w83627uhg/early_serial.c
deleted file mode 100644
index bfd08a3..0000000
--- a/src/superio/winbond/w83627uhg/early_serial.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2009 Dynon Avionics
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <arch/io.h>
-#include "w83627uhg.h"
-
-static void pnp_enter_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0x87, port);
- outb(0x87, port);
-}
-
-static void pnp_exit_ext_func_mode(device_t dev)
-{
- u16 port = dev >> 8;
- outb(0xaa, port);
-}
-
-/** Set the input clock to 24 or 48 MHz. */
-static void w83627uhg_set_input_clk_sel(device_t dev, u8 speed_24mhz)
-{
- u8 value;
-
- value = pnp_read_config(dev, 0x24);
- value &= ~(1 << 6);
- if (!speed_24mhz)
- value |= (1 << 6);
- pnp_write_config(dev, 0x24, value);
-}
-
-static void w83627uhg_enable_serial(device_t dev, u16 iobase)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
- pnp_set_iobase(dev, PNP_IDX_IO0, iobase);
- pnp_set_enable(dev, 1);
- pnp_exit_ext_func_mode(dev);
-}
diff --git a/src/superio/winbond/w83627uhg/w83627uhg.h b/src/superio/winbond/w83627uhg/w83627uhg.h
index f5442bc..1925a57 100644
--- a/src/superio/winbond/w83627uhg/w83627uhg.h
+++ b/src/superio/winbond/w83627uhg/w83627uhg.h
@@ -37,4 +37,4 @@
#define W83627UHG_SP5 14 /* Com5 */
#define W83627UHG_SP6 15 /* Com6 */
-#endif
+#endif /* SUPERIO_WINBOND_W83627UHG_W83627UHG_H */