coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

Patch merged into coreboot/master: 8be6759 chrome ec: Fix temperature calcualtion in PATx methods
by gerrit＠coreboot.org 13 May '14

13 May '14

the following patch was just integrated into master: commit 8be6759f79b033f4f87c49d340ee935e38b55f20 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jan 9 10:01:05 2014 -0800 chrome ec: Fix temperature calcualtion in PATx methods The PATx methods will be passed a temperature in deci-kelvin, so it needs to be converted back to kelvin before being sent to the EC. The PAT disable method is changed to take the temperature ID as an argument so individual sensors can be disabled. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi, load esif_lf kernel drivers and esif_uf userspace application. Start and stop DPTF and see that temperature thresholds are set to sane values. Change-Id: Ieeff5a5d2d833042923c059caf3e5abaf392da95 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182023 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5036 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5036 for details. -gerrit

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Patch merged into coreboot/master: b3ce658 chrome ec: call DPTF thermal threshold event handler
by gerrit＠coreboot.org 13 May '14

13 May '14

the following patch was just integrated into master: commit b3ce6586085f11412ab58852153c18678c330a3e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue May 13 09:23:10 2014 -0500 chrome ec: call DPTF thermal threshold event handler When an EC thermal event occurs call the DPTF thermal threshold event handler to handle notifications. Change-Id: Ica928790bb478fccf8a46afef4eb7800589518b2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5726 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5726 for details. -gerrit

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Patch merged into coreboot/master: a36d60a baytrail: Updates for DPTF ACPI framework
by gerrit＠coreboot.org 13 May '14

13 May '14

the following patch was just integrated into master: commit a36d60af1ab93945bd216ec3b698f9358840cd96 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 6 12:33:59 2014 -0800 baytrail: Updates for DPTF ACPI framework - Remove some unused functions from CPU participant that were confusing the userland component since the CPU does not have an ACPI managed sensor. - Guard the charger participant with an ifdef so it can be left out if not supported. - Use the EC methods for setting auxiliary trip points and for handling the event when those trip points are crossed. - Add _NTT _DTI _SCP methods for thermal sensors. I'm not clear if these are required or not but they seem to be expected by the other DPTF framework components. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and load ESIF framework Change-Id: I3c9d92d5c52e5a7ec890a377e65ebf118cdd7087 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181662 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5028 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5028 for details. -gerrit

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Patch merged into coreboot/master: 93e2444 chrome ec: Update header and add functions to support DPTF
by gerrit＠coreboot.org 13 May '14

13 May '14

the following patch was just integrated into master: commit 93e244433a510cd57012973192cffb3fa50d66e3 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 6 12:30:52 2014 -0800 chrome ec: Update header and add functions to support DPTF The EC now supports two auxiliary programmable trip points for thermal monitoring. These are expected to be used by DPTF and need to be exported. In order to support these the header was updated from the latest chrome ec source. BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi Change-Id: I257d910daac4e36280c0cecf4129381a32ffcb9a Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181661 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5027 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5027 for details. -gerrit

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Patch merged into coreboot/master: 063b2c4 rambi: Update the DPTF configuration
by gerrit＠coreboot.org 13 May '14

13 May '14

the following patch was just integrated into master: commit 063b2c4df71e54c674d729eae021da3e340bc110 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 6 12:35:36 2014 -0800 rambi: Update the DPTF configuration - Add passive thresholds for thermal participants - Disable the charger participant and remove from _TRT BUG=chrome-os-partner:17279 BRANCH=rambi TEST=build and boot on rambi and start ESIF framework Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181663 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5029 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5029 for details. -gerrit

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New patch to review for coreboot: 377ed49 payloads/coreinfo/multiboot_module.c: Trivial fix indents
by Edward O'Callaghan 13 May '14

13 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5731 -gerrit commit 377ed4969787c9d94aa05deaf6dd3e6af6ebb091 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 04:13:16 2014 +1000 payloads/coreinfo/multiboot_module.c: Trivial fix indents Stylistic fix-up's. Change-Id: I0cad7c860280d0d8dcb16d052846c72f690e2b65 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- payloads/coreinfo/multiboot_module.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/payloads/coreinfo/multiboot_module.c b/payloads/coreinfo/multiboot_module.c index 4cb426b..fdf5434 100644 --- a/payloads/coreinfo/multiboot_module.c +++ b/payloads/coreinfo/multiboot_module.c @@ -68,14 +68,14 @@ int multiboot_module_redraw(WINDOW *win) static void parse_memory(struct multiboot_header *table) { - u8 *start = (u8 *) phys_to_virt(table->mmap_addr); - u8 *ptr = start; + u8 *start = (u8 *) phys_to_virt(table->mmap_addr); + u8 *ptr = start; int i = 0; cb_info.mem_count = 0; - while(ptr < (start + table->mmap_length)) { - struct multiboot_mmap *mmap = (struct multiboot_mmap *) ptr; + while(ptr < (start + table->mmap_length)) { + struct multiboot_mmap *mmap = (struct multiboot_mmap *) ptr; cb_info.range[i].start = mmap->addr; cb_info.range[i].size = mmap->length; @@ -84,9 +84,9 @@ static void parse_memory(struct multiboot_header *table) if (++cb_info.mem_count == MAX_MEMORY_COUNT) return; - ptr += (mmap->size + sizeof(mmap->size)); + ptr += (mmap->size + sizeof(mmap->size)); i++; - } + } } static void parse_header(unsigned long addr) @@ -118,4 +118,4 @@ struct coreinfo_module multiboot_module = { struct coreinfo_module multiboot_module = { }; -#endif +#endif /* CONFIG_MODULE_MULTIBOOT */

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New patch to review for coreboot: 9bf1b2b mainboard/asus/k8v-x: Abstract PNP programming to obj level
by Edward O'Callaghan 13 May '14

13 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5730 -gerrit commit 9bf1b2b97a42dd19afc21ec568b245a3c0822d54 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed May 14 03:41:00 2014 +1000 mainboard/asus/k8v-x: Abstract PNP programming to obj level This board #include's fragments of superio support leading to a blur of abstraction even at the source level. Convert serial init to recent general winbond romstage framework. Ensure superio code and romstage code are separated down to the object level. Change-Id: Ibedc147761caacfae9136d77af7179f22f1f147e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/asus/k8v-x/romstage.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 4fe1016..0ab882f 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -6,6 +6,7 @@ * Copyright (C) 2006 MSI * (Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI) * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -38,7 +39,8 @@ unsigned int get_sbdn(unsigned bus); #include "cpu/x86/lapic.h" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/early_ht.c" -#include "superio/winbond/w83697hf/early_serial.c" +#include <superio/winbond/common/winbond.h> +#include <superio/winbond/w83697hf/w83697hf.h> #include "southbridge/via/vt8237r/early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ #include "cpu/x86/bist.h" @@ -97,8 +99,12 @@ unsigned int get_sbdn(unsigned bus) static void sio_init(void) { u8 reg; + u16 port = SERIAL_DEV >> 8; + + /* enter SIO PNP config state */ + outb(0x87, port); + outb(0x87, port); - pnp_enter_ext_func_mode(SERIAL_DEV); reg = pnp_read_config(SERIAL_DEV, 0x24); /* 4 Mbit flash */ reg = (reg & ~0x30) | 0x20; @@ -107,6 +113,9 @@ static void sio_init(void) /* enable MEMW#, so flash can be written */ reg |= 0x08; pnp_write_config(SERIAL_DEV, 0x24, reg); + + /* exit SIO PNP config state */ + outb(0xAA, port); } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -124,7 +133,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; sio_init(); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_rom_decode(); @@ -137,13 +146,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) enumerate_ht_chain(); } - // FIXME why is this executed again? ---> - sio_init(); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); - enable_rom_decode(); - // <--- FIXME why is this executed again? - print_info("now booting... real_main\n"); if (bist == 0)

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Patch set updated for coreboot: b732402 superio/winbond/w83977f: Avoid .c includes
by Edward O'Callaghan 13 May '14

13 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5447 -gerrit commit b7324021e28049c6fb51adbc25b9cc6972dc484b Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Apr 3 03:29:22 2014 +1100 superio/winbond/w83977f: Avoid .c includes Following the same reasoning as commit d304331 superio/fintek/f81865f: Avoid .c includes Change-Id: I97f14306b2c269b99d60327a6f9869de6a7d7cc3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/superio/winbond/w83977f/Makefile.inc | 2 +- src/superio/winbond/w83977f/early_serial.c | 3 ++- src/superio/winbond/w83977f/w83977f.h | 8 +++++--- 3 files changed, 8 insertions(+), 5 deletions(-) diff --git a/src/superio/winbond/w83977f/Makefile.inc b/src/superio/winbond/w83977f/Makefile.inc index e52c09d..60edac9 100644 --- a/src/superio/winbond/w83977f/Makefile.inc +++ b/src/superio/winbond/w83977f/Makefile.inc @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## +romstage-$(CONFIG_SUPERIO_WINBOND_W83977F) += early_serial.c ramstage-$(CONFIG_SUPERIO_WINBOND_W83977F) += superio.c - diff --git a/src/superio/winbond/w83977f/early_serial.c b/src/superio/winbond/w83977f/early_serial.c index c572dcb..11723a6 100644 --- a/src/superio/winbond/w83977f/early_serial.c +++ b/src/superio/winbond/w83977f/early_serial.c @@ -34,7 +34,8 @@ static void pnp_exit_ext_func_mode(device_t dev) outb(0xaa, port); } -static void w83977f_enable_serial(device_t dev, u16 iobase) +/* Depreciated use winbond_enable_serial() instead. */ +void w83977f_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); diff --git a/src/superio/winbond/w83977f/w83977f.h b/src/superio/winbond/w83977f/w83977f.h index f2b68ed..8d38463 100644 --- a/src/superio/winbond/w83977f/w83977f.h +++ b/src/superio/winbond/w83977f/w83977f.h @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef SUPERIO_WINBOND_W83977F_W83977F_H -#define SUPERIO_WINBOND_W83977F_W83977F_H +#ifndef SUPERIO_WINBOND_W83977F_H +#define SUPERIO_WINBOND_W83977F_H #define W83977F_FDC 0 /* Floppy */ #define W83977F_PP 1 /* Parallel port */ @@ -31,4 +31,6 @@ #define W83977F_GPIO1 7 /* General Purpose I/O 1 */ #define W83977F_GPIO2 8 /* General Purpose I/O 2 */ -#endif +void w83977f_enable_serial(device_t dev, u16 iobase); + +#endif /* SUPERIO_WINBOND_W83977F_H */

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Patch set updated for coreboot: 314f544 superio/ite/it8728f/it8728f_hwm.c: Small fixes
by Paul Menzel 13 May '14

13 May '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5729 -gerrit commit 314f5445e00fc866695f63cddb9edf993b01b47f Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue May 13 16:46:21 2014 +0200 superio/ite/it8728f/it8728f_hwm.c: Small fixes Use proper include header in it8728f_hwm.c, fix format error. The base of HWM block starts at offset +5. Change-Id: I6855225b38bbcf5687d506bea9482c951d314684 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/superio/ite/it8728f/it8728f_hwm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c index 389cfd5..fd486a8 100644 --- a/src/superio/ite/it8728f/it8728f_hwm.c +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -23,13 +23,13 @@ #include <device/device.h> #include <device/pnp.h> #include "chip.h" -#include "ite_internal.h" +#include "it8728f_internal.h" /* * FAN controller configuration register index's */ #define HWM_MAIN_CTL_REG 0x13 /* default 0x07 */ -#define HWM_CTL_REG 0x14 /* default 0x40 */ +#define HWM_CTL_REG 0x14 /* default 0x40 */ #define HWM_FAN1_CTL_PWM 0x15 /* default 0x00 */ #define HWM_FAN2_CTL_PWM 0x16 /* default 0x00 */ #define HWM_FAN3_CTL_PWM 0x17 /* default 0x00 */ @@ -50,7 +50,8 @@ void it8728f_hwm_ec_init(device_t dev) printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); return; } - u16 port = res->base; + /* I/O port for HWM is at base + 5 */ + u16 port = res->base + 5; printk(BIOS_INFO, "ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n");

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New patch to review for coreboot: 161bc32 it8728f_hwm.c: Small fixes
by Rudolf Marek 13 May '14

13 May '14

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5729 -gerrit commit 161bc326abb8fc079edff910157f5f82c1aa2d6e Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Tue May 13 16:46:21 2014 +0200 it8728f_hwm.c: Small fixes Use proper include header in it8728f_hwm.c, fix format error. The base of HWM block starts at offset +5. Change-Id: I6855225b38bbcf5687d506bea9482c951d314684 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/superio/ite/it8728f/it8728f_hwm.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/superio/ite/it8728f/it8728f_hwm.c b/src/superio/ite/it8728f/it8728f_hwm.c index 389cfd5..fd486a8 100644 --- a/src/superio/ite/it8728f/it8728f_hwm.c +++ b/src/superio/ite/it8728f/it8728f_hwm.c @@ -23,13 +23,13 @@ #include <device/device.h> #include <device/pnp.h> #include "chip.h" -#include "ite_internal.h" +#include "it8728f_internal.h" /* * FAN controller configuration register index's */ #define HWM_MAIN_CTL_REG 0x13 /* default 0x07 */ -#define HWM_CTL_REG 0x14 /* default 0x40 */ +#define HWM_CTL_REG 0x14 /* default 0x40 */ #define HWM_FAN1_CTL_PWM 0x15 /* default 0x00 */ #define HWM_FAN2_CTL_PWM 0x16 /* default 0x00 */ #define HWM_FAN3_CTL_PWM 0x17 /* default 0x00 */ @@ -50,7 +50,8 @@ void it8728f_hwm_ec_init(device_t dev) printk(BIOS_WARNING, "Super I/O HWM: No HWM resource found.\n"); return; } - u16 port = res->base; + /* I/O port for HWM is at base + 5 */ + u16 port = res->base + 5; printk(BIOS_INFO, "ITE IT8728F Super I/O HWM: Initializing Hardware Monitor..\n");

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coreboot-gerrit May 2014