coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

New patch to review for coreboot: 0f13737 xcompile: fail earlier on missing host tools
by Patrick Georgi 14 May '14

14 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5742 -gerrit commit 0f1373762a90fe96d99dbf86ccf161362800535b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 14 14:26:07 2014 +0200 xcompile: fail earlier on missing host tools No need to test all the cross compiler things if there's no host compiler or iasl. Also test that the alternatives work, instead of assuming iasl or cc are in the path. Change-Id: I1d2293873f4bf1bb525d794851ec20adddb05ac6 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/xcompile/xcompile | 47 +++++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 20 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 2ac82b6..81d5b3c 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -20,6 +20,7 @@ # TMPFILE="" +XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} die() { echo "ERROR: $*" >&2 @@ -36,6 +37,32 @@ program_exists() { type "$1" >/dev/null 2>&1 } + +if [ "$(${XGCCPATH}/iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then + IASL=${XGCCPATH}iasl +elif [ "$(iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then + IASL=iasl +else + echo "no iasl found" + exit 1 +fi + +if program_exists gcc; then + HOSTCC=gcc +elif program_exists cc; then + HOSTCC=cc +else + echo "no host compiler found" + exit 1 +fi + +cat <<EOF +# platform agnostic and host tools +IASL:=${IASL} +HOSTCC:=${HOSTCC} + +EOF + testcc() { local tmp_c="$TMPFILE.c" local tmp_o="$TMPFILE.o" @@ -163,8 +190,6 @@ arch_config_x86() { TWIDTH="32" } -XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} - # This loops over all supported architectures. for architecture in $SUPPORTED_ARCHITECTURE; do GCCPREFIX="invalid" @@ -207,21 +232,3 @@ for architecture in $SUPPORTED_ARCHITECTURE; do report_arch_toolchain done -if [ "$(${XGCCPATH}/iasl 2>/dev/null | grep -c ACPI)" -gt 0 ]; then - IASL=${XGCCPATH}iasl -else - IASL=iasl -fi - -if program_exists gcc; then - HOSTCC=gcc -else - HOSTCC=cc -fi - -cat <<EOF -IASL:=${IASL} - -# native toolchain -HOSTCC:=${HOSTCC} -EOF

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New patch to review for coreboot: 42c5578 xcompile: slightly refactor variable expansion magic
by Patrick Georgi 14 May '14

14 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5741 -gerrit commit 42c55782660bb366e750a3e662d18bb2285ed400 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 14 14:23:28 2014 +0200 xcompile: slightly refactor variable expansion magic Change-Id: Iebe071c863c6c7139128a2ec59acfb9da0f83512 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/xcompile/xcompile | 50 +++++++++++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 23 deletions(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index 160b73b..2ac82b6 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -142,34 +142,38 @@ trap clean_up EXIT # Architecture definition SUPPORTED_ARCHITECTURE="x86 armv7 aarch64" -# ARM Architecture -TARCH_armv7="armv7" -TBFDARCH_armv7="littlearm" -TCLIST_armv7="armv7a armv7-a" -TWIDTH_armv7="32" - -# AARCH64 -- armv8 -TARCH_aarch64="aarch64" -TBFDARCH_aarch64="littleaarch64" -TCLIST_aarch64="aarch64" -TWIDTH_aarch64="64" - -# X86 Architecture -TARCH_x86="i386" -TBFDARCH_x86="i386" -TCLIST_x86="i386 x86_64" -TWIDTH_x86="32" +arch_config_armv7() { + TARCH="armv7" + TBFDARCH="littlearm" + TCLIST="armv7a armv7-a" + TWIDTH="32" +} + +arch_config_aarch64() { + TARCH="aarch64" + TBFDARCH="littleaarch64" + TCLIST="aarch64" + TWIDTH="64" +} + +arch_config_x86() { + TARCH="i386" + TBFDARCH="i386" + TCLIST="i386 x86_64" + TWIDTH="32" +} + XGCCPATH=${1:-"`pwd`/util/crossgcc/xgcc/bin/"} # This loops over all supported architectures. for architecture in $SUPPORTED_ARCHITECTURE; do GCCPREFIX="invalid" - TARCH="$(eval echo \$TARCH_$architecture)" - TBFDARCH="$(eval echo \$TBFDARCH_$architecture)" - TCLIST="$(eval echo \$TCLIST_$architecture)" - TWIDTH="$(eval echo \$TWIDTH_$architecture)" - [ -z "$TARCH" -o -z "$TCLIST" -o -z "$TWIDTH" ] && - die "Missing architecture definition for $architecture." + if type arch_config_$architecture > /dev/null; then + arch_config_$architecture + else + echo "no architecture definition for $architecture" + exit 1 + fi # To override toolchain, define CROSS_COMPILE_$arch or CROSS_COMPILE as # environment variable.

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New patch to review for coreboot: fa3c557 xcompile: use bash
by Patrick Georgi 14 May '14

14 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5740 -gerrit commit fa3c557fc45b811d2d1322e9565cacc8e571dfea Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 14 14:14:38 2014 +0200 xcompile: use bash I don't think all /bin/sh implement all features used in xcompile. Change-Id: Ida2a166242201ed0221316b123888127c83bf3c1 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/xcompile/xcompile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/xcompile/xcompile b/util/xcompile/xcompile index df7d558..160b73b 100644 --- a/util/xcompile/xcompile +++ b/util/xcompile/xcompile @@ -1,4 +1,4 @@ -#!/bin/sh +#!/bin/bash # # This file is part of the coreboot project. #

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New patch to review for coreboot: c986847 abuild: add -L|--clang to enable clang builds
by Patrick Georgi 14 May '14

14 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5739 -gerrit commit c986847e83146c9586f6f90b01f0d74ca02db3fb Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Wed May 14 13:43:58 2014 +0200 abuild: add -L|--clang to enable clang builds Change-Id: I11053456fd90cda07143b76de49c2804e38f06e0 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- util/abuild/abuild | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index 713bbf6..c08f4a2 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -393,6 +393,7 @@ function myhelp printf " [-u|--update] update existing image\n" printf " [-P|--prefix <name>] file name prefix in CBFS\n" printf " [-B|--blobs] Allow using binary files\n" + printf " [-L|--clang] Use clang\n" printf " [cbroot] absolute path to coreboot sources\n" printf " (defaults to $ROOT)\n\n" } @@ -433,7 +434,7 @@ cmdline="$* -c 1" getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,verbose,help,all,target:,payloads:,test,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs -o Vvhat:p:Tc:sJCl:rP:uyB -- "$@"` || exit 1 + args=`getopt -l version,verbose,help,all,target:,payloads:,test,cpus:,silent,junit,config,loglevel:,remove,prefix:,update,scan-build,ccache,blobs,clang -o Vvhat:p:Tc:sJCl:rP:uyBL -- "$@"` || exit 1 eval set -- $args else # Detected non-GNU getopt @@ -494,6 +495,10 @@ while true ; do customizing="${customizing}, blobs" configoptions="${configoptions}CONFIG_USE_BLOBS=y\n" ;; + -L|--clang) shift + customizing="${customizing}, clang" + configoptions="${configoptions}CONFIG_COMPILER_LLVM_CLANG=y\n" + ;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;;

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Patch set updated for coreboot: 8998795 rambi: disable SERIRQ native functionality
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5042 -gerrit commit 89987950484b9b15c3d848f9278f640b47bb4d64 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Jan 10 11:48:45 2014 -0600 rambi: disable SERIRQ native functionality Nothing can actually use this as the EC cannot speak using baytrail's SERIRQ protocol. Also, the voltage bridge is going away so nothing will be hooked up to it. Therefore disable this it. BUG=chrome-os-partner:24693 BRANCH=rambi TEST=Built and booted. Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182082 Reviewed-by: Shawn Nematbakhsh <shawnn(a)chromium.org> --- src/mainboard/google/rambi/gpio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/rambi/gpio.c b/src/mainboard/google/rambi/gpio.c index f1d9ef4..281709a 100644 --- a/src/mainboard/google/rambi/gpio.c +++ b/src/mainboard/google/rambi/gpio.c @@ -106,7 +106,7 @@ static const struct soc_gpio_map gpscore_gpio_map[] = { GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */ - GPIO_FUNC(1, PULL_UP, 10K), /* S0-SC050 - IRQ_SERIRQ */ + GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */

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Patch set updated for coreboot: cb0155c baytrail: mrc_cache: check region erased before erasing
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5043 -gerrit commit cb0155cd285b009d06e7e6227ee1f81257433b4c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 13 11:34:51 2014 -0600 baytrail: mrc_cache: check region erased before erasing On a firmware update the MRC cache is destroyed. On the subsequent boot the MRC region was attempted to be erased even if it was already erased. This led to spi part taking longer than it should have for an unnecessary erase operation. Therefore, check that the region is erased before issuing the erease command. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmeareupdate. Noted no error messages in this path. Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182153 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/mrc_cache.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/baytrail/mrc_cache.c b/src/soc/intel/baytrail/mrc_cache.c index 5613761..ae0afe7 100644 --- a/src/soc/intel/baytrail/mrc_cache.c +++ b/src/soc/intel/baytrail/mrc_cache.c @@ -275,9 +275,12 @@ static void update_mrc_cache(void *unused) next_slot = mrc_cache_next_slot(&region, current_saved); if (!mrc_slot_valid(&region, next_slot, current_boot)) { - if (nvm_erase(region.base, region.size) < 0) { - printk(BIOS_DEBUG, "Could not erase MRC region.\n"); - return; + printk(BIOS_DEBUG, "Slot @ %p is invalid.\n", next_slot); + if (!nvm_is_erased(region.base, region.size)) { + if (nvm_erase(region.base, region.size) < 0) { + printk(BIOS_DEBUG, "Failure erasing region.\n"); + return; + } } next_slot = region.base; }

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Patch set updated for coreboot: 1f4781d baytrail: Add ACPI Device for XHCI
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5046 -gerrit commit 1f4781d8e2d67069a2a95a44d30db2f744685ce4 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 14 14:59:28 2014 -0800 baytrail: Add ACPI Device for XHCI This will allow USB devices to wake the system (if 5V is not turned off) and the controller to enter D3 at runtime. (if autosuspend is enabled) BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on baytrail 1) with modified EC to leave 5V on in S3 ensure that waking from suspend with USB keyboard works. 2) with laptop-mode-tools usb autosuepend config updated see that device enters D3 at runtime when no external devices attached. Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182536 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/acpi/southcluster.asl | 3 +++ src/soc/intel/baytrail/acpi/xhci.asl | 36 ++++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) diff --git a/src/soc/intel/baytrail/acpi/southcluster.asl b/src/soc/intel/baytrail/acpi/southcluster.asl index ced1618..61642a5 100644 --- a/src/soc/intel/baytrail/acpi/southcluster.asl +++ b/src/soc/intel/baytrail/acpi/southcluster.asl @@ -252,6 +252,9 @@ Device (IOSF) // LPC Bridge 0:1f.0 #include "lpc.asl" +// USB XHCI 0:14.0 +#include "xhci.asl" + // IRQ routing for each PCI device #include "irqroute.asl" diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl new file mode 100644 index 0000000..4d5367a --- /dev/null +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +Device (XHCI) +{ + Name (_ADR, 0x00140000) + Name (_PRW, Package () { 0x0d, 3 }) + Name (_S3D, 3) /* Highest D state in S3 state */ + + Device (RHUB) + { + Name (_ADR, 0x00000000) + Device (PRT1) { Name (_ADR, 1) } + Device (PRT2) { Name (_ADR, 2) } + Device (PRT3) { Name (_ADR, 3) } + Device (PRT4) { Name (_ADR, 4) } + } +}

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Patch set updated for coreboot: 7ab7676 baytrail: nvm: use proper types for checking erase
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5044 -gerrit commit 7ab767673e4073ef9f80c209ff4ad5f2ce51b222 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 13 11:39:04 2014 -0600 baytrail: nvm: use proper types for checking erase The current byte value was being converted to an int when checking against literal 0xff. As the type of the current pointer was char (signed) it was sign extending the value leading to 0xffffffff != 0xff. Fix this by using an unsigned type and using a constant type for expected erase value. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmwareupdate. Noted that MRC cache doesn't think the erased region isn't erased. Change-Id: If95425fe26da050acb25f52bea060e288ad3633c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182154 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/nvm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/nvm.c b/src/soc/intel/baytrail/nvm.c index dccc801..843bc5a 100644 --- a/src/soc/intel/baytrail/nvm.c +++ b/src/soc/intel/baytrail/nvm.c @@ -54,10 +54,11 @@ static inline uint32_t to_flash_offset(void *p) int nvm_is_erased(const void *start, size_t size) { - const char *cur = start; + const uint8_t *cur = start; + const uint8_t erased_value = 0xff; while (size > 0) { - if (*cur != 0xff) + if (*cur != erased_value) return 0; cur++; size--;

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Patch set updated for coreboot: 177a446 rambi: Add ACPI table support for I2C devices
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5045 -gerrit commit 177a4464e98a3e3db52eac457b4265dca3756c0a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 13 10:15:12 2014 -0800 rambi: Add ACPI table support for I2C devices In order to support probing I2C devices when the controller is in ACPI mode the mainboard needs to decalre them in the proper scope with the address/interrupt information. The touchpad devices are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can be distinguished in userland scripts based on ID. There is also a special "ISTP" node that indicates whether the devices is a touchpad (=1) or touchscreen (=0) in case this is useful to drivers. These names may not be final but they are a starting point and can be easily changed. Atmel devices also have a bootloader mode which needs to be declared as a separate device. Unfortunately it does not work as expected to have multiple I2cSerialBus() resources declared in a single device and have it select properly, even with the use of StartDependentFn(), so bootloader devices are declared separately. The original devices are left in \_SB scope and are only enabled if the I2C controllers are in PCI mode. The new devices are only enabled if the I2C controllers are in ACPI mode. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual 1) Ensure there is no change in functionality by default and that the devices are still probed by chromeos_laptop in the kernel. 2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to add _HID entries for devices in appropriate drivers. Ensure that the devices are probed successfully. Further changes are needed to the chromeos-touch-firmware scripts to load config and update firmware based on the new ACPI _HID entries. 3) Put touchpad in bootloader mode (by flashing bad firmware) and ensure that it is detected at address 0x25 and the firmware is able to be updated. Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182259 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/rambi/acpi/mainboard.asl | 226 +++++++++++++++++++++++--- src/mainboard/google/rambi/dsdt.asl | 5 +- 2 files changed, 202 insertions(+), 29 deletions(-) diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 696d1aa..9b16272 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -40,71 +40,243 @@ Scope (\_SB) Device (TPAD) { - Name (_ADR, 0x0) + Name (_HID, EisaId ("PNP0C0E")) Name (_UID, 1) - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) - Name (_CRS, ResourceTemplate() { Interrupt (ResourceConsumer, Edge, ActiveLow) { BOARD_TRACKPAD_IRQ } + }) + + Method (_STA) + { + /* Disable if I2C1 is in ACPI mode */ + If (LEqual (\S1EN, 1)) { + Return (0x0) + } Else { + Return (0xF) + } + } - VendorShort (ADDR) + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + } + + Device (TSCR) + { + Name (_HID, EisaId ("PNP0C0E")) + Name (_UID, 2) + + Name (_CRS, ResourceTemplate() + { + Interrupt (ResourceConsumer, Edge, ActiveLow) { - BOARD_TRACKPAD_I2C_ADDR + BOARD_TOUCHSCREEN_IRQ } }) - Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + Method (_STA) + { + /* Disable if I2C6 is in ACPI mode */ + If (LEqual (\S6EN, 1)) { + Return (0x0) + } Else { + Return (0xF) + } + } + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + } +} + +Scope (\_SB.I2C1) +{ + Device (ATPB) + { + Name (_HID, "ATML0000") + Name (_DDN, "Atmel Touchpad Bootloader") + Name (_UID, 1) + Name (ISTP, 1) /* Touchpad */ - Method (_DSW, 3, NotSerialized) + Name (_CRS, ResourceTemplate() { - Store (BOARD_TRACKPAD_WAKE_GPIO, Local0) + I2cSerialBus ( + 0x25, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - // \_SB.PCI0.LPCB.GWAK (Local0) + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) } - Device (TSCR) + Device (ATPA) { - Name (_ADR, 0x0) + Name (_HID, "ATML0000") + Name (_CID, EisaId ("PNP0C0E")) + Name (_DDN, "Atmel Touchpad") Name (_UID, 2) + Name (ISTP, 1) /* Touchpad */ + + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x4b, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.I2C1", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TRACKPAD_IRQ + } + }) - // Report as a Sleep Button device so Linux will - // automatically enable it as a wake source - Name (_HID, EisaId("PNP0C0E")) + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + } + + Device (ETPA) + { + Name (_HID, "ELAN0000") + Name (_CID, EisaId ("PNP0C0E")) + Name (_DDN, "Elan Touchpad") + Name (_UID, 3) + Name (ISTP, 1) /* Touchpad */ Name (_CRS, ResourceTemplate() { + I2cSerialBus ( + 0x15, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.I2C1", // ResourceSource + ) Interrupt (ResourceConsumer, Edge, ActiveLow) { - BOARD_TOUCHSCREEN_IRQ + BOARD_TRACKPAD_IRQ } + }) + + Method (_STA) + { + If (LEqual (\S1EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + + Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 }) + } +} + +Scope (\_SB.I2C6) +{ + Device (ATSB) + { + Name (_HID, "ATML0001") + Name (_DDN, "Atmel Touchscreen Bootloader") + Name (_UID, 4) + Name (ISTP, 0) /* TouchScreen */ - VendorShort (ADDR) + Name (_CRS, ResourceTemplate() + { + I2cSerialBus ( + 0x26, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) { - BOARD_TOUCHSCREEN_I2C_ADDR + BOARD_TOUCHSCREEN_IRQ } }) - Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) + } + } - Method (_DSW, 3, NotSerialized) + /* Allow device to power off in S0 */ + Name (_S0W, 4) + } + + Device (ATSA) + { + Name (_HID, "ATML0001") + Name (_CID, EisaId ("PNP0C0E")) + Name (_DDN, "Atmel Touchscreen") + Name (_UID, 5) + Name (ISTP, 0) /* TouchScreen */ + + Name (_CRS, ResourceTemplate() { - Store (BOARD_TOUCHSCREEN_WAKE_GPIO, Local0) + I2cSerialBus ( + 0x4a, // SlaveAddress + ControllerInitiated, // SlaveMode + 400000, // ConnectionSpeed + AddressingMode7Bit, // AddressingMode + "\_SB.I2C6", // ResourceSource + ) + Interrupt (ResourceConsumer, Edge, ActiveLow) + { + BOARD_TOUCHSCREEN_IRQ + } + }) - If (LEqual (Arg0, 1)) { - // Enable GPIO as wake source - // \_SB.PCI0.LPCB.GWAK (Local0) + Method (_STA) + { + If (LEqual (\S6EN, 1)) { + Return (0xF) + } Else { + Return (0x0) } } + + /* Allow device to power off in S0 */ + Name (_S0W, 4) + + Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 }) } } diff --git a/src/mainboard/google/rambi/dsdt.asl b/src/mainboard/google/rambi/dsdt.asl index 53f2922..4165087 100644 --- a/src/mainboard/google/rambi/dsdt.asl +++ b/src/mainboard/google/rambi/dsdt.asl @@ -23,7 +23,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 + 0x05, // DSDT revision: ACPI v5.0 "COREv4", // OEM id "COREBOOT", // OEM table id 0x20110725 // OEM revision @@ -31,7 +31,6 @@ DefinitionBlock( { // Some generic macros #include <soc/intel/baytrail/acpi/platform.asl> - #include "acpi/mainboard.asl" // global NVS and variables #include <soc/intel/baytrail/acpi/globalnvs.asl> @@ -56,4 +55,6 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/baytrail/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" }

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Patch set updated for coreboot: 37ca186 baytrail: enable graphics turbo
by Aaron Durbin 14 May '14

14 May '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5050 -gerrit commit 37ca1861cad66aa399b1c667f282390cbd915e7a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jan 15 11:59:10 2014 -0600 baytrail: enable graphics turbo Though the limited documentation indicates the default is 0 for the gfx_turbo_disable bit, in practice that isn't true. Knock down the gfs_turbo_disable bit to enable graphics turbo mode. BUG=chrome-os-partner:25044 BRANCH=baytrail TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG. Noted that bit 7 was set to 0. Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182640 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/gfx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 6f78dac..4ed08c9 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -212,6 +212,10 @@ static const struct reg_script gfx_init_script[] = { REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0), REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0), + + /* Enable Gfx Turbo. */ + REG_IOSF_RMW(IOSF_PORT_PMC, SB_BIOS_CONFIG, + ~SB_BIOS_CONFIG_GFX_TURBO_DIS, 0), REG_SCRIPT_END };

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coreboot-gerrit May 2014