coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: d44aedf vendorcode/amd/agesa, cimx: Integer comparisons always true
by Edward O'Callaghan 15 May '14

15 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5749 -gerrit commit d44aedfeeda4e5d59e504c1dd492cd02be813ecf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 05:23:09 2014 +1000 vendorcode/amd/agesa,cimx: Integer comparisons always true Change-Id: I6a3f36cd7e4f2cf26a72f3e849fed0b2da691d1d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Lib/amdlib.c | 9 +++++---- src/vendorcode/amd/cimx/sb800/SATA.c | 12 ++++++------ 2 files changed, 11 insertions(+), 10 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c index 31b3f1e..2bee185 100644 --- a/src/vendorcode/amd/agesa/f14/Lib/amdlib.c +++ b/src/vendorcode/amd/agesa/f14/Lib/amdlib.c @@ -348,11 +348,12 @@ LibAmdBitScanReverse ( IN UINT32 value ) { - UINTN Index; - for (Index = 31; Index >= 0; Index--){ - if (value & (1 << Index)) break; + UINT8 Index; + for (Index = 31; Index > 0; Index--){ + if (value & (1 << Index)) + return Index; } - return (UINT8) Index; + return 0xFF; } VOID LibAmdMsrRead ( diff --git a/src/vendorcode/amd/cimx/sb800/SATA.c b/src/vendorcode/amd/cimx/sb800/SATA.c index a301208..c2f2162 100644 --- a/src/vendorcode/amd/cimx/sb800/SATA.c +++ b/src/vendorcode/amd/cimx/sb800/SATA.c @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -25,10 +25,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -39,7 +39,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -568,7 +568,7 @@ sataDriveDetection ( UINT8 dbPortNum; UINT8 dbVar0; UINT16 dwIoBase; - UINT16 dwVar0; + UINT32 dwVar0; if ( (pConfig->SataClass == NATIVE_IDE_MODE) || (pConfig->SataClass == LEGACY_IDE_MODE) || (pConfig->SataClass == IDE_TO_AHCI_MODE) ) { for ( dbPortNum = 0; dbPortNum < 4; dbPortNum++ ) { ReadMEM (*pBar5 + SB_SATA_BAR5_REG128 + dbPortNum * 0x80, AccWidthUint32, &ddVar0);

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Patch merged into coreboot/master: 9fd7c0f baytrail: Add SOC thermal settings
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit 9fd7c0f18ee8665f2e4dc311ae906412f2b0a0a1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jan 16 09:47:39 2014 -0800 baytrail: Add SOC thermal settings Apply the SOC thermal settings from DPTF reference code for SdpProfile=4 and adjust graphics PUNIT setting to match. BUG=chrome-os-partner:17279 BRANCH=baytrail TEST=boot on rambi and check for valid GPU power values from DPTF Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182786 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5052 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5052 for details. -gerrit

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Patch merged into coreboot/master: c6313db baytrail: Enable PCIe common clock and ASPM
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit c6313db34f26bcb8bdbb5ff04ebc9c9e7193cf0f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Jan 16 11:18:36 2014 -0800 baytrail: Enable PCIe common clock and ASPM Enable the config options to have the device enumeration layer configure common clock and ASPM for endpoints. BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on rambi, check PCIe for ASPM and common clock: lspci -vv -s 0:1c.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ lspci -vv -s 1:00.0 | grep LnkCtl: LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes Disabled- Retrain- CommClk+ Change-Id: I2477e3cada0732dc71db0d6692ff5b6159ed269f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182860 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5051 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5051 for details. -gerrit

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Patch merged into coreboot/master: 3549462 baytrail: enable graphics turbo
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit 3549462a95c5d7b9450924a1c0ca54b992c81211 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Jan 15 11:59:10 2014 -0600 baytrail: enable graphics turbo Though the limited documentation indicates the default is 0 for the gfx_turbo_disable bit, in practice that isn't true. Knock down the gfs_turbo_disable bit to enable graphics turbo mode. BUG=chrome-os-partner:25044 BRANCH=baytrail TEST=Built and booted. Added debug code to output SB_BIOS_CONFIG. Noted that bit 7 was set to 0. Change-Id: I11210c6a0b29765cb709a54d6ebd94211538807b Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182640 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5050 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5050 for details. -gerrit

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Patch merged into coreboot/master: 469b520 rambi: Add ACPI devices and interrupts for codec and ALS
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit 469b5205c31eeb7f58e66aaec58ef824f2e090a5 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 13 16:37:51 2014 -0800 rambi: Add ACPI devices and interrupts for codec and ALS The Codec and ALS both have interrupt sources that can be configured. The ALS kernel driver currently does not try to use it but the codec driver does for things like jack detect. ACPI Devices are added, but as with other ACPI devices the HID may need to be updated once more official strings are decided. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual: build and boot on rambi and check for functional lightsensor Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182366 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5049 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5049 for details. -gerrit

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Patch merged into coreboot/master: 59d1d87 baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit 59d1d87c86ff26142de23fd372fece3977a7330c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Jan 14 17:34:10 2014 -0600 baytrail: use CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED On baytrail, it appears that the turbo disable setting is actually building-block scoped. One can see this on quad core parts where if enable_turbo() is called only on the BSP then only cpus 0 and 1 have turbo enabled. Fix this by calling enable_turbo() on all non-bsp cpus. BUG=chrome-os-partner:25014 BRANCH=baytrail TEST=Built and booted rambi. All cpus have bit 38 set to 0 in msr 0x1a0. Change-Id: Id493e070c4a70bb236cdbd540d2321731a99aec2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182406 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5048 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5048 for details. -gerrit

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Patch merged into coreboot/master: 3f94a74 baytrail: Add ACPI Device for XHCI
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit 3f94a74de29c660555d10fc3ddc18626668c618a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Jan 14 14:59:28 2014 -0800 baytrail: Add ACPI Device for XHCI This will allow USB devices to wake the system (if 5V is not turned off) and the controller to enter D3 at runtime. (if autosuspend is enabled) BUG=chrome-os-partner:23629 BRANCH=baytrail TEST=build and boot on baytrail 1) with modified EC to leave 5V on in S3 ensure that waking from suspend with USB keyboard works. 2) with laptop-mode-tools usb autosuepend config updated see that device enters D3 at runtime when no external devices attached. Change-Id: Ia396d42494e30105f06eb3bd65b4ba8b1372cf35 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182536 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5046 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5046 for details. -gerrit

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Patch merged into coreboot/master: 5a45c95 rambi: Add ACPI table support for I2C devices
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit 5a45c9529a24a1be0a288fac2dab45b24e50c272 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Jan 13 10:15:12 2014 -0800 rambi: Add ACPI table support for I2C devices In order to support probing I2C devices when the controller is in ACPI mode the mainboard needs to decalre them in the proper scope with the address/interrupt information. The touchpad devices are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can be distinguished in userland scripts based on ID. There is also a special "ISTP" node that indicates whether the devices is a touchpad (=1) or touchscreen (=0) in case this is useful to drivers. These names may not be final but they are a starting point and can be easily changed. Atmel devices also have a bootloader mode which needs to be declared as a separate device. Unfortunately it does not work as expected to have multiple I2cSerialBus() resources declared in a single device and have it select properly, even with the use of StartDependentFn(), so bootloader devices are declared separately. The original devices are left in \_SB scope and are only enabled if the I2C controllers are in PCI mode. The new devices are only enabled if the I2C controllers are in ACPI mode. BUG=chrome-os-partner:24380 BRANCH=baytrail TEST=manual 1) Ensure there is no change in functionality by default and that the devices are still probed by chromeos_laptop in the kernel. 2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to add _HID entries for devices in appropriate drivers. Ensure that the devices are probed successfully. Further changes are needed to the chromeos-touch-firmware scripts to load config and update firmware based on the new ACPI _HID entries. 3) Put touchpad in bootloader mode (by flashing bad firmware) and ensure that it is detected at address 0x25 and the firmware is able to be updated. Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182259 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/5045 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5045 for details. -gerrit

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Patch merged into coreboot/master: b013fff baytrail: nvm: use proper types for checking erase
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit b013fff5a3c036864c8f545f5cf645e27100209c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 13 11:39:04 2014 -0600 baytrail: nvm: use proper types for checking erase The current byte value was being converted to an int when checking against literal 0xff. As the type of the current pointer was char (signed) it was sign extending the value leading to 0xffffffff != 0xff. Fix this by using an unsigned type and using a constant type for expected erase value. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmwareupdate. Noted that MRC cache doesn't think the erased region isn't erased. Change-Id: If95425fe26da050acb25f52bea060e288ad3633c Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182154 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5044 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5044 for details. -gerrit

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Patch merged into coreboot/master: 931e590 baytrail: mrc_cache: check region erased before erasing
by gerrit＠coreboot.org 15 May '14

15 May '14

the following patch was just integrated into master: commit 931e59074556988dfc4a2f32fe7fa7874a4e064e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Mon Jan 13 11:34:51 2014 -0600 baytrail: mrc_cache: check region erased before erasing On a firmware update the MRC cache is destroyed. On the subsequent boot the MRC region was attempted to be erased even if it was already erased. This led to spi part taking longer than it should have for an unnecessary erase operation. Therefore, check that the region is erased before issuing the erease command. BUG=chrome-os-partner:24916 BRANCH=baytrail TEST=Booted after chromeos-firmeareupdate. Noted no error messages in this path. Change-Id: I6fadeb6bc5fc178abb0a7e3f0898855e481add2e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182153 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: http://review.coreboot.org/5043 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/5043 for details. -gerrit

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coreboot-gerrit May 2014