coreboot-gerrit May 2014

coreboot-gerrit@coreboot.org

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1066 discussions

New patch to review for coreboot: 7cbc109 build: reduce duplication in payload adding rules
by Patrick Georgi 17 May '14

17 May '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5763 -gerrit commit 7cbc10975291038579b00cc8cc77ca5a997f11ad Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Sat May 17 14:11:57 2014 +0200 build: reduce duplication in payload adding rules They're all the same, so treat them that way. Change-Id: I8e3976df1e3a0f9dbcf1d5373611f6197bc9701b Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- Makefile.inc | 29 ++++------------------------- 1 file changed, 4 insertions(+), 25 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 3205a10..b139403 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -482,12 +482,11 @@ $(obj)/coreboot.pre1: $(CBFSTOOL) endif ifeq ($(CONFIG_PAYLOAD_LINUX),y) -LINUX_ADDITIONAL_CONFIG:= ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_COMMAND_LINE))),) - LINUX_ADDITIONAL_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE) + ADDITIONAL_PAYLOAD_CONFIG+=-C $(CONFIG_LINUX_COMMAND_LINE) endif ifneq ($(strip $(call strip_quotes,$(CONFIG_LINUX_INITRD))),) - LINUX_ADDITIONAL_CONFIG+=-I $(CONFIG_LINUX_INITRD) + ADDITIONAL_PAYLOAD_CONFIG+=-I $(CONFIG_LINUX_INITRD) endif endif @@ -504,36 +503,16 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $(c ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf " PAYLOAD none (as specified by user)\n" endif -ifeq ($(CONFIG_PAYLOAD_ELF),y) - @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_PAYLOAD_LINUX),y) +ifneq ($(CONFIG_PAYLOAD_FILE),) @printf " PAYLOAD $(CONFIG_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(LINUX_ADDITIONAL_CONFIG) + $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) $(ADDITIONAL_PAYLOAD_CONFIG) endif -ifeq ($(CONFIG_PAYLOAD_SEABIOS),y) - @printf " PAYLOAD SeaBIOS (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),) ifneq ($(CONFIG_SEABIOS_PS2_TIMEOUT),0) @printf " SeaBIOS Wait up to $(CONFIG_SEABIOS_PS2_TIMEOUT) ms for PS/2 keyboard controller initialization\n" $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_PS2_TIMEOUT) -n etc/ps2-keyboard-spinup endif endif -endif -ifeq ($(CONFIG_PAYLOAD_FILO),y) - @printf " PAYLOAD FILO (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_PAYLOAD_GRUB2),y) - @printf " PAYLOAD GRUB2 (internal, compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif -ifeq ($(CONFIG_PAYLOAD_TIANOCORE),y) - @printf " PAYLOAD Tiano Core (compression: $(CBFS_PAYLOAD_COMPRESS_FLAG))\n" - $(CBFSTOOL) $@.tmp add-payload -f $(CONFIG_PAYLOAD_FILE) -n $(CONFIG_CBFS_PREFIX)/payload -c $(CBFS_PAYLOAD_COMPRESS_FLAG) -endif ifeq ($(CONFIG_INCLUDE_CONFIG_FILE),y) @printf " CONFIG $(DOTCONFIG)\n" if [ -f $(DOTCONFIG) ]; then \

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Patch set updated for coreboot: 8e74d6e vendorcode/amd/agesa: Silence warn of assigment in if-statement
by Edward O'Callaghan 16 May '14

16 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5759 -gerrit commit 8e74d6e072bb8c9339920713060a7444d3159468 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:22:17 2014 +1000 vendorcode/amd/agesa: Silence warn of assigment in if-statement Change-Id: I86a475a2ae101cc3ebfee742de0c75cacd352fbe Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c index c2f9372..20a90d5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c @@ -290,7 +290,7 @@ MemTDIMMPresence3 ( // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks. // - if (ChannelPtr->LrDimmPresent |= DimmMask) { + if ((ChannelPtr->LrDimmPresent |= DimmMask)) { // // LRDIMM Physical Ranks //

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Patch set updated for coreboot: 89470f8 vendorcode/amd/agesa: Implicit assigment between enum without cast
by Edward O'Callaghan 16 May '14

16 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5760 -gerrit commit 89470f84bdd5575a992ea80f64fb897e2b0bcc92 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:23:51 2014 +1000 vendorcode/amd/agesa: Implicit assigment between enum without cast Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c index 613aadd..9ff66f2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c @@ -186,7 +186,7 @@ MemNSyncTargetSpeedNb ( ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) : ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY)); - MemClkFreq = ChnlTmgMod[1]; + MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1]; } }

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Patch set updated for coreboot: 0a0b5c0 amd/agesa/*/gcc-intrin.h: Invaild inline asm
by Edward O'Callaghan 16 May '14

16 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5758 -gerrit commit 0a0b5c0c1e0c6061b9f57a876698bd41dab82a1c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:13:33 2014 +1000 amd/agesa/*/gcc-intrin.h: Invaild inline asm The 'm' (a memory reference) constraint makes little sense here since we are talking about a fs relative read, rather 'ir' (immediate or register) constraint is more sensible. N.B. The 'p' constraint allows anything which fits the form of an address calculation where the 'ir' constraint is just a register /xor/ immediate. Hence would produce better code here however, unfortunately, clang does not currently support it properly. The %b and %w constraints are also redundant and only hide errors. The functions writefsword() and writefsdword() should use ir instead of iq. iq is unnecessarily restrictive (it is only required for writing bytes). The cld in stosb is redundant (and the constraints are unnecessarily complicated). Line wrap these extraneously long lines found with these particular functions. Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 62 +++++++++++++++-------- 1 file changed, 40 insertions(+), 22 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 5ce3ee3..61ff215 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -1,7 +1,7 @@ /* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * + * Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2014, Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + #if defined (__GNUC__) /* I/O intrin functions. */ @@ -526,39 +526,57 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); } -static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) +static __inline__ __attribute__((always_inline)) void +__writefsbyte(const unsigned long Offset, const unsigned char Data) { - __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movb %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) +static __inline__ __attribute__((always_inline)) void +__writefsword(const unsigned long Offset, const unsigned short Data) { - __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movw %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) +static __inline__ __attribute__((always_inline)) void +__writefsdword(const unsigned long Offset, const unsigned long Data) { - __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movl %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "ir" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned char +__readfsbyte(const unsigned long Offset) { unsigned char value; - __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movb %%fs:%a[Offset], %b[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned short +__readfsword(const unsigned long Offset) { unsigned short value; - __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movw %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) +static __inline__ __attribute__((always_inline)) unsigned long long +__readfsdword(unsigned long long Offset) { unsigned long long value; - __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movl %%fs:%a[Offset], %[value]" + : [value] "=q" (value) + : [Offset] "ir" (Offset)); return value; } @@ -594,12 +612,12 @@ static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) { __builtin_ia32_sfence (); } -#endif +#endif /* __SSE3__ */ static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) { __asm__ __volatile__ ( - "cld ; rep ; stosb " + "rep ; stosb " : "=D" (dest), "=c" (count) : "a"(data), "0"(dest), "1" (count) );

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Patch set updated for coreboot: 5df3b18 vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdp
by Edward O'Callaghan 16 May '14

16 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5752 -gerrit commit 5df3b18855cfd4ae15993f5628197b1a7dbb29f8 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 19:37:24 2014 +1000 vendorcode/amd/agesa: Logic typo in GfxPowerPlayLocateTdp The function GfxPowerPlayLocateTdp() sets MinDeltaSclk to a maximum sentinel value and checks DeltaSclk in a loop to minimize MinDeltaSclk. However, MinDeltaSclk incorrectly self-assigns. Change-Id: Id01c792057681516bba411adec268769a3549aa8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 2 +- .../f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 12 ++++++------ .../Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c | 2 +- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index 6642c8a..7ecb6fa 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -211,7 +211,7 @@ GfxPowerPlayLocateTdp ( DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); if (DeltaSclk < MinDeltaSclk) { - MinDeltaSclk = MinDeltaSclk; + MinDeltaSclk = DeltaSclk; DpmIndex = Index; } } diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index feb6123..5f06eb6 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -17,7 +17,7 @@ * * Copyright (c) 2011, Advanced Micro Devices, Inc. * All rights reserved. - * + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -25,10 +25,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -39,7 +39,7 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * * *************************************************************************** * */ @@ -204,7 +204,7 @@ GfxPowerPlayLocateTdp ( DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); if (DeltaSclk < MinDeltaSclk) { - MinDeltaSclk = MinDeltaSclk; + MinDeltaSclk = DeltaSclk; DpmIndex = Index; } } diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c index 0c3e7a1..1bbb397 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbGfxInitLibV1/GfxPowerPlayTable.c @@ -147,7 +147,7 @@ GfxPowerPlayLocateTdp ( DpmSclk = GfxFmCalculateClock (PpFuses->SclkDpmDid[Index], StdHeader); DeltaSclk = (DpmSclk > Sclk) ? (DpmSclk - Sclk) : (Sclk - DpmSclk); if (DeltaSclk < MinDeltaSclk) { - MinDeltaSclk = MinDeltaSclk; + MinDeltaSclk = DeltaSclk; DpmIndex = Index; } }

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Patch set updated for coreboot: 8641b28 lenovo/t60: Enable dock serial port when undocked and redocked
by Damien Zammit 16 May '14

16 May '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5761 -gerrit commit 8641b283773ee666f65c786893678a67d4d97681 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri May 16 18:52:47 2014 +1000 lenovo/t60: Enable dock serial port when undocked and redocked When the system is started with dock, the serial port works. As soon as the laptop is undocked and redocked, the serial port no longer works. See below superiotool dump snippet: Upon bootup: SIO @ 0x2e LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 01 03 f8 04 03 04 04 02 Redocked: SIO @ 0x2e LDN 0x03 (COM1) idx 30 60 61 70 71 74 75 f0 val 00 03 f8 04 03 04 04 02 Since the function dock_connect is executed every time the dock is reconnected, starting without a dock and then attaching it to a dock is now also fixed. Change-Id: Ibd97589a8c743673a55e382a5db2ba62656c595e Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/lenovo/t60/dock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 9921457..b01f8e8 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -133,6 +133,10 @@ static int dock_superio_init(void) */ dock_write_register(0x22, 0xa9); + /* enable serial port */ + dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x30, 0x01); + dock_write_register(0x07, PC87384_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20);

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New patch to review for coreboot: 862be9f Lenovo T60: Enabled dock serial port when undocked and redocked
by Damien Zammit 16 May '14

16 May '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5761 -gerrit commit 862be9f126f323c28d96a719b9e94d0fc9161765 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri May 16 18:52:47 2014 +1000 Lenovo T60: Enabled dock serial port when undocked and redocked Change-Id: Ibd97589a8c743673a55e382a5db2ba62656c595e Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/lenovo/t60/dock.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/t60/dock.c b/src/mainboard/lenovo/t60/dock.c index 9921457..b01f8e8 100644 --- a/src/mainboard/lenovo/t60/dock.c +++ b/src/mainboard/lenovo/t60/dock.c @@ -133,6 +133,10 @@ static int dock_superio_init(void) */ dock_write_register(0x22, 0xa9); + /* enable serial port */ + dock_write_register(0x07, PC87384_SP1); + dock_write_register(0x30, 0x01); + dock_write_register(0x07, PC87384_GPIO); dock_write_register(0x60, 0x16); dock_write_register(0x61, 0x20);

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Patch set updated for coreboot: bff64dc vendorcode/amd/agesa: Silence warn of assigment in if-statement
by Edward O'Callaghan 15 May '14

15 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5759 -gerrit commit bff64dc21ead1efdafe8f99b3b2324b4f4af3b2a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:22:17 2014 +1000 vendorcode/amd/agesa: Silence warn of assigment in if-statement Change-Id: I86a475a2ae101cc3ebfee742de0c75cacd352fbe Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c index c2f9372..20a90d5 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/Tech/DDR3/mtspd3.c @@ -290,7 +290,7 @@ MemTDIMMPresence3 ( // as a QR RDIMM with a rank Mux of x1 and therefore all four CS will be used. So an 8R LRDIMM will // be marked as a QR even if Rank multiplication allows it to use only 2 logical ranks. // - if (ChannelPtr->LrDimmPresent |= DimmMask) { + if ((ChannelPtr->LrDimmPresent |= DimmMask)) { // // LRDIMM Physical Ranks //

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Patch set updated for coreboot: c2168d2 vendorcode/amd/agesa/*/gcc-intrin.h: Invaild inline asm
by Edward O'Callaghan 15 May '14

15 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5758 -gerrit commit c2168d2e6685444b6fda36480d6b26165257d385 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:13:33 2014 +1000 vendorcode/amd/agesa/*/gcc-intrin.h: Invaild inline asm The 'm' (a memory reference) constraint makes little sense here since we are talking about a fs relative read, rather 'ir' (immediate or register) constraint is more sensible. Line wrap these extraneously long lines found with these particular functions. N.B. The 'p' constraint allows anything which fits the form of an address calculation where the 'ir' constraint is just a register /xor/ immediate. Hence would produce better code here however, unfortunately, clang does not currently support it properly. Change-Id: Iaf3ad65791640e1060a2029e7ebb043f57b338a9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h | 60 +++++++++++++++-------- 1 file changed, 39 insertions(+), 21 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h index 5ce3ee3..310223f 100644 --- a/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h +++ b/src/vendorcode/amd/agesa/f14/Include/gcc-intrin.h @@ -1,7 +1,7 @@ /* - * Copyright (c) 2011, Advanced Micro Devices, Inc. - * All rights reserved. - * + * Copyright (c) 2011, Advanced Micro Devices, Inc. All rights reserved. + * Copyright (c) 2014, Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * Redistributions of source code must retain the above copyright @@ -9,10 +9,10 @@ * * Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * * Neither the name of Advanced Micro Devices, Inc. nor the names of - * its contributors may be used to endorse or promote products derived + * * Neither the name of Advanced Micro Devices, Inc. nor the names of + * its contributors may be used to endorse or promote products derived * from this software without specific prior written permission. - * + * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -23,9 +23,9 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * + * */ - + #if defined (__GNUC__) /* I/O intrin functions. */ @@ -526,39 +526,57 @@ static __inline__ __attribute__((always_inline)) void __lidt(void *Source) __asm__ __volatile__("lidt %0" : : "m"(*(short*)Source)); } -static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data) +static __inline__ __attribute__((always_inline)) void +__writefsbyte(const unsigned long Offset, const unsigned char Data) { - __asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movb %b[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data) +static __inline__ __attribute__((always_inline)) void +__writefsword(const unsigned long Offset, const unsigned short Data) { - __asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movw %w[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); } -static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data) +static __inline__ __attribute__((always_inline)) void +__writefsdword(const unsigned long Offset, const unsigned long Data) { - __asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data)); + __asm__ ("movl %[Data], %%fs:%a[Offset]" + : + : [Offset] "ir" (Offset), [Data] "iq" (Data)); } -static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned char +__readfsbyte(const unsigned long Offset) { unsigned char value; - __asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movb %%fs:%a[Offset], %b[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset) +static __inline__ __attribute__((always_inline)) unsigned short +__readfsword(const unsigned long Offset) { unsigned short value; - __asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movw %%fs:%a[Offset], %[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; } -static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset) +static __inline__ __attribute__((always_inline)) unsigned long long +__readfsdword(unsigned long long Offset) { unsigned long long value; - __asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset)); + __asm__ ("movl %%fs:%a[Offset], %[value]" + : [value] "=r" (value) + : [Offset] "ir" (Offset)); return value; } @@ -594,7 +612,7 @@ static __inline __attribute__(( __always_inline__)) void _mm_sfence (void) { __builtin_ia32_sfence (); } -#endif +#endif /* __SSE3__ */ static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count) {

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Patch set updated for coreboot: 1a2545b vendorcode/amd/agesa: Implicit assigment between enum without cast
by Edward O'Callaghan 15 May '14

15 May '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5760 -gerrit commit 1a2545beadfb205d7e26fe41cc1bc236a1bf5591 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu May 15 21:23:51 2014 +1000 vendorcode/amd/agesa: Implicit assigment between enum without cast Change-Id: I31632948ce69b2d1ff63b6c920016ed6fdf9e2f8 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c index 613aadd..9ff66f2 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Mem/NB/mnmct.c @@ -186,7 +186,7 @@ MemNSyncTargetSpeedNb ( ASSERT ((NBPtr->ChannelPtr->TechType == DDR3_TECHNOLOGY) ? ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) >= DDR667_FREQUENCY) : ((MEMORY_BUS_SPEED)(ChnlTmgMod[1]) <= DDR1066_FREQUENCY)); - MemClkFreq = ChnlTmgMod[1]; + MemClkFreq = (MEMORY_BUS_SPEED) ChnlTmgMod[1]; } }

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coreboot-gerrit May 2014