coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

1 participants
584 discussions

Patch set updated for coreboot: 92ab060 lib/dynamic_cbmem.c: Include `cbmem_console.h`
by Paul Menzel 08 Mar '14

08 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5351 -gerrit commit 92ab06044ce57fab822ae99682b5170c21b7b6be Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 11:37:46 2014 +0100 lib/dynamic_cbmem.c: Include `cbmem_console.h` Broken with commit 1d7541fe (console: Fix includes). Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/dynamic_cbmem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 322ead0..1382f1d 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,6 +21,7 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> +#include <console/cbmem_console.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h>

1 0

Patch set updated for coreboot: 5e899b6 lib/dynamic_cbmem.c: Fix missing include
by Kyösti Mälkki 08 Mar '14

08 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5351 -gerrit commit 5e899b65c00ac7894e77a7e1b7e614ac823fae20 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 11:37:46 2014 +0100 lib/dynamic_cbmem.c: Fix missing include Broken with commit 1d7541fe. Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/dynamic_cbmem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 322ead0..1382f1d 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,6 +21,7 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> +#include <console/cbmem_console.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h>

1 0

New patch to review for coreboot: 66b90a1 lib/dynamic_cbmem.c: Add prototype for `cbmemc_reinit()`
by Paul Menzel 08 Mar '14

08 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5351 -gerrit commit 66b90a1d136f3741f38897d0f525de4e1e1c80a2 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 11:37:46 2014 +0100 lib/dynamic_cbmem.c: Add prototype for `cbmemc_reinit()` Enabling CBMEM console for boards using dynamic CBMEM, board.i386/google/bolt board.i386/google/falco board.i386/google/peppy board.ARMV7/google/pit board.i386/google/rambi board.i386/google/slippy board.ARMV7/google/snow board.i386/intel/baskingridge board.i386/intel/cougar_canyon2 board.i386/intel/wtm2 the build fails with the error below. CC lib/dynamic_cbmem.ramstage.o src/lib/dynamic_cbmem.c: In function 'init_cbmem_pre_device': src/lib/dynamic_cbmem.c:425:2: error: implicit declaration of function 'cbmemc_reinit' [-Werror=implicit-function-declaration] cc1: all warnings being treated as errors make: *** [coreboot-builds/google_bolt/lib/dynamic_cbmem.ramstage.o] Error 1 Including the header file `cbmem_console.h` with the prototype for `cbmemc_reinit()` fixes this error. Change-Id: If41f9e08df98d79b7bbf740b1a5634d0140207be Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/lib/dynamic_cbmem.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 322ead0..1382f1d 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -21,6 +21,7 @@ #include <bootmem.h> #include <console/console.h> #include <cbmem.h> +#include <console/cbmem_console.h> #include <string.h> #include <stdlib.h> #include <arch/early_variables.h>

1 0

Patch set updated for coreboot: 251a592 console/Kconfig: Enable CBMEM console by default
by Paul Menzel 08 Mar '14

08 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5350 -gerrit commit 251a59207d133f17d393ef36a67092315e9e8275 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 10:46:52 2014 +0100 console/Kconfig: Enable CBMEM console by default Thanks to Kyösti Mälkki’s Google Summer of Code 2013 work, console output to CBMEM (CBMEM console) for ramstage messages works on all boards. For romstage messages it works for Intel boards from the i945 chipset on, but it does not work yet for AMD boards. The board status script under `util/board_status/` reads the coreboot messages from CBMEM, which are then uploaded to the board status repository. With CBMEM console disabled by default, currently no coreboot console messages are uploaded to the board status repository. Enabling CBMEM console by default improves this situation, so that at least ramstage messages are stored in the board status repository. Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/console/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index bb64f29..86c7cbb 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -202,7 +202,7 @@ config CONSOLE_NE2K_IO_PORT config CONSOLE_CBMEM bool "Send console output to a CBMEM buffer" - default n + default y help Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space.

1 0

New patch to review for coreboot: af83f30 console/Kconfig: Enable CBMEM console by default
by Paul Menzel 08 Mar '14

08 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5350 -gerrit commit af83f3015ab3de7df5587334732372c6416cbe3c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 10:46:52 2014 +0100 console/Kconfig: Enable CBMEM console by default Thanks to Kyösti Mälkki’s Google Summer of Code 2013 work, console output to CBMEM (CBMEM console) for ramstage messages works on all boards. For romstage messages it works for Intel boards from the i945 chipset on, but it does not work yet for AMD boards. The board status script under `util/board_status/` reads the coreboot messages from CBMEM, which are then uploaded to the board status repository. With CBMEM console disabled by default, currently no coreboot console messages are uploaded to the board status repository. Enabling CBMEM console by default improves this situation, so that at least ramstage messages are stored in the board status repository. Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/console/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index bb64f29..86c7cbb 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -202,7 +202,7 @@ config CONSOLE_NE2K_IO_PORT config CONSOLE_CBMEM bool "Send console output to a CBMEM buffer" - default n + default y help Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space.

1 0

Patch set updated for coreboot: 05d4277 Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs"
by Alexandru Gagniuc 07 Mar '14

07 Mar '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5177 -gerrit commit 05d4277af1804269e518757a9f55e639a0cba8f8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Sun Feb 9 14:50:50 2014 -0600 Revert "boardstatus/towiki: Declare southbridge=northbridge=cpu on SOCs" This reverts commit b845636ce67f6e7c96bf3fb3008738f596a5d5ce. This commit changed the board status script to describe all boards in terms of x86 terminology, such as CPU->southbridge->northbridge. This terminology does not apply to a number of SoCs, in which the buses are not connected via successive bridges, and as such it is misleading and misguided to describe ideas of southbridge and northbridge for these devices. Change-Id: I98ba24ee00b816bf20d507c6d313ec2946acaedf Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- util/board_status/to-wiki/towiki.sh | 24 +----------------------- 1 file changed, 1 insertion(+), 23 deletions(-) diff --git a/util/board_status/to-wiki/towiki.sh b/util/board_status/to-wiki/towiki.sh index 5632887..5244843 100755 --- a/util/board_status/to-wiki/towiki.sh +++ b/util/board_status/to-wiki/towiki.sh @@ -224,8 +224,6 @@ EOF case "$cpu" in ALLWINNER_A10) cpu_nice="Allwinner A10" - northbridge_nice="Allwinner A10" - southbridge_nice="Allwinner A10" socket_nice="?";; AMD_GEODE_*) cpu_nice="AMD Geode™ ${cpu#AMD_GEODE_}"; @@ -274,32 +272,22 @@ EOF socket_nice="Socket 939" ;; AMD_SC520) - cpu_nice="AMD Élan™ SC520"; - northbridge_nice="AMD Élan™ SC520"; - southbridge_nice="AMD Élan™ SC520"; + cpu_nice="AMD Élan™SC520"; socket_nice="—";; ARMLTD_CORTEX_A9) cpu_nice="ARM Cortex A9"; - northbridge_nice="ARM Cortex A9"; - southbridge_nice="ARM Cortex A9"; socket_nice="?";; DMP_VORTEX86EX) cpu_nice="DMP VORTEX86EX"; socket_nice="?";; SAMSUNG_EXYNOS5420) cpu_nice="Samsung Exynos 5420"; - northbridge_nice="Samsung Exynos 5420"; - southbridge_nice="Samsung Exynos 5420"; socket_nice="?";; SAMSUNG_EXYNOS5250) cpu_nice="Samsung Exynos 5250"; - northbridge_nice="Samsung Exynos 5250"; - southbridge_nice="Samsung Exynos 5250"; socket_nice="?";; TI_AM335X) cpu_nice="TI AM335X"; - southbridge_nice="TI AM335X"; - northbridge_nice="TI AM335X"; socket_nice="?";; INTEL_SLOT_1) cpu_nice="Intel® Pentium® II/III, Celeron®"; @@ -390,16 +378,6 @@ EOF socket_nice="$cpu";; esac - if [ x"$northbridge_nice" = x ]; then - if grep 'select SOC_INTEL_BAYTRAIL' "$vendor_board_dir/Kconfig" > /dev/null ; then - southbridge_nice="Intel® Baytrail" - northbridge_nice="Intel® Baytrail" - cpu_nice="Intel® Baytrail" - socket_nice="—" - fi - fi - - echo "|- bgcolor=\"#$color\"" echo "| $vendor_nice" echo -n "| [[Board:$vendor/$board|$board_nice]]"

1 0

Patch merged into coreboot/master: 3dea35e x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
by gerrit＠coreboot.org 07 Mar '14

07 Mar '14

the following patch was just integrated into master: commit 3dea35e5a1a69c600feb2c16eef5d957b85c46ee Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Feb 25 20:36:56 2014 -0600 x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option Boot speeds can be sped up by mirroring the payload into main memory before doing the actual loading. Systems that would benefit from this are typically Intel ones whose SPI are memory mapped. Without the SPI being cached all accesses to the payload in SPI while being loaded result in uncacheable accesses. Instead take advantage of the on-board SPI controller which has an internal cache and prefetcher by copying 64-byte cachelines using 32-bit word copies. Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> See http://review.coreboot.org/5305 for details. -gerrit

1 0

Patch set updated for coreboot: 062ead2 uart: Support multiple ports
by Kyösti Mälkki 07 Mar '14

07 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5342 -gerrit commit 062ead28c3a197afff1944b3686b48181bf1003d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 25 09:02:17 2014 +0200 uart: Support multiple ports The port for console remains to be a compile time constant. The Kconfig option is changed to select an UART port with index to avoid putting map of UART base addresses in Kconfigs. With this change it is possible to have other than debug console on different UART port. Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/Kconfig | 38 +++++------------- src/cpu/allwinner/a10/Kconfig | 49 ++---------------------- src/cpu/allwinner/a10/uart_console.c | 50 ++++++++---------------- src/cpu/samsung/exynos5250/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5250/uart.c | 23 ++++++----- src/cpu/samsung/exynos5420/Kconfig | 39 ++----------------- src/cpu/samsung/exynos5420/uart.c | 21 ++++++---- src/cpu/ti/am335x/uart.c | 24 +++++++----- src/drivers/uart/oxpcie_early.c | 2 +- src/drivers/uart/pl011.c | 15 +++----- src/drivers/uart/uart8250io.c | 18 ++++----- src/drivers/uart/uart8250mem.c | 16 ++++---- src/include/console/uart.h | 14 +++---- src/mainboard/emulation/qemu-armv7/Kconfig | 5 --- src/mainboard/emulation/qemu-armv7/Makefile.inc | 4 ++ src/mainboard/ti/beaglebone/Kconfig | 51 ++----------------------- 16 files changed, 114 insertions(+), 294 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index 9377a78..e46714f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -48,39 +48,21 @@ if CONSOLE_SERIAL comment "device-specific UART" depends on HAVE_UART_SPECIAL -choice - prompt "Serial port for 8250" - default CONSOLE_SERIAL_COM1 - depends on DRIVERS_UART_8250IO - -config CONSOLE_SERIAL_COM1 - bool "COM1/ttyS0, I/O port 0x3f8" - help - Serial console on COM1/ttyS0 at I/O port 0x3f8. -config CONSOLE_SERIAL_COM2 - bool "COM2/ttyS1, I/O port 0x2f8" - help - Serial console on COM2/ttyS1 at I/O port 0x2f8. -config CONSOLE_SERIAL_COM3 - bool "COM3/ttyS2, I/O port 0x3e8" - help - Serial console on COM3/ttyS2 at I/O port 0x3e8. -config CONSOLE_SERIAL_COM4 - bool "COM4/ttyS3, I/O port 0x2e8" - help - Serial console on COM4/ttyS3 at I/O port 0x2e8. - -endchoice +config CONSOLE_PORT + prompt "Index for UART port to use for console" + default 0 +# FIXME: Early programming in romstage is incorrect as we should +# program different LDN to actually change the physical port. config TTYS0_BASE hex depends on DRIVERS_UART_8250IO - default 0x3f8 if CONSOLE_SERIAL_COM1 - default 0x2f8 if CONSOLE_SERIAL_COM2 - default 0x3e8 if CONSOLE_SERIAL_COM3 - default 0x2e8 if CONSOLE_SERIAL_COM4 + default 0x3f8 if CONSOLE_PORT = 0 + default 0x2f8 if CONSOLE_PORT = 1 + default 0x3e8 if CONSOLE_PORT = 2 + default 0x2e8 if CONSOLE_PORT = 3 help - Map the COM port names to the respective I/O port. + Map the COM port number to the respective I/O port. choice prompt "Baud rate" diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 8512c38..5e3491d 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -73,51 +73,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -config CONSOLE_SERIAL_UART6 - bool "UART6" - help - Serial console on UART6 - -config CONSOLE_SERIAL_UART7 - bool "UART7" - help - Serial console on UART7 - -endchoice +config CONSOLE_PORT + int + default 0 endif # if CPU_ALLWINNER_A10 diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index 0b80938..cf2ac9e 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -14,28 +14,15 @@ #include <cpu/allwinner/a10/uart.h> -static void *get_console_uart_base_addr(void) +unsigned int uart_platform_base(int idx) { - /* This big block gets compiled to a constant, not a function call */ - if (CONFIG_CONSOLE_SERIAL_UART0) - return (void *)A1X_UART0_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART1) - return (void *)A1X_UART1_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART2) - return (void *)A1X_UART2_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART3) - return (void *)A1X_UART3_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART4) - return (void *)A1X_UART4_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART5) - return (void *)A1X_UART5_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART6) - return (void *)A1X_UART6_BASE; - else if (CONFIG_CONSOLE_SERIAL_UART7) - return (void *)A1X_UART7_BASE; - - /* If selection is invalid, default to UART0 */ - return (void *)A1X_UART0_BASE; + const unsigned int bases[] = { + A1X_UART0_BASE, A1X_UART1_BASE, A1X_UART2_BASE, A1X_UART3_BASE, + A1X_UART4_BASE, A1X_UART5_BASE, A1X_UART6_BASE, A1X_UART7_BASE, + }; + if (idx < sizeof(bases)/sizeof(bases[0])) + return bases[idx]; + return A1X_UART0_BASE; } /* FIXME: We assume clock is 24MHz, which may not be the case. */ @@ -44,14 +31,9 @@ unsigned int uart_platform_refclk(void) return 24000000; } -unsigned int uart_platform_base(int idx) -{ - return (unsigned int)get_console_uart_base_addr(); -} - -void uart_init(void) +void uart_init(int idx) { - void *uart_base = (void *) uart_platform_base(0); + void *uart_base = (void *) uart_platform_base(idx); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, default_baudrate(), @@ -59,19 +41,19 @@ void uart_init(void) a10_uart_enable_fifos(uart_base); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - void *uart_base = (void *) uart_platform_base(0); + void *uart_base = (void *) uart_platform_base(idx); return a10_uart_rx_blocking(uart_base); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - void *uart_base = (void *) uart_platform_base(0); + void *uart_base = (void *) uart_platform_base(idx); a10_uart_tx_blocking(uart_base, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -80,7 +62,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_CONSOLE_PORT); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 9320184..5775f59 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -88,41 +88,8 @@ config SYS_SDRAM_BASE hex default 0x40000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config CONSOLE_PORT + int + default 3 endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 5458e7b..07302e3 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -157,30 +157,35 @@ static void exynos5_uart_tx_flush(struct s5p_uart *uart) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + const unsigned int bases[] = { + 0x12c00000, 0x12c10000, 0x12c20000, 0x12c30000 + }; + if (idx < sizeof(bases)/sizeof(bases[0])) + return bases[idx]; + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(idx); exynos5_uart_tx_flush(uart); } diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 5f78cc5..6fa0efb 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -90,41 +90,8 @@ config SYS_SDRAM_BASE hex default 0x20000000 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x12c00000 if CONSOLE_SERIAL_UART0 - default 0x12c10000 if CONSOLE_SERIAL_UART1 - default 0x12c20000 if CONSOLE_SERIAL_UART2 - default 0x12c30000 if CONSOLE_SERIAL_UART3 - help - Map the UART names to the respective MMIO address. +config CONSOLE_PORT + int + default 3 endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index 0928111..c4e1443 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -149,28 +149,33 @@ static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + const unsigned int bases[] = { + 0x12c00000, 0x12c10000, 0x12c20000, 0x12c30000 + }; + if (idx < sizeof(bases)/sizeof(bases[0])) + return bases[idx]; + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(idx); exynos5_init_dev(uart); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(idx); return exynos5_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(idx); exynos5_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { /* Exynos5250 implements this too. */ } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index be41653..bfc733b 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -154,30 +154,36 @@ unsigned int uart_platform_refclk(void) unsigned int uart_platform_base(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + const unsigned int bases[] = { + 0x44e09000, 0x48022000, 0x48024000, + 0x481a6000, 0x481a8000, 0x481aa000 + }; + if (idx < sizeof(bases)/sizeof(bases[0])) + return bases[idx]; + return 0; } -void uart_init(void) +void uart_init(int idx) { - struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(idx); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); am335x_uart_init(uart, div); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(idx); return am335x_uart_rx_byte(uart); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(idx); am335x_uart_tx_byte(uart, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -186,7 +192,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_CONSOLE_PORT); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index b81fa89..d5370ba 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -97,7 +97,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_CONSOLE_PORT); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index b652f36..99b14f1 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -21,22 +21,17 @@ static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) *uart_base = (unsigned int)data; } -unsigned int uart_platform_base(int idx) +void uart_init(int idx) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -void uart_init(void) +void uart_tx_byte(int idx, unsigned char data) { -} - -void uart_tx_byte(unsigned char data) -{ - unsigned int *uart_base = (unsigned int *) uart_platform_base(0); + unsigned int *uart_base = (unsigned int *) uart_platform_base(idx); pl011_uart_tx_byte(uart_base, data); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { } @@ -50,7 +45,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_CONSOLE_PORT); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e1fb39b..8e96a9b 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -111,27 +111,27 @@ unsigned int uart_platform_base(int idx) return bases[idx]; } -void uart_init(void) +void uart_init(int idx) { unsigned int div; div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK, BAUDRATE_OVERSAMPLE); - uart8250_init(bases[0], div); + uart8250_init(uart_platform_base(idx), div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - uart8250_tx_byte(bases[0], data); + uart8250_tx_byte(uart_platform_base(idx), data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - return uart8250_rx_byte(bases[0]); + return uart8250_rx_byte(uart_platform_base(idx)); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - uart8250_tx_flush(bases[0]); + uart8250_tx_flush(uart_platform_base(idx)); } #ifndef __PRE_RAM__ @@ -139,7 +139,7 @@ void uart_fill_lb(void *data) { struct lb_serial serial; serial.type = LB_SERIAL_TYPE_IO_MAPPED; - serial.baseaddr = uart_platform_base(0); + serial.baseaddr = uart_platform_base(CONFIG_CONSOLE_PORT); serial.baud = default_baudrate(); lb_add_serial(&serial, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 5a186f0..976bcb6 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -89,9 +89,9 @@ static void uart8250_mem_init(unsigned base_port, unsigned divisor) write8(base_port + UART_LCR, CONFIG_TTYS0_LCS); } -void uart_init(void) +void uart_init(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; @@ -100,25 +100,25 @@ void uart_init(void) uart8250_mem_init(base, div); } -void uart_tx_byte(unsigned char data) +void uart_tx_byte(int idx, unsigned char data) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_byte(base, data); } -unsigned char uart_rx_byte(void) +unsigned char uart_rx_byte(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return 0xff; return uart8250_mem_rx_byte(base); } -void uart_tx_flush(void) +void uart_tx_flush(int idx) { - u32 base = uart_platform_base(0); + u32 base = uart_platform_base(idx); if (!base) return; uart8250_mem_tx_flush(base); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 566791a..d51bf2a 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -39,10 +39,10 @@ unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); -void uart_init(void); -void uart_tx_byte(unsigned char data); -void uart_tx_flush(void); -unsigned char uart_rx_byte(void); +void uart_init(int idx); +void uart_tx_byte(int idx, unsigned char data); +void uart_tx_flush(int idx); +unsigned char uart_rx_byte(int idx); unsigned int uart_platform_base(int idx); @@ -52,9 +52,9 @@ void oxford_remap(unsigned int new_base); (ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_SMM && CONFIG_DEBUG_SMI) #if __CONSOLE_SERIAL_ENABLE__ -#define __uart_init() uart_init() -#define __uart_tx_byte(x) uart_tx_byte(x); -#define __uart_tx_flush() uart_tx_flush() +#define __uart_init() uart_init(CONFIG_CONSOLE_PORT) +#define __uart_tx_byte(x) uart_tx_byte(CONFIG_CONSOLE_PORT, x); +#define __uart_tx_flush() uart_tx_flush(CONFIG_CONSOLE_PORT) #else #define __uart_init() #define __uart_tx_byte(x) diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index 040ed9c..6d04216 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -48,11 +48,6 @@ config DRAM_SIZE_MB int default 1024 -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x10009000 - # Memory map for qemu vexpress-a9: # # 0x0000_0000: jump instruction (by qemu) diff --git a/src/mainboard/emulation/qemu-armv7/Makefile.inc b/src/mainboard/emulation/qemu-armv7/Makefile.inc index d15495f..27461bb 100644 --- a/src/mainboard/emulation/qemu-armv7/Makefile.inc +++ b/src/mainboard/emulation/qemu-armv7/Makefile.inc @@ -21,3 +21,7 @@ ramstage-y += media.c bootblock-y += timer.c romstage-y += timer.c ramstage-y += timer.c + +bootblock-y += iomap.c +romstage-y += iomap.c +ramstage-y += iomap.c diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index c842a5d..41c4c35 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -61,54 +61,9 @@ config CBFS_HEADER_ROM_OFFSET hex default 0x10 -choice CONSOLE_SERIAL_UART_CHOICES - prompt "Serial Console UART" - default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL - -config CONSOLE_SERIAL_UART0 - bool "UART0" - help - Serial console on UART0 - -config CONSOLE_SERIAL_UART1 - bool "UART1" - help - Serial console on UART1 - -config CONSOLE_SERIAL_UART2 - bool "UART2" - help - Serial console on UART2 - -config CONSOLE_SERIAL_UART3 - bool "UART3" - help - Serial console on UART3 - -config CONSOLE_SERIAL_UART4 - bool "UART4" - help - Serial console on UART4 - -config CONSOLE_SERIAL_UART5 - bool "UART5" - help - Serial console on UART5 - -endchoice - -config CONSOLE_SERIAL_UART_ADDRESS - hex - depends on CONSOLE_SERIAL - default 0x44e09000 if CONSOLE_SERIAL_UART0 - default 0x48022000 if CONSOLE_SERIAL_UART1 - default 0x48024000 if CONSOLE_SERIAL_UART2 - default 0x481a6000 if CONSOLE_SERIAL_UART3 - default 0x481a8000 if CONSOLE_SERIAL_UART4 - default 0x481aa000 if CONSOLE_SERIAL_UART5 - help - Map the UART names to the respective MMIO address. +config CONSOLE_PORT + int + default 0 ################################################################# # stuff from smdk5250.h #

1 0

Patch set updated for coreboot: fde5560 console: Add console for GDB
by Kyösti Mälkki 07 Mar '14

07 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5343 -gerrit commit fde556051d2b72d8607485237a0b7ba376166d28 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jan 26 22:51:48 2014 +0200 console: Add console for GDB Change-Id: I90e05e8132889e788b92e055ee191f35add43bbc Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/c_start.S | 1 + src/arch/x86/lib/exception.c | 13 +++++++++++-- src/console/console.c | 24 ++++++++++++++++++++++++ src/include/console/streams.h | 6 ++++++ src/include/console/uart.h | 7 +++++++ src/include/console/usb.h | 10 ++++++++++ 6 files changed, 59 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S index 01ffa7c..839f259 100644 --- a/src/arch/x86/lib/c_start.S +++ b/src/arch/x86/lib/c_start.S @@ -84,6 +84,7 @@ _start: post_code(POST_PRE_HARDWAREMAIN) /* post fe */ #if CONFIG_GDB_WAIT + call gdb_hw_init call gdb_stub_breakpoint #endif call main diff --git a/src/arch/x86/lib/exception.c b/src/arch/x86/lib/exception.c index 9756949..f64b2e7 100644 --- a/src/arch/x86/lib/exception.c +++ b/src/arch/x86/lib/exception.c @@ -1,4 +1,5 @@ #include <console/console.h> +#include <console/streams.h> #include <string.h> #if CONFIG_GDB_STUB @@ -217,12 +218,17 @@ static char out_buffer[BUFMAX]; static inline void stub_putc(int ch) { - console_tx_byte(ch); + gdb_tx_byte(ch); +} + +static inline void stub_flush(void) +{ + gdb_tx_flush(); } static inline int stub_getc(void) { - return console_rx_byte(); + return gdb_rx_byte(); } static int hex(char ch) @@ -322,9 +328,11 @@ static int get_packet(char *buffer) if (checksum != xmitcsum) { stub_putc('-'); /* failed checksum */ + stub_flush(); } else { stub_putc('+'); /* successful transfer */ + stub_flush(); } } } while(checksum != xmitcsum); @@ -353,6 +361,7 @@ static void put_packet(char *buffer) stub_putc('#'); stub_putc(hexchars[checksum >> 4]); stub_putc(hexchars[checksum % 16]); + stub_flush(); } while ((stub_getc() & 0x7f) != '+'); diff --git a/src/console/console.c b/src/console/console.c index cd72596..396ca07 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -54,6 +54,30 @@ void console_tx_flush(void) __usb_tx_flush(); } + +#if CONFIG_GDB_STUB && !defined(__SMM__) +void gdb_hw_init(void) +{ + __gdb_hw_init(); +} + +void gdb_tx_byte(unsigned char byte) +{ + __gdb_tx_byte(byte); +} + +void gdb_tx_flush(void) +{ + __gdb_tx_flush(); +} + +unsigned char gdb_rx_byte(void) +{ + return __gdb_rx_byte(); +} +#endif + + void console_tx_nibble(unsigned nibble) { unsigned char digit; diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 550004e..cac7449 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -47,6 +47,12 @@ void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void); +/* For remote GDB debugging. */ +void gdb_hw_init(void); +void gdb_tx_byte(unsigned char byte); +void gdb_tx_flush(void); +unsigned char gdb_rx_byte(void); + /* Helpers for ROMCC console. */ void console_tx_nibble(unsigned nibble); void console_tx_hex8(unsigned char value); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index d51bf2a..0a85213 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -61,4 +61,11 @@ void oxford_remap(unsigned int new_base); #define __uart_tx_flush() #endif +#if 0 /* CONFIG_GDB_STUB_SERIAL && (ENV_ROMSTAGE || ENV_RAMSTAGE) */ +#define __gdb_hw_init() uart_init(CONFIG_GDB_PORT) +#define __gdb_tx_byte(x) uart_tx_byte(CONFIG_GDB_PORT, x); +#define __gdb_tx_flush() uart_tx_flush(CONFIG_GDB_PORT) +#define __gdb_rx_byte() uart_rx_byte(CONFIG_GDB_PORT) +#endif + #endif /* CONSOLE_UART_H */ diff --git a/src/include/console/usb.h b/src/include/console/usb.h index 31059cb..8c81e49 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -33,6 +33,9 @@ int usb_can_rx_byte(int idx); #define __CONSOLE_USB_ENABLE__ CONFIG_CONSOLE_USB && \ (ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE || ENV_RAMSTAGE) +#define __GDB_STUB_USB_ENABLE__ 0 /* CONFIG_GDB_STUB_USB */ && \ + (ENV_ROMSTAGE && CONFIG_USBDEBUG_IN_ROMSTAGE || ENV_RAMSTAGE) + #if __CONSOLE_USB_ENABLE__ #define __usbdebug_init() usbdebug_init() #define __usb_tx_byte(x) usb_tx_byte(0, x) @@ -43,4 +46,11 @@ int usb_can_rx_byte(int idx); #define __usb_tx_flush() #endif +#if __GDB_STUB_USB_ENABLE__ +#define __gdb_hw_init() usbdebug_init() +#define __gdb_tx_byte(x) usb_tx_byte(0, x) +#define __gdb_tx_flush() usb_tx_flush(0) +#define __gdb_rx_byte() usb_rx_byte(0) +#endif + #endif /* _CONSOLE_USB_H_ */

1 0

Patch set updated for coreboot: 696ebda console: Simplify the enable rules
by Kyösti Mälkki 07 Mar '14

07 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5340 -gerrit commit 696ebdacd9b8dea00e624ec8f5720a4a86a8327e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Feb 26 15:19:04 2014 +0200 console: Simplify the enable rules Consoles on CBMEM and USB have somewhat complex rules and dependencies when they can be active. Provide simple variables to test which stage of boot is being built. Change-Id: I2872d7b5c930b5b3b3a604caa529625163ed989a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/console/streams.h | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/include/console/streams.h b/src/include/console/streams.h index 9d4d3fc..550004e 100644 --- a/src/include/console/streams.h +++ b/src/include/console/streams.h @@ -18,6 +18,31 @@ #ifndef _CONSOLE_STREAMS_H_ #define _CONSOLE_STREAMS_H_ + +#if defined(__BOOTBLOCK__) || defined(__PRE_RAM__) && defined(__ROMCC__) +#define ENV_BOOTBLOCK 1 +#else +#define ENV_BOOTBLOCK 0 +#endif + +#if defined(__PRE_RAM__) && !defined(__ROMCC__) +#define ENV_ROMSTAGE 1 +#else +#define ENV_ROMSTAGE 0 +#endif + +#if !defined(__PRE_RAM__) && !defined(__SMM__) +#define ENV_RAMSTAGE 1 +#else +#define ENV_RAMSTAGE 0 +#endif + +#if defined(__SMM__) +#define ENV_SMM 1 +#else +#define ENV_SMM 0 +#endif + void console_hw_init(void); void console_tx_byte(unsigned char byte); void console_tx_flush(void);

1 0

← Newer
1
...
34
35
36
37
38
39
40
...
59
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2014