coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: ee353d4 intel/cougar_canyon2/romstage.c: Remove unneeded `cbmemc_reinit`
by Paul Menzel 09 Mar '14

09 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5352 -gerrit commit ee353d4b1b3c62275b4b959d4de90d0650939832 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 12:39:30 2014 +0100 intel/cougar_canyon2/romstage.c: Remove unneeded `cbmemc_reinit` Enabling CBMEM console for the Cougar Canyon 2 makes the build fail as there is no prototype for cbmemc_reinit. Rather than fix this problem, we can recognize that since commit cbf5bdfe6 CBMEM: Always select CAR_MIGRATION calling 'cbmemc_reinit()' in the board’s romstage is not needed anymore, so remove it. Change-Id: I4dff2d11f073e2829ab3b081b5460f66eead4640 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/intel/cougar_canyon2/romstage.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index afd7e25..76a2689 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -340,10 +340,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif /* * FSP returns to this function instead of main, so we can't return back

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Patch set updated for coreboot: 5ceef5b CBMEM console: Fix build for ARM
by Paul Menzel 09 Mar '14

09 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5356 -gerrit commit 5ceef5be82f135872b9f2d9cfdb78ba27dbe4349 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Mar 9 13:46:48 2014 +0200 CBMEM console: Fix build for ARM This preprocessor guard was used to disable CBMEM console from romstage of ROMCC boards. It unintentionally disabled it for ARM too as they do not have CACHE_AS_RAM selected. Option EARLY_CBMEM_INIT implies CAR migration which is required to have CBMEM console in romstage. This change should have been done in commit f8bf5a10 already, but we missed it. Change-Id: I03e95183be0e78bc7dd439d5fef5b10e54966dc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/console/cbmem_console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 69332aa..4f4a54f 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -19,7 +19,7 @@ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ -#if CONFIG_CACHE_AS_RAM || !defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) void cbmemc_init(void); void cbmemc_reinit(void); void cbmemc_tx_byte(unsigned char data);

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Patch set updated for coreboot: 798d195 console/Kconfig: Enable CBMEM console by default
by Paul Menzel 09 Mar '14

09 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5350 -gerrit commit 798d195db81dbcdb062eb90d8b91d737aba58996 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 10:46:52 2014 +0100 console/Kconfig: Enable CBMEM console by default Thanks to Kyösti Mälkki’s Google Summer of Code 2013 work, console output to CBMEM (CBMEM console) for ramstage messages works on all boards. Currently on AMD boards no romstage messages can be saved in CBMEM, so only messages from ramstage on will be stored in CBMEM. Other than that nothing changes. Enabling CBMEM console by default does not noticeably decrease boot time as the messages are directly written to CAR or RAM. The board status script under `util/board_status/` reads the coreboot messages from CBMEM, which are then uploaded to the board status repository. With CBMEM console disabled by default, currently no coreboot console messages are uploaded to the board status repository, although it is important to have those. Enabling CBMEM console by default improves this situation, so that for all boards at least ramstage messages are stored in the board status repository. Change-Id: I8d5a58c078325c43a0317bcfaafc722d039aab0b Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/console/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index bb64f29..86c7cbb 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -202,7 +202,7 @@ config CONSOLE_NE2K_IO_PORT config CONSOLE_CBMEM bool "Send console output to a CBMEM buffer" - default n + default y help Enable this to save the console output in a CBMEM buffer. This would allow to see coreboot console output from Linux space.

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Patch merged into coreboot/master: 9d5e900 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
by gerrit＠coreboot.org 09 Mar '14

09 Mar '14

the following patch was just integrated into master: commit 9d5e9007d6e6d89209bead7f562f3da6350911cf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 9 17:46:39 2014 +1100 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge. The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/5355 for details. -gerrit

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Patch set updated for coreboot: 9d5e900 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
by Edward O'Callaghan 09 Mar '14

09 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5355 -gerrit commit 9d5e9007d6e6d89209bead7f562f3da6350911cf Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 9 17:46:39 2014 +1100 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge. The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index b17bc6a..44f9c48 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -65,11 +65,11 @@ static void mainboard_enable(device_t dev) acpi_slp_type = acpi_get_sleep_type(); #endif - /* enable GPP CLK0 thru CLK1 */ - /* disable GPP CLK2 thru SLT_GFX_CLK */ + /* enable GPP CLK0 thru CLK3 (interleaved) */ + /* disable GPP CLK4 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); *(misc_mem_clk_cntrl + 0) = 0xFF; - *(misc_mem_clk_cntrl + 1) = 0x00; + *(misc_mem_clk_cntrl + 1) = 0xFF; *(misc_mem_clk_cntrl + 2) = 0x00; *(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00;

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Patch merged into coreboot/master: 56fc285 intel/jarrell: Apply ROMCC workaround
by gerrit＠coreboot.org 09 Mar '14

09 Mar '14

the following patch was just integrated into master: commit 56fc2858723187bc94160240b4a8af1250bcc443 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 6 16:32:18 2014 +0200 intel/jarrell: Apply ROMCC workaround Taken from intel/xe7501devkit, maybe it had same symptoms once. The call to ich5_watchdog_on() has side-effect of exploding the requirements for ROMCC internal arrays at compile-time. The hard-coded limit in question is MAX_RHS in util/romcc.c, the default of 127 comes from the rhs field defined with 7 bits. Before this patch intel/jarrell builds were using upto MAX_RHS=102, while other ROMCC boards built even with MAX_RHS=10. This workaround brings intel/jarrell to the same level. Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See http://review.coreboot.org/5348 for details. -gerrit

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Patch set updated for coreboot: aa687ac mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
by Edward O'Callaghan 09 Mar '14

09 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5355 -gerrit commit aa687ac341408229e0a27f19f8266b28a291fdb1 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 9 17:46:39 2014 +1100 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge. The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index b17bc6a..35c61fa 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -65,11 +65,11 @@ static void mainboard_enable(device_t dev) acpi_slp_type = acpi_get_sleep_type(); #endif - /* enable GPP CLK0 thru CLK1 */ + /* enable GPP CLK0 thru CLK3 (interleaved) */ /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); *(misc_mem_clk_cntrl + 0) = 0xFF; - *(misc_mem_clk_cntrl + 1) = 0x00; + *(misc_mem_clk_cntrl + 1) = 0xFF; *(misc_mem_clk_cntrl + 2) = 0x00; *(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00;

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New patch to review for coreboot: 0435c30 CBMEM console: Fix build for ARM
by Kyösti Mälkki 09 Mar '14

09 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5356 -gerrit commit 0435c30b4344e36bd100179173e6e4aed66796db Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Mar 9 13:46:48 2014 +0200 CBMEM console: Fix build for ARM This preprocessor guard was used to disable CBMEM console from romstage of ROMCC boards. It unintentionally disabled it for ARM too as the do not have CACHE_AS_RAM selected. Option EARLY_CBMEM_INIT implies CAR migration which is required to have CBMEM console in romstage. This change should have been done in commit f8bf5a10 already, but we missed it. Change-Id: I03e95183be0e78bc7dd439d5fef5b10e54966dc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/console/cbmem_console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/console/cbmem_console.h b/src/include/console/cbmem_console.h index 69332aa..4f4a54f 100644 --- a/src/include/console/cbmem_console.h +++ b/src/include/console/cbmem_console.h @@ -19,7 +19,7 @@ #ifndef _CONSOLE_CBMEM_CONSOLE_H_ #define _CONSOLE_CBMEM_CONSOLE_H_ -#if CONFIG_CACHE_AS_RAM || !defined(__PRE_RAM__) +#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) void cbmemc_init(void); void cbmemc_reinit(void); void cbmemc_tx_byte(unsigned char data);

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Patch set updated for coreboot: 0596d0b mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
by Edward O'Callaghan 09 Mar '14

09 Mar '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5355 -gerrit commit 0596d0b0f3de641115844e51f285128ae987309f Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sun Mar 9 17:46:39 2014 +1100 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge. The platform dependent mainboard.c was incorrectly disabling the second clock signal feeding the GPP ports. This results in spurious hangs by calling the set_pcie_dereset() SB CIMx callback many times. This also stops coreboot from finding the second NIC behind the pci 15.0 bridge. Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c index b17bc6a..97f9417 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c +++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c @@ -69,7 +69,7 @@ static void mainboard_enable(device_t dev) /* disable GPP CLK2 thru SLT_GFX_CLK */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE); *(misc_mem_clk_cntrl + 0) = 0xFF; - *(misc_mem_clk_cntrl + 1) = 0x00; + *(misc_mem_clk_cntrl + 1) = 0xFF; *(misc_mem_clk_cntrl + 2) = 0x00; *(misc_mem_clk_cntrl + 3) = 0x00; *(misc_mem_clk_cntrl + 4) = 0x00;

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Patch set updated for coreboot: f05cca0 intel/cougar_canyon2/romstage.c: Remove unneeded `cbmemc_reinit`
by Paul Menzel 09 Mar '14

09 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5352 -gerrit commit f05cca09b3ab5ace5008596e609cdfb1f3ed5985 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Mar 8 12:39:30 2014 +0100 intel/cougar_canyon2/romstage.c: Remove unneeded `cbmemc_reinit` Enabling CBMEM console for the Cougar Canyon 2 makes the build fail as there is no prototype for cbmemc_reinit. Rather than fix this problem, we can recognize that since commit cbf5bdfe6 CBMEM: Always select CAR_MIGRATION calling 'cbmemc_reinit()' in the board’s romstage is not needed anymore, so remove it. Change-Id: I4dff2d11f073e2829ab3b081b5460f66eead4640 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/mainboard/intel/cougar_canyon2/romstage.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index afd7e25..76a2689 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -340,10 +340,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { timestamp_add(TS_AFTER_INITRAM, after_initram_time); timestamp_add_now(TS_END_ROMSTAGE); #endif -#if CONFIG_CONSOLE_CBMEM - /* Keep this the last thing this function does. */ - cbmemc_reinit(); -#endif /* * FSP returns to this function instead of main, so we can't return back

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coreboot-gerrit March 2014