Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5352
-gerrit
commit 4fcc6c0dea9f8848b047a295c0ae34c0af8d6102
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Mar 8 12:39:30 2014 +0100
intel/cougar_canyon2/romstage.c: Remove un-needed `cbmemc_reinit`
Enabling CBMEM console for the Cougar Canyon 2 makes the build fail
as there is no prototype for cbmemc_reinit.
Rather than fix this problem, we can recognize that since commit
cbf5bdfe6 CBMEM: Always select CAR_MIGRATION
calling 'cbmemc_reinit()' in the board’s romstage is not needed anymore,
so remove it.
Change-Id: I4dff2d11f073e2829ab3b081b5460f66eead4640
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/mainboard/intel/cougar_canyon2/romstage.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index afd7e25..76a2689 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -340,10 +340,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
-#if CONFIG_CONSOLE_CBMEM
- /* Keep this the last thing this function does. */
- cbmemc_reinit();
-#endif
/*
* FSP returns to this function instead of main, so we can't return back
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5352
-gerrit
commit 8bf45c205491c996f729e81fb90d285fd916ac78
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Mar 8 12:39:30 2014 +0100
intel/cougar_canyon2/romstage.c: Remove un-needed `cbmemc_reinit`
Enabling CBMEM console for the Cougar Canyon 2 makes the build fail
as there is no prototype for cbmemc_reinit.
Rather than fix this problem, we can recognize that since commit
cbf5bdfe6 (CBMEM: Always select CAR_MIGRATION) calling 'cbmemc_reinit()'
in the board’s romstage is not needed anymore, so remove it.
Change-Id: I4dff2d11f073e2829ab3b081b5460f66eead4640
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/mainboard/intel/cougar_canyon2/romstage.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index afd7e25..76a2689 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -340,10 +340,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
-#if CONFIG_CONSOLE_CBMEM
- /* Keep this the last thing this function does. */
- cbmemc_reinit();
-#endif
/*
* FSP returns to this function instead of main, so we can't return back
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5355
-gerrit
commit d2878c9af9c27a2ef0f1241b001b4931b1efef81
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun Mar 9 17:46:39 2014 +1100
mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
The platform dependant mainboard.c was incorrectly disabling the
second clock signal feeding the GPP ports. This results in
spurious hangs by calling the set_pcie_dereset() SB CIMx callback
many times. This also stops coreboot from finding the second NIC
behind the pci 15.0 bridge.
Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index b17bc6a..97f9417 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -69,7 +69,7 @@ static void mainboard_enable(device_t dev)
/* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
*(misc_mem_clk_cntrl + 0) = 0xFF;
- *(misc_mem_clk_cntrl + 1) = 0x00;
+ *(misc_mem_clk_cntrl + 1) = 0xFF;
*(misc_mem_clk_cntrl + 2) = 0x00;
*(misc_mem_clk_cntrl + 3) = 0x00;
*(misc_mem_clk_cntrl + 4) = 0x00;
Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5355
-gerrit
commit 31b31f9680c900286914b5b9168a56c63a2cc8fb
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Sun Mar 9 17:46:39 2014 +1100
mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
The platform dependant mainboard.c was incorrectly disabling the
second clock signal feeding the GPP ports. This results in
spurious hangs by calling the set_pcie_dereset() SB CIMx callback
many times. This also stops CB from finding the second NIC behind
the pci 15.0 bridge.
Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
---
src/mainboard/jetway/nf81-t56n-lf/mainboard.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
index b17bc6a..97f9417 100644
--- a/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
+++ b/src/mainboard/jetway/nf81-t56n-lf/mainboard.c
@@ -69,7 +69,7 @@ static void mainboard_enable(device_t dev)
/* disable GPP CLK2 thru SLT_GFX_CLK */
u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);
*(misc_mem_clk_cntrl + 0) = 0xFF;
- *(misc_mem_clk_cntrl + 1) = 0x00;
+ *(misc_mem_clk_cntrl + 1) = 0xFF;
*(misc_mem_clk_cntrl + 2) = 0x00;
*(misc_mem_clk_cntrl + 3) = 0x00;
*(misc_mem_clk_cntrl + 4) = 0x00;
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5352
-gerrit
commit fa94ae0d72524bb868e765d166875d91a14e0bbe
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Mar 8 12:39:30 2014 +0100
intel/cougar_canyon2/romstage.c: Remove un-needed 'cbmemc_reinit`
Enabling CBMEM console for the Cougar Canyon 2 makes the build fail
as there is no prototype for cbmemc_reinit.
Rather than fix this problem, we can recognize that since
commit cbf5bdfe6 (CBMEM: Always select CAR_MIGRATION) calling
'cbmemc_reinit()'
in the board’s romstage is not needed anymore, so remove it.
Change-Id: I4dff2d11f073e2829ab3b081b5460f66eead4640
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
---
src/mainboard/intel/cougar_canyon2/romstage.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c
index afd7e25..76a2689 100644
--- a/src/mainboard/intel/cougar_canyon2/romstage.c
+++ b/src/mainboard/intel/cougar_canyon2/romstage.c
@@ -340,10 +340,6 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) {
timestamp_add(TS_AFTER_INITRAM, after_initram_time);
timestamp_add_now(TS_END_ROMSTAGE);
#endif
-#if CONFIG_CONSOLE_CBMEM
- /* Keep this the last thing this function does. */
- cbmemc_reinit();
-#endif
/*
* FSP returns to this function instead of main, so we can't return back
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5348
-gerrit
commit 56fc2858723187bc94160240b4a8af1250bcc443
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Thu Mar 6 16:32:18 2014 +0200
intel/jarrell: Apply ROMCC workaround
Taken from intel/xe7501devkit, maybe it had same symptoms once.
The call to ich5_watchdog_on() has side-effect of exploding the
requirements for ROMCC internal arrays at compile-time. The hard-coded
limit in question is MAX_RHS in util/romcc.c, the default of 127 comes
from the rhs field defined with 7 bits.
Before this patch intel/jarrell builds were using upto MAX_RHS=102, while
other ROMCC boards built even with MAX_RHS=10. This workaround brings
intel/jarrell to the same level.
Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/mainboard/intel/jarrell/romstage.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/src/mainboard/intel/jarrell/romstage.c b/src/mainboard/intel/jarrell/romstage.c
index c6f014c..bddb34a 100644
--- a/src/mainboard/intel/jarrell/romstage.c
+++ b/src/mainboard/intel/jarrell/romstage.c
@@ -102,4 +102,8 @@ static void main(unsigned long bist)
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
+ /* NOTE: ROMCC dies with an internal compiler error if the
+ * following line is removed.
+ */
+ print_debug("SDRAM is up.\n");
}
the following patch was just integrated into master:
commit a8eadb527e793d887ba73e5478ea614734cd72b6
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Fri Mar 7 10:40:21 2014 +0200
ROMCC: Trigger internal compiler failure and apply the workaround
These boards first failed when attempting to change print_err() from
direct function call to console_tx_XX() to a code block in the form of
do { if (y) console_tx_XX(x); } while(0)
Removing the label dummy_romcc_workaround_label added here will
trigger the following compiler error for the two boards:
Internal compiler error: no edge to block->last->next
Change-Id: I997adfaf586d7fa2096401dd574b07ce676d0ac6
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
See http://review.coreboot.org/5349 for details.
-gerrit
Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5354
-gerrit
commit 95f8389e8a9c9e5d352e89e3ca7bd7f3c161e8b8
Author: Ronald G. Minnich <rminnich(a)gmail.com>
Date: Sat Mar 8 17:33:12 2014 +0100
Enable pages. Testing for now. Do not commit
Enable paging in coreboot. We're going to have to do this at some point,
when we hit x86_64; the ARM ports do paging in both 32- and 64-bit modes;
MTRR is a PITA; and it's easy.
This trial example just sets up a 4G identity map using 4M pages.
Not tested, just wanted to save it somewhere. The code is known to work
as I've used it other places.
If this works I'll add the code later to manipulate page tables.
IMHO we use this for machines where coreboot can live in the low 4G.
For other cases, it's time to start thinking about 64-bit mode. The
ARM V8 port is carving the way so this is as good a time as any.
This code is enabled by CONFIG_PGE, which defaults to n.
To turn it on navigate to architecture options in
menuconfig.
A remaining question is whether to turn off paging when we start the payload.
I tend to vote 'not', since, again, ARM shows we don't have too. But we'll
burn that bikeshed when we come to it. Many kernels do, however, know how to
manage starting up from a bootstrap with paging enabled.
Change-Id: Iea0192e5187c47e63d25f88eaa3e88cb6c58feb1
Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com>
---
src/arch/x86/Kconfig | 11 ++++
src/arch/x86/lib/c_start.S | 20 +++++++
src/arch/x86/lib/makepg.c | 11 ++++
src/arch/x86/lib/pagetables.S | 130 ++++++++++++++++++++++++++++++++++++++++++
4 files changed, 172 insertions(+)
diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig
index 8854e6b..0c0f91c 100644
--- a/src/arch/x86/Kconfig
+++ b/src/arch/x86/Kconfig
@@ -78,6 +78,17 @@ config UPDATE_IMAGE
is a suitable file for further processing.
The bootblock will not be modified.
+config PGE
+ bool "Enable x86 page tables."
+ default n
+ help
+ In original coreboot we did not use page tables. The
+ MTRR code just keeps getting messier and if we turn
+ on paging it gets very easy. We can enable disable
+ caching on anything down to a 4k boundary. We can
+ control cache disable and write-back/writethrough
+ on each page. For now, this code creates an identity
+ map for 4G using 4M pages.
config ROMCC
bool
default n
diff --git a/src/arch/x86/lib/c_start.S b/src/arch/x86/lib/c_start.S
index 01ffa7c..831ebb1 100644
--- a/src/arch/x86/lib/c_start.S
+++ b/src/arch/x86/lib/c_start.S
@@ -31,6 +31,26 @@ _start:
movl %eax, %gs
post_code(POST_ENTRY_C_START) /* post 13 */
+#ifdef CONFIG_PGE
+ jmp code
+
+#include "pagetables.S"
+
+code:
+ movl $pagetables, %ecx /* load address of page directory */
+ movl %ecx, %cr3
+ jmp 1f
+1:
+
+ movl %cr0, %edx
+ orl $0x80010000, %edx /* PG|WP */
+ andl $~0x6000000A, %edx /* ~(CD|NW|TS|MP) */
+
+ movl $paging, %eax
+ movl %edx, %cr0
+ jmp *%eax
+paging:
+#endif
cld
diff --git a/src/arch/x86/lib/makepg.c b/src/arch/x86/lib/makepg.c
new file mode 100644
index 0000000..9ffa7fd
--- /dev/null
+++ b/src/arch/x86/lib/makepg.c
@@ -0,0 +1,11 @@
+#include <stdio.h>
+main(int argc, char *argv[])
+{
+ int i, j;
+ for(i = 0; i < 1024; i += 8){
+ printf("\t.long ");
+ for(j = 0; j < 8; j++)
+ printf("0x%08x,", ((i+j)<<22) + 0x105);
+ printf("\n");
+ }
+}
diff --git a/src/arch/x86/lib/pagetables.S b/src/arch/x86/lib/pagetables.S
new file mode 100644
index 0000000..beff3ef
--- /dev/null
+++ b/src/arch/x86/lib/pagetables.S
@@ -0,0 +1,130 @@
+pagetables:
+ .align 4096
+ .long 0x00000105,0x00400105,0x00800105,0x00c00105,0x01000105,0x01400105,0x01800105,0x01c00105
+ .long 0x02000105,0x02400105,0x02800105,0x02c00105,0x03000105,0x03400105,0x03800105,0x03c00105
+ .long 0x04000105,0x04400105,0x04800105,0x04c00105,0x05000105,0x05400105,0x05800105,0x05c00105
+ .long 0x06000105,0x06400105,0x06800105,0x06c00105,0x07000105,0x07400105,0x07800105,0x07c00105
+ .long 0x08000105,0x08400105,0x08800105,0x08c00105,0x09000105,0x09400105,0x09800105,0x09c00105
+ .long 0x0a000105,0x0a400105,0x0a800105,0x0ac00105,0x0b000105,0x0b400105,0x0b800105,0x0bc00105
+ .long 0x0c000105,0x0c400105,0x0c800105,0x0cc00105,0x0d000105,0x0d400105,0x0d800105,0x0dc00105
+ .long 0x0e000105,0x0e400105,0x0e800105,0x0ec00105,0x0f000105,0x0f400105,0x0f800105,0x0fc00105
+ .long 0x10000105,0x10400105,0x10800105,0x10c00105,0x11000105,0x11400105,0x11800105,0x11c00105
+ .long 0x12000105,0x12400105,0x12800105,0x12c00105,0x13000105,0x13400105,0x13800105,0x13c00105
+ .long 0x14000105,0x14400105,0x14800105,0x14c00105,0x15000105,0x15400105,0x15800105,0x15c00105
+ .long 0x16000105,0x16400105,0x16800105,0x16c00105,0x17000105,0x17400105,0x17800105,0x17c00105
+ .long 0x18000105,0x18400105,0x18800105,0x18c00105,0x19000105,0x19400105,0x19800105,0x19c00105
+ .long 0x1a000105,0x1a400105,0x1a800105,0x1ac00105,0x1b000105,0x1b400105,0x1b800105,0x1bc00105
+ .long 0x1c000105,0x1c400105,0x1c800105,0x1cc00105,0x1d000105,0x1d400105,0x1d800105,0x1dc00105
+ .long 0x1e000105,0x1e400105,0x1e800105,0x1ec00105,0x1f000105,0x1f400105,0x1f800105,0x1fc00105
+ .long 0x20000105,0x20400105,0x20800105,0x20c00105,0x21000105,0x21400105,0x21800105,0x21c00105
+ .long 0x22000105,0x22400105,0x22800105,0x22c00105,0x23000105,0x23400105,0x23800105,0x23c00105
+ .long 0x24000105,0x24400105,0x24800105,0x24c00105,0x25000105,0x25400105,0x25800105,0x25c00105
+ .long 0x26000105,0x26400105,0x26800105,0x26c00105,0x27000105,0x27400105,0x27800105,0x27c00105
+ .long 0x28000105,0x28400105,0x28800105,0x28c00105,0x29000105,0x29400105,0x29800105,0x29c00105
+ .long 0x2a000105,0x2a400105,0x2a800105,0x2ac00105,0x2b000105,0x2b400105,0x2b800105,0x2bc00105
+ .long 0x2c000105,0x2c400105,0x2c800105,0x2cc00105,0x2d000105,0x2d400105,0x2d800105,0x2dc00105
+ .long 0x2e000105,0x2e400105,0x2e800105,0x2ec00105,0x2f000105,0x2f400105,0x2f800105,0x2fc00105
+ .long 0x30000105,0x30400105,0x30800105,0x30c00105,0x31000105,0x31400105,0x31800105,0x31c00105
+ .long 0x32000105,0x32400105,0x32800105,0x32c00105,0x33000105,0x33400105,0x33800105,0x33c00105
+ .long 0x34000105,0x34400105,0x34800105,0x34c00105,0x35000105,0x35400105,0x35800105,0x35c00105
+ .long 0x36000105,0x36400105,0x36800105,0x36c00105,0x37000105,0x37400105,0x37800105,0x37c00105
+ .long 0x38000105,0x38400105,0x38800105,0x38c00105,0x39000105,0x39400105,0x39800105,0x39c00105
+ .long 0x3a000105,0x3a400105,0x3a800105,0x3ac00105,0x3b000105,0x3b400105,0x3b800105,0x3bc00105
+ .long 0x3c000105,0x3c400105,0x3c800105,0x3cc00105,0x3d000105,0x3d400105,0x3d800105,0x3dc00105
+ .long 0x3e000105,0x3e400105,0x3e800105,0x3ec00105,0x3f000105,0x3f400105,0x3f800105,0x3fc00105
+ .long 0x40000105,0x40400105,0x40800105,0x40c00105,0x41000105,0x41400105,0x41800105,0x41c00105
+ .long 0x42000105,0x42400105,0x42800105,0x42c00105,0x43000105,0x43400105,0x43800105,0x43c00105
+ .long 0x44000105,0x44400105,0x44800105,0x44c00105,0x45000105,0x45400105,0x45800105,0x45c00105
+ .long 0x46000105,0x46400105,0x46800105,0x46c00105,0x47000105,0x47400105,0x47800105,0x47c00105
+ .long 0x48000105,0x48400105,0x48800105,0x48c00105,0x49000105,0x49400105,0x49800105,0x49c00105
+ .long 0x4a000105,0x4a400105,0x4a800105,0x4ac00105,0x4b000105,0x4b400105,0x4b800105,0x4bc00105
+ .long 0x4c000105,0x4c400105,0x4c800105,0x4cc00105,0x4d000105,0x4d400105,0x4d800105,0x4dc00105
+ .long 0x4e000105,0x4e400105,0x4e800105,0x4ec00105,0x4f000105,0x4f400105,0x4f800105,0x4fc00105
+ .long 0x50000105,0x50400105,0x50800105,0x50c00105,0x51000105,0x51400105,0x51800105,0x51c00105
+ .long 0x52000105,0x52400105,0x52800105,0x52c00105,0x53000105,0x53400105,0x53800105,0x53c00105
+ .long 0x54000105,0x54400105,0x54800105,0x54c00105,0x55000105,0x55400105,0x55800105,0x55c00105
+ .long 0x56000105,0x56400105,0x56800105,0x56c00105,0x57000105,0x57400105,0x57800105,0x57c00105
+ .long 0x58000105,0x58400105,0x58800105,0x58c00105,0x59000105,0x59400105,0x59800105,0x59c00105
+ .long 0x5a000105,0x5a400105,0x5a800105,0x5ac00105,0x5b000105,0x5b400105,0x5b800105,0x5bc00105
+ .long 0x5c000105,0x5c400105,0x5c800105,0x5cc00105,0x5d000105,0x5d400105,0x5d800105,0x5dc00105
+ .long 0x5e000105,0x5e400105,0x5e800105,0x5ec00105,0x5f000105,0x5f400105,0x5f800105,0x5fc00105
+ .long 0x60000105,0x60400105,0x60800105,0x60c00105,0x61000105,0x61400105,0x61800105,0x61c00105
+ .long 0x62000105,0x62400105,0x62800105,0x62c00105,0x63000105,0x63400105,0x63800105,0x63c00105
+ .long 0x64000105,0x64400105,0x64800105,0x64c00105,0x65000105,0x65400105,0x65800105,0x65c00105
+ .long 0x66000105,0x66400105,0x66800105,0x66c00105,0x67000105,0x67400105,0x67800105,0x67c00105
+ .long 0x68000105,0x68400105,0x68800105,0x68c00105,0x69000105,0x69400105,0x69800105,0x69c00105
+ .long 0x6a000105,0x6a400105,0x6a800105,0x6ac00105,0x6b000105,0x6b400105,0x6b800105,0x6bc00105
+ .long 0x6c000105,0x6c400105,0x6c800105,0x6cc00105,0x6d000105,0x6d400105,0x6d800105,0x6dc00105
+ .long 0x6e000105,0x6e400105,0x6e800105,0x6ec00105,0x6f000105,0x6f400105,0x6f800105,0x6fc00105
+ .long 0x70000105,0x70400105,0x70800105,0x70c00105,0x71000105,0x71400105,0x71800105,0x71c00105
+ .long 0x72000105,0x72400105,0x72800105,0x72c00105,0x73000105,0x73400105,0x73800105,0x73c00105
+ .long 0x74000105,0x74400105,0x74800105,0x74c00105,0x75000105,0x75400105,0x75800105,0x75c00105
+ .long 0x76000105,0x76400105,0x76800105,0x76c00105,0x77000105,0x77400105,0x77800105,0x77c00105
+ .long 0x78000105,0x78400105,0x78800105,0x78c00105,0x79000105,0x79400105,0x79800105,0x79c00105
+ .long 0x7a000105,0x7a400105,0x7a800105,0x7ac00105,0x7b000105,0x7b400105,0x7b800105,0x7bc00105
+ .long 0x7c000105,0x7c400105,0x7c800105,0x7cc00105,0x7d000105,0x7d400105,0x7d800105,0x7dc00105
+ .long 0x7e000105,0x7e400105,0x7e800105,0x7ec00105,0x7f000105,0x7f400105,0x7f800105,0x7fc00105
+ .long 0x80000105,0x80400105,0x80800105,0x80c00105,0x81000105,0x81400105,0x81800105,0x81c00105
+ .long 0x82000105,0x82400105,0x82800105,0x82c00105,0x83000105,0x83400105,0x83800105,0x83c00105
+ .long 0x84000105,0x84400105,0x84800105,0x84c00105,0x85000105,0x85400105,0x85800105,0x85c00105
+ .long 0x86000105,0x86400105,0x86800105,0x86c00105,0x87000105,0x87400105,0x87800105,0x87c00105
+ .long 0x88000105,0x88400105,0x88800105,0x88c00105,0x89000105,0x89400105,0x89800105,0x89c00105
+ .long 0x8a000105,0x8a400105,0x8a800105,0x8ac00105,0x8b000105,0x8b400105,0x8b800105,0x8bc00105
+ .long 0x8c000105,0x8c400105,0x8c800105,0x8cc00105,0x8d000105,0x8d400105,0x8d800105,0x8dc00105
+ .long 0x8e000105,0x8e400105,0x8e800105,0x8ec00105,0x8f000105,0x8f400105,0x8f800105,0x8fc00105
+ .long 0x90000105,0x90400105,0x90800105,0x90c00105,0x91000105,0x91400105,0x91800105,0x91c00105
+ .long 0x92000105,0x92400105,0x92800105,0x92c00105,0x93000105,0x93400105,0x93800105,0x93c00105
+ .long 0x94000105,0x94400105,0x94800105,0x94c00105,0x95000105,0x95400105,0x95800105,0x95c00105
+ .long 0x96000105,0x96400105,0x96800105,0x96c00105,0x97000105,0x97400105,0x97800105,0x97c00105
+ .long 0x98000105,0x98400105,0x98800105,0x98c00105,0x99000105,0x99400105,0x99800105,0x99c00105
+ .long 0x9a000105,0x9a400105,0x9a800105,0x9ac00105,0x9b000105,0x9b400105,0x9b800105,0x9bc00105
+ .long 0x9c000105,0x9c400105,0x9c800105,0x9cc00105,0x9d000105,0x9d400105,0x9d800105,0x9dc00105
+ .long 0x9e000105,0x9e400105,0x9e800105,0x9ec00105,0x9f000105,0x9f400105,0x9f800105,0x9fc00105
+ .long 0xa0000105,0xa0400105,0xa0800105,0xa0c00105,0xa1000105,0xa1400105,0xa1800105,0xa1c00105
+ .long 0xa2000105,0xa2400105,0xa2800105,0xa2c00105,0xa3000105,0xa3400105,0xa3800105,0xa3c00105
+ .long 0xa4000105,0xa4400105,0xa4800105,0xa4c00105,0xa5000105,0xa5400105,0xa5800105,0xa5c00105
+ .long 0xa6000105,0xa6400105,0xa6800105,0xa6c00105,0xa7000105,0xa7400105,0xa7800105,0xa7c00105
+ .long 0xa8000105,0xa8400105,0xa8800105,0xa8c00105,0xa9000105,0xa9400105,0xa9800105,0xa9c00105
+ .long 0xaa000105,0xaa400105,0xaa800105,0xaac00105,0xab000105,0xab400105,0xab800105,0xabc00105
+ .long 0xac000105,0xac400105,0xac800105,0xacc00105,0xad000105,0xad400105,0xad800105,0xadc00105
+ .long 0xae000105,0xae400105,0xae800105,0xaec00105,0xaf000105,0xaf400105,0xaf800105,0xafc00105
+ .long 0xb0000105,0xb0400105,0xb0800105,0xb0c00105,0xb1000105,0xb1400105,0xb1800105,0xb1c00105
+ .long 0xb2000105,0xb2400105,0xb2800105,0xb2c00105,0xb3000105,0xb3400105,0xb3800105,0xb3c00105
+ .long 0xb4000105,0xb4400105,0xb4800105,0xb4c00105,0xb5000105,0xb5400105,0xb5800105,0xb5c00105
+ .long 0xb6000105,0xb6400105,0xb6800105,0xb6c00105,0xb7000105,0xb7400105,0xb7800105,0xb7c00105
+ .long 0xb8000105,0xb8400105,0xb8800105,0xb8c00105,0xb9000105,0xb9400105,0xb9800105,0xb9c00105
+ .long 0xba000105,0xba400105,0xba800105,0xbac00105,0xbb000105,0xbb400105,0xbb800105,0xbbc00105
+ .long 0xbc000105,0xbc400105,0xbc800105,0xbcc00105,0xbd000105,0xbd400105,0xbd800105,0xbdc00105
+ .long 0xbe000105,0xbe400105,0xbe800105,0xbec00105,0xbf000105,0xbf400105,0xbf800105,0xbfc00105
+ .long 0xc0000105,0xc0400105,0xc0800105,0xc0c00105,0xc1000105,0xc1400105,0xc1800105,0xc1c00105
+ .long 0xc2000105,0xc2400105,0xc2800105,0xc2c00105,0xc3000105,0xc3400105,0xc3800105,0xc3c00105
+ .long 0xc4000105,0xc4400105,0xc4800105,0xc4c00105,0xc5000105,0xc5400105,0xc5800105,0xc5c00105
+ .long 0xc6000105,0xc6400105,0xc6800105,0xc6c00105,0xc7000105,0xc7400105,0xc7800105,0xc7c00105
+ .long 0xc8000105,0xc8400105,0xc8800105,0xc8c00105,0xc9000105,0xc9400105,0xc9800105,0xc9c00105
+ .long 0xca000105,0xca400105,0xca800105,0xcac00105,0xcb000105,0xcb400105,0xcb800105,0xcbc00105
+ .long 0xcc000105,0xcc400105,0xcc800105,0xccc00105,0xcd000105,0xcd400105,0xcd800105,0xcdc00105
+ .long 0xce000105,0xce400105,0xce800105,0xcec00105,0xcf000105,0xcf400105,0xcf800105,0xcfc00105
+ .long 0xd0000105,0xd0400105,0xd0800105,0xd0c00105,0xd1000105,0xd1400105,0xd1800105,0xd1c00105
+ .long 0xd2000105,0xd2400105,0xd2800105,0xd2c00105,0xd3000105,0xd3400105,0xd3800105,0xd3c00105
+ .long 0xd4000105,0xd4400105,0xd4800105,0xd4c00105,0xd5000105,0xd5400105,0xd5800105,0xd5c00105
+ .long 0xd6000105,0xd6400105,0xd6800105,0xd6c00105,0xd7000105,0xd7400105,0xd7800105,0xd7c00105
+ .long 0xd8000105,0xd8400105,0xd8800105,0xd8c00105,0xd9000105,0xd9400105,0xd9800105,0xd9c00105
+ .long 0xda000105,0xda400105,0xda800105,0xdac00105,0xdb000105,0xdb400105,0xdb800105,0xdbc00105
+ .long 0xdc000105,0xdc400105,0xdc800105,0xdcc00105,0xdd000105,0xdd400105,0xdd800105,0xddc00105
+ .long 0xde000105,0xde400105,0xde800105,0xdec00105,0xdf000105,0xdf400105,0xdf800105,0xdfc00105
+ .long 0xe0000105,0xe0400105,0xe0800105,0xe0c00105,0xe1000105,0xe1400105,0xe1800105,0xe1c00105
+ .long 0xe2000105,0xe2400105,0xe2800105,0xe2c00105,0xe3000105,0xe3400105,0xe3800105,0xe3c00105
+ .long 0xe4000105,0xe4400105,0xe4800105,0xe4c00105,0xe5000105,0xe5400105,0xe5800105,0xe5c00105
+ .long 0xe6000105,0xe6400105,0xe6800105,0xe6c00105,0xe7000105,0xe7400105,0xe7800105,0xe7c00105
+ .long 0xe8000105,0xe8400105,0xe8800105,0xe8c00105,0xe9000105,0xe9400105,0xe9800105,0xe9c00105
+ .long 0xea000105,0xea400105,0xea800105,0xeac00105,0xeb000105,0xeb400105,0xeb800105,0xebc00105
+ .long 0xec000105,0xec400105,0xec800105,0xecc00105,0xed000105,0xed400105,0xed800105,0xedc00105
+ .long 0xee000105,0xee400105,0xee800105,0xeec00105,0xef000105,0xef400105,0xef800105,0xefc00105
+ .long 0xf0000105,0xf0400105,0xf0800105,0xf0c00105,0xf1000105,0xf1400105,0xf1800105,0xf1c00105
+ .long 0xf2000105,0xf2400105,0xf2800105,0xf2c00105,0xf3000105,0xf3400105,0xf3800105,0xf3c00105
+ .long 0xf4000105,0xf4400105,0xf4800105,0xf4c00105,0xf5000105,0xf5400105,0xf5800105,0xf5c00105
+ .long 0xf6000105,0xf6400105,0xf6800105,0xf6c00105,0xf7000105,0xf7400105,0xf7800105,0xf7c00105
+ .long 0xf8000105,0xf8400105,0xf8800105,0xf8c00105,0xf9000105,0xf9400105,0xf9800105,0xf9c00105
+ .long 0xfa000105,0xfa400105,0xfa800105,0xfac00105,0xfb000105,0xfb400105,0xfb800105,0xfbc00105
+ .long 0xfc000105,0xfc400105,0xfc800105,0xfcc00105,0xfd000105,0xfd400105,0xfd800105,0xfdc00105
+ .long 0xfe000105,0xfe400105,0xfe800105,0xfec00105,0xff000105,0xff400105,0xff800105,0xffc00105
the following patch was just integrated into master:
commit cdc2a881dcf78057ed416cc3fb581b506c22b6ab
Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
Date: Thu Feb 20 20:06:42 2014 +1100
utils/romcc.c: Fix spurious unsigned integer comparisons.
Clang warns about comparisons of unsigned integers with being below
zero. Remove spurious logic checks that are always false.
Change-Id: I70c4d5331df81e48bf7ef27ff98400c4218f7edc
Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com>
See http://review.coreboot.org/5275 for details.
-gerrit
the following patch was just integrated into master:
commit 63cf2cdc4abe5224536bc2b07014ac780b7007fa
Author: Patrick Georgi <patrick(a)georgi-clan.de>
Date: Sat Jan 18 18:28:58 2014 +0100
qemu-i440fx: add a prototype for main()
This probably belongs elsewhere, but I haven't found a nice place yet.
Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
See http://review.coreboot.org/4720 for details.
-gerrit