coreboot-gerrit March 2014

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Patch set updated for coreboot: 28fffe2 console: Refactor uart8250/NE2K
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5330 -gerrit commit 28fffe2d77e783bf69f024b1e7c2e09bfe1ef2fa Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 11:34:38 2014 +0200 console: Refactor uart8250/NE2K Do this for symmetry with romstage_console.c. Change-Id: If17acfc3da07b1dbefa87162c3c7168deb7b354a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 35 ++++++++++++++++------------------- src/arch/x86/lib/romstage_console.c | 2 +- src/include/console/ne2k.h | 4 ++++ 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 7d2fa5c..43de28b 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -41,6 +41,16 @@ static void __console_tx_byte(unsigned char byte) #endif } +static void __console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL + uart_tx_flush(); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} + static void __console_tx_nibble(unsigned nibble) { unsigned char digit; @@ -54,13 +64,8 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_show(loglevel)) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + __console_tx_byte(byte); + __console_tx_flush(); } } @@ -69,10 +74,8 @@ static void __console_tx_hex8(int loglevel, unsigned char value) if (console_show(loglevel)) { __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_hex16(int loglevel, unsigned short value) @@ -82,10 +85,8 @@ static void __console_tx_hex16(int loglevel, unsigned short value) __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_hex32(int loglevel, unsigned int value) @@ -99,10 +100,8 @@ static void __console_tx_hex32(int loglevel, unsigned int value) __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_string(int loglevel, const char *str) @@ -114,9 +113,7 @@ static void __console_tx_string(int loglevel, const char *str) __console_tx_byte('\r'); __console_tx_byte(ch); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + __console_tx_flush(); } } diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 4971f01..58742a2 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -33,7 +33,7 @@ void console_tx_byte(unsigned char byte) usb_tx_byte(0, byte); #endif #if CONFIG_CONSOLE_NE2K - ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); #endif #if CONFIG_CONSOLE_CBMEM && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) cbmemc_tx_byte(byte); diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 62424f1..cb3c1ec 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -22,4 +22,8 @@ void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); + +#ifndef __ROMCC__ +#define ne2k_append_data_byte(d, base) ne2k_append_data(&d, 1, base) +#endif #endif /* _NE2K_H */

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Patch set updated for coreboot: 5c28731 console: Move newline translation outside console_tx_byte
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5336 -gerrit commit 5c28731cba627c0aadd610d7d50e3827e902db95 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 19:03:57 2014 +0200 console: Move newline translation outside console_tx_byte This gives us completely transparent low-level function to transmit data. Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 3 --- src/arch/x86/lib/romstage_console.c | 3 --- src/console/console.c | 9 +-------- src/console/printk.c | 12 ++++++++++-- src/cpu/x86/smm/smiutil.c | 3 --- src/include/console/console.h | 15 ++++++++------- src/northbridge/intel/haswell/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/soc/intel/baytrail/romstage/raminit.c | 2 +- 9 files changed, 22 insertions(+), 29 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index a85f554..599cbc7 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -24,9 +24,6 @@ /* FIXME: need to make console driver more generic */ void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index c80cf8c..4971f01 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,9 +26,6 @@ void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/console/console.c b/src/console/console.c index 1712877..d5aadf6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -48,7 +48,7 @@ void console_tx_flush(void) } } -static void __console_tx_byte(unsigned char byte) +void console_tx_byte(unsigned char byte) { struct console_driver *driver; for(driver = console_drivers; driver < econsole_drivers; driver++) { @@ -56,13 +56,6 @@ static void __console_tx_byte(unsigned char byte) } } -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - __console_tx_byte('\r'); - __console_tx_byte(byte); -} - unsigned char console_rx_byte(void) { struct console_driver *driver; diff --git a/src/console/printk.c b/src/console/printk.c index 5275050..44f8c3d 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -13,6 +13,13 @@ DECLARE_SPIN_LOCK(console_lock) +void do_putchar(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + console_tx_byte(byte); +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -30,7 +37,7 @@ int do_printk(int msg_level, const char *fmt, ...) spin_lock(&console_lock); va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); + i = vtxprintf(do_putchar, fmt, args); va_end(args); console_tx_flush(); @@ -44,7 +51,8 @@ int do_printk(int msg_level, const char *fmt, ...) #if CONFIG_CHROMEOS void do_vtxprintf(const char *fmt, va_list args) { - vtxprintf(console_tx_byte, fmt, args); + vtxprintf(do_putchar, fmt, args); console_tx_flush(); } #endif + diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 6e9822e..644cab7 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -29,9 +29,6 @@ void console_tx_flush(void) void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index ee7f885..0dbec42 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -62,25 +62,26 @@ void post_log_clear(void); /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #if defined(__BOOT_BLOCK__) && !CONFIG_BOOTBLOCK_CONSOLE || \ defined(__SMM__) && !CONFIG_DEBUG_SMI || \ (defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__)) && !CONFIG_EARLY_CONSOLE -static inline void printk(int LEVEL, const char *fmt, ...); -static inline void printk(int LEVEL, const char *fmt, ...) { - /* Do nothing. */ -} +/* Do nothing. */ +static inline void printk(int LEVEL, const char *fmt, ...) {} +static inline void do_putchar(unsigned char byte) {} -#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#else + +int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +void do_putchar(unsigned char byte); #define printk(LEVEL, fmt, args...) \ do { \ do_printk(LEVEL, fmt, ##args); \ } while(0) -#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#endif #if CONFIG_CHROMEOS /* FIXME: Collision of varargs with AMD headers without guard. */ diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 316f7fd..1e020f9 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -166,7 +166,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* Pass console handler in pei_data */ - pei_data->tx_byte = console_tx_byte; + pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ entry = (unsigned long)cbfs_get_file_content( diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index bfb4033..61e1545 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -248,7 +248,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* Pass console handler in pei_data */ - pei_data->tx_byte = console_tx_byte; + pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ /* TODO make MRC blob (0xab?) defined in cbfs_core.h. */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 7bcd54f..98d389e 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -55,7 +55,7 @@ static void enable_smbus(void) static void ABI_X86 send_to_console(unsigned char b) { - console_tx_byte(b); + do_putchar(b); } static void print_dram_info(void)

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Patch set updated for coreboot: 105115d console: Simplify vtxprintf
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5334 -gerrit commit 105115d47878bb5a578a2c66e8a7b5f636193327 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 14:28:17 2014 +0200 console: Simplify vtxprintf We do not need ROMCC support here and using wrappers for console_tx_byte we can simplify this code. Change-Id: I7f3b5acdfd0bde1d832b16418339dd5e232627e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 10 ++++++++-- src/console/vsprintf.c | 2 +- src/console/vtxprintf.c | 42 ++++++++--------------------------------- src/include/console/console.h | 1 + src/include/console/vtxprintf.h | 7 ++----- 5 files changed, 20 insertions(+), 42 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index 44f8c3d..4fc66ab 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -5,6 +5,7 @@ * */ +#include <stddef.h> #include <smp/node.h> #include <smp/spinlock.h> #include <console/vtxprintf.h> @@ -20,6 +21,11 @@ void do_putchar(unsigned char byte) console_tx_byte(byte); } +void wrap_putchar(unsigned char byte, void *data) +{ + do_putchar(byte); +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -37,7 +43,7 @@ int do_printk(int msg_level, const char *fmt, ...) spin_lock(&console_lock); va_start(args, fmt); - i = vtxprintf(do_putchar, fmt, args); + i = vtxprintf(wrap_putchar, fmt, args, NULL); va_end(args); console_tx_flush(); @@ -51,7 +57,7 @@ int do_printk(int msg_level, const char *fmt, ...) #if CONFIG_CHROMEOS void do_vtxprintf(const char *fmt, va_list args) { - vtxprintf(do_putchar, fmt, args); + vtxprintf(wrap_putchar, fmt, args, NULL); console_tx_flush(); } #endif diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 1fb834f..fd6646b 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -48,7 +48,7 @@ static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) ctx.str_buf = buf; ctx.buf_limit = size ? size - 1 : 0; - i = vtxdprintf(str_tx_byte, fmt, args, &ctx); + i = vtxprintf(str_tx_byte, fmt, args, &ctx); if (size) *ctx.str_buf = '\0'; diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 502d53e..d4d70b6 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -8,15 +8,7 @@ #include <console/console.h> #include <console/vtxprintf.h> -#if !defined (__ROMCC__) && !defined(__SMM__) -#define DATA_ARG , data -#define DATA_ARG_DECL , void *data -#else -#define DATA_ARG -#define DATA_ARG_DECL -#endif - -#define call_tx(x) tx_byte(x DATA_ARG) +#define call_tx(x) tx_byte(x, data) /* haha, don't need ctype.c */ #define isdigit(c) ((c) >= '0' && (c) <= '9') @@ -40,9 +32,9 @@ static int skip_atoi(const char **s) #define SPECIAL 32 /* 0x */ #define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ -static int number(void (*tx_byte)(unsigned char byte DATA_ARG_DECL), - unsigned long long num, int base, int size, int precision, int type - DATA_ARG_DECL) +static int number(void (*tx_byte)(unsigned char byte, void *data), + unsigned long long num, int base, int size, int precision, int type, + void *data) { char c,sign,tmp[66]; const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; @@ -112,12 +104,8 @@ static int number(void (*tx_byte)(unsigned char byte DATA_ARG_DECL), } -#if !defined (__ROMCC__) && !defined(__SMM__) -int vtxdprintf(void (*tx_byte)(unsigned char byte, void *data), +int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data) -#else -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) -#endif { int len; unsigned long long num; @@ -135,7 +123,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args #if defined(__SMM__) && CONFIG_SMM_TSEG /* Fix pointer in TSEG */ - tx_byte = console_tx_byte; + tx_byte = wrap_putchar; #endif for (count=0; *fmt ; ++fmt) { @@ -236,7 +224,7 @@ repeat: } count += number(tx_byte, (unsigned long) va_arg(args, void *), 16, - field_width, precision, flags DATA_ARG); + field_width, precision, flags, data); continue; case 'n': @@ -300,21 +288,7 @@ repeat: } else { num = va_arg(args, unsigned int); } - count += number(tx_byte, num, base, field_width, precision, flags DATA_ARG); + count += number(tx_byte, num, base, field_width, precision, flags, data); } return count; } - - -#if !defined (__ROMCC__) && !defined(__SMM__) -static void wrap_tx_byte (unsigned char byte, void *data) -{ - void (*tx_byte)(unsigned char byte) = data; - tx_byte (byte); -} - -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) -{ - return vtxdprintf(wrap_tx_byte, fmt, args, tx_byte); -} -#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 0dbec42..ad605d0 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -75,6 +75,7 @@ static inline void do_putchar(unsigned char byte) {} int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); +void wrap_putchar(unsigned char byte, void *data); #define printk(LEVEL, fmt, args...) \ do { \ diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index c5daf9d..3f0c63e 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -34,10 +34,7 @@ typedef __builtin_va_list va_list; #include <stdarg.h> #endif -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args); - -#if !defined (__ROMCC__) && !defined (__SMM__) -int vtxdprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data); -#endif +int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), + const char *fmt, va_list args, void *data); #endif

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Patch set updated for coreboot: f7b8cee console: Remove old fix for DEBUG_SMI
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5335 -gerrit commit f7b8cee7a33396c2c6c054639a710ee9c5148caf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 19:50:07 2014 +0200 console: Remove old fix for DEBUG_SMI No longer needed as wrap_putchar() survives SMM relocation to TSEG. Change-Id: I6143844b0b9902ef63baf3e5781a5dc4f54234be Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 3 +-- src/console/vtxprintf.c | 5 ----- src/include/console/console.h | 1 - 3 files changed, 1 insertion(+), 8 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index 4fc66ab..f96442a 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -21,7 +21,7 @@ void do_putchar(unsigned char byte) console_tx_byte(byte); } -void wrap_putchar(unsigned char byte, void *data) +static void wrap_putchar(unsigned char byte, void *data) { do_putchar(byte); } @@ -61,4 +61,3 @@ void do_vtxprintf(const char *fmt, va_list args) console_tx_flush(); } #endif - diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index d4d70b6..23db037 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -121,11 +121,6 @@ int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), int count; -#if defined(__SMM__) && CONFIG_SMM_TSEG - /* Fix pointer in TSEG */ - tx_byte = wrap_putchar; -#endif - for (count=0; *fmt ; ++fmt) { if (*fmt != '%') { call_tx(*fmt), count++; diff --git a/src/include/console/console.h b/src/include/console/console.h index ad605d0..0dbec42 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -75,7 +75,6 @@ static inline void do_putchar(unsigned char byte) {} int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); -void wrap_putchar(unsigned char byte, void *data); #define printk(LEVEL, fmt, args...) \ do { \

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Patch set updated for coreboot: 15cbffd console: Add printk helper for ChromeOS
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5347 -gerrit commit 15cbffd5f7e4fde4649c47f548325ddb7a33965e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 6 16:55:05 2014 +0200 console: Add printk helper for ChromeOS Do not expose console_tx_flush() to ChromeOS as that function is part of lower-level implementation. Change-Id: I1e31662da88a60e83f8e5d307a4b53441c130aab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 8 ++++++++ src/include/console/console.h | 10 ++++++++++ src/vendorcode/google/chromeos/vboot_loader.c | 3 +-- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index a3b91ad..5275050 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -40,3 +40,11 @@ int do_printk(int msg_level, const char *fmt, ...) return i; } + +#if CONFIG_CHROMEOS +void do_vtxprintf(const char *fmt, va_list args) +{ + vtxprintf(console_tx_byte, fmt, args); + console_tx_flush(); +} +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index f4b3c46..ee7f885 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -82,6 +82,16 @@ static inline void printk(int LEVEL, const char *fmt, ...) { #endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#if CONFIG_CHROMEOS +/* FIXME: Collision of varargs with AMD headers without guard. */ +#include <console/vtxprintf.h> +#if !defined(__PRE_RAM__) || CONFIG_EARLY_CONSOLE +void do_vtxprintf(const char *fmt, va_list args); +#else +static inline void do_vtxprintf(const char *fmt, va_list args) {}; +#endif +#endif + #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) #define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 0c5220a..943ad17 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -64,8 +64,7 @@ out: /* Helper routines for the vboot stub. */ static void log_msg(const char *fmt, va_list args) { - vtxprintf(console_tx_byte, fmt, args); - console_tx_flush(); + do_vtxprintf(fmt, args); } static void fatal_error(void)

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Patch set updated for coreboot: 54ba627 console: Add printk helper for ChromeOS
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5347 -gerrit commit 54ba627fec203d31b3dfeea43ca9146fa8195469 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 6 16:55:05 2014 +0200 console: Add printk helper for ChromeOS Do not expose console_tx_flush() to ChromeOS as that function is part of lower-level implementation. Change-Id: I1e31662da88a60e83f8e5d307a4b53441c130aab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 8 ++++++++ src/include/console/console.h | 10 ++++++++++ src/vendorcode/google/chromeos/vboot_loader.c | 3 +-- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index a3b91ad..f60af61 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -40,3 +40,11 @@ int do_printk(int msg_level, const char *fmt, ...) return i; } + +#if CONFIG_CHROMEOS +void do_vtxprintf(const char *fmt, va_list args) +{ + vtxprintf(console_tx_byte, fmt, args, NULL); + console_tx_flush(); +} +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index f4b3c46..ee7f885 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -82,6 +82,16 @@ static inline void printk(int LEVEL, const char *fmt, ...) { #endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#if CONFIG_CHROMEOS +/* FIXME: Collision of varargs with AMD headers without guard. */ +#include <console/vtxprintf.h> +#if !defined(__PRE_RAM__) || CONFIG_EARLY_CONSOLE +void do_vtxprintf(const char *fmt, va_list args); +#else +static inline void do_vtxprintf(const char *fmt, va_list args) {}; +#endif +#endif + #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) #define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 0c5220a..943ad17 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -64,8 +64,7 @@ out: /* Helper routines for the vboot stub. */ static void log_msg(const char *fmt, va_list args) { - vtxprintf(console_tx_byte, fmt, args); - console_tx_flush(); + do_vtxprintf(fmt, args); } static void fatal_error(void)

1 0

Patch set updated for coreboot: c01e5a6 src/vendorcode/amd: correct spelling of MTRR
by Paul Menzel 06 Mar '14

06 Mar '14

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4806 -gerrit commit c01e5a62fa96883490b4fff22ec8a843d2fcf08c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jan 25 15:59:31 2014 +0100 src/vendorcode/amd: correct spelling of MTRR Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c | 4 ++-- src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c | 12 ++++++------ src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm | 2 +- src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c | 2 +- src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f10/cpcarmac.inc | 6 +++--- src/vendorcode/amd/agesa/f10/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c | 6 +++--- src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c | 2 +- src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f12/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f12/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c | 6 +++--- src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f14/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f14/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c | 6 +++--- src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f15/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f15/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c | 6 +++--- .../amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f15tn/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f16kb/Include/Filecode.h | 4 ++-- src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c | 6 +++--- .../amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c | 2 +- .../amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c | 2 +- .../amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c | 2 +- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 2 +- 40 files changed, 69 insertions(+), 69 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c index 1dbe440..3a3be35 100644 --- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c @@ -120,7 +120,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -151,7 +151,7 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c index 10f4f5c..87dda2a 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c @@ -208,7 +208,7 @@ AllocateExecutionCache ( GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader); - // Setup MTTRs for region 0 to region 2 + // Setup MTRRs for region 0 to region 2 VariableMttrBase = AMD_MTRR_VARIABLE_BASE6; for (i = 0; i < 3; i++) { // Exit if no more cache available @@ -265,7 +265,7 @@ AllocateExecutionCache ( if (StartAddr < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region if ((StartAddr + ExeCacheSize) > 0xFFFFF) { ExeCacheSize = 0xFFFFF - StartAddr; AgesaStatus = AGESA_WARNING; @@ -276,7 +276,7 @@ AllocateExecutionCache ( i, StartAddr, ExeCacheSize, 0, StdHeader); } - // Find start and end of MTTR + // Find start and end of MTRR StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7); @@ -290,14 +290,14 @@ AllocateExecutionCache ( } } - // Setup MTTRs + // Setup MTRRs MsrData = WP_IO; for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) { LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader); } } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) { AgesaStatus = AGESA_ERROR; AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB; @@ -373,7 +373,7 @@ AllocateExecutionCache ( } } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm index 0b796c8..e92c945 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm @@ -147,7 +147,7 @@ EFLoop: .endw .endif - ; restore variable MTTR6 and MTTR7 to default states + ; restore variable MTRR6 and MTRR7 to default states mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6 xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 xor edx, edx diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c index 2421bb9..789a6bd 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c @@ -156,7 +156,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); } - // restore variable MTTR6 and MTTR7 to default states + // restore variable MTRR6 and MTRR7 to default states for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared __writemsr (msrno, 0); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c index b5be972..aa79b16 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c @@ -153,7 +153,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/cpcarmac.inc b/src/vendorcode/amd/agesa/f10/cpcarmac.inc index f7119d1..e893d1e 100644 --- a/src/vendorcode/amd/agesa/f10/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f10/cpcarmac.inc @@ -187,7 +187,7 @@ SetupDramMap: inc cl .endw - ; setup MTTR for stacks + ; setup MTRR for stacks mov ebx, WB_DRAM_TYPE .if (di == 0) ;core 0 .if (si > 3) ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h @@ -198,7 +198,7 @@ SetupDramMap: or edx, ebx _WRMSR .else ;core 1 to core 7 start at 60000h - .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTTR + .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTRR shl ebx, 16 .if (si > 1) shl ebx, 8 @@ -207,7 +207,7 @@ SetupDramMap: _RDMSR or edx, ebx _WRMSR - .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTTR + .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTRR mov ecx, AMD_MTRR_FIX16k_80000 _RDMSR .if (si < 6) ; node 4 and node 5 diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 11f50db..62957e4 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -1353,7 +1353,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c index bf8e6d2..eac7c2a 100644 --- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c @@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c index fbc1b5e..d84e689 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c index 1bad891..57483a9 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c @@ -148,7 +148,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); } - // restore variable MTTR6 and MTTR7 to default states + // restore variable MTRR6 and MTRR7 to default states for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared __writemsr (msrno, 0); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c index dacaded..e9e41cb 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c @@ -188,7 +188,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f12/cpcarmac.inc b/src/vendorcode/amd/agesa/f12/cpcarmac.inc index b4add85..5bd41d0 100644 --- a/src/vendorcode/amd/agesa/f12/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f12/cpcarmac.inc @@ -220,7 +220,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index 22564cb..3b360a4 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1347,7 +1347,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c index bb23204..3e97fe6 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c @@ -140,7 +140,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -171,14 +171,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c index 6d06745..dbe4717 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c @@ -280,7 +280,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -298,7 +298,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -324,7 +324,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm index 3ffe146..de5201d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm @@ -173,7 +173,7 @@ EFLoop: .endw .endif - ; restore variable MTTR6 and MTTR7 to default states + ; restore variable MTRR6 and MTRR7 to default states mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6 xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 xor edx, edx diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S index 48ee5d0..137261c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -157,7 +157,7 @@ EFLoop: jmp 5b /* .endw */ 4: /* .endif */ - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ xor %edx, %edx diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c index f6b409f..0e4bce9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c @@ -192,7 +192,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/cpcarmac.inc b/src/vendorcode/amd/agesa/f14/cpcarmac.inc index b703b7f..54e7f95 100644 --- a/src/vendorcode/amd/agesa/f14/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f14/cpcarmac.inc @@ -215,7 +215,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 40e0e31..5088008 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1361,7 +1361,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c index b2accb2..3eb908e 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c @@ -138,7 +138,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -169,14 +169,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c index ca60b2b..274844b 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c @@ -282,7 +282,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -300,7 +300,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -326,7 +326,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S index 221805a..012c4f7 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S @@ -187,7 +187,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c index f42c35d..e1fc324 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c @@ -189,7 +189,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/cpcarmac.inc b/src/vendorcode/amd/agesa/f15/cpcarmac.inc index 24a6073..8947491 100644 --- a/src/vendorcode/amd/agesa/f15/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f15/cpcarmac.inc @@ -221,7 +221,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index c88709c..521851e 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -1368,7 +1368,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c index 7ed5f16..9f5243f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c @@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c index fcd7bf4..e9c8922 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S index 4ab535a..c1e7ab7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S @@ -187,7 +187,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c index 2e45471..fdf2581 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c @@ -188,7 +188,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc index 98c7696..19044bd 100644 --- a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc @@ -220,7 +220,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index d6dd49a..ba04027 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1677,7 +1677,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h index a3b3472..dcec443 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h @@ -575,7 +575,7 @@ #define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) #define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) #define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0XF58B) +#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c index 7f03e13..a795b2e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c @@ -141,7 +141,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -172,14 +172,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c index b5a38b8..d8243ad 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S index 97f6f16..5803c26 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S @@ -179,7 +179,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c index 42a6afa..3f3dbda 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c @@ -191,7 +191,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c index a568f9e..832e807 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c @@ -64,7 +64,7 @@ CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE +#define FILECODE PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c index 0fc13f9..08c7730 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c @@ -70,7 +70,7 @@ CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE +#define FILECODE PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 90c8cc6..357ad89 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1042,7 +1042,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction.

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Patch set updated for coreboot: 64e008c console: Add printk helper for ChromeOS
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5347 -gerrit commit 64e008c2ef4db92476e297c9e28facce087468e9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 6 16:55:05 2014 +0200 console: Add printk helper for ChromeOS Do not expose console_tx_flush() to ChromeOS as the function is details of lower-level implementation. Change-Id: I1e31662da88a60e83f8e5d307a4b53441c130aab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 8 ++++++++ src/include/console/console.h | 10 ++++++++++ src/vendorcode/google/chromeos/vboot_loader.c | 3 +-- 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index a3b91ad..f60af61 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -40,3 +40,11 @@ int do_printk(int msg_level, const char *fmt, ...) return i; } + +#if CONFIG_CHROMEOS +void do_vtxprintf(const char *fmt, va_list args) +{ + vtxprintf(console_tx_byte, fmt, args, NULL); + console_tx_flush(); +} +#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index f4b3c46..ee7f885 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -82,6 +82,16 @@ static inline void printk(int LEVEL, const char *fmt, ...) { #endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#if CONFIG_CHROMEOS +/* FIXME: Collision of varargs with AMD headers without guard. */ +#include <console/vtxprintf.h> +#if !defined(__PRE_RAM__) || CONFIG_EARLY_CONSOLE +void do_vtxprintf(const char *fmt, va_list args); +#else +static inline void do_vtxprintf(const char *fmt, va_list args) {}; +#endif +#endif + #define print_emerg(STR) printk(BIOS_EMERG, "%s", (STR)) #define print_alert(STR) printk(BIOS_ALERT, "%s", (STR)) #define print_crit(STR) printk(BIOS_CRIT, "%s", (STR)) diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 0c5220a..943ad17 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -64,8 +64,7 @@ out: /* Helper routines for the vboot stub. */ static void log_msg(const char *fmt, va_list args) { - vtxprintf(console_tx_byte, fmt, args); - console_tx_flush(); + do_vtxprintf(fmt, args); } static void fatal_error(void)

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Patch set updated for coreboot: aef9a6f console: Move newline translation outside console_tx_byte
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5336 -gerrit commit aef9a6f3013f11a66e28c1d064f1e735322a0340 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 19:03:57 2014 +0200 console: Move newline translation outside console_tx_byte This gives us completely transparent low-level function to transmit data. Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 3 --- src/arch/x86/lib/romstage_console.c | 3 --- src/console/console.c | 9 +-------- src/console/printk.c | 12 ++++++++++-- src/cpu/x86/smm/smiutil.c | 3 --- src/include/console/console.h | 15 ++++++++------- src/northbridge/intel/haswell/raminit.c | 2 +- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/soc/intel/baytrail/romstage/raminit.c | 2 +- 9 files changed, 22 insertions(+), 29 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index a85f554..599cbc7 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -24,9 +24,6 @@ /* FIXME: need to make console driver more generic */ void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index c80cf8c..4971f01 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -26,9 +26,6 @@ void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/console/console.c b/src/console/console.c index 1712877..d5aadf6 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -48,7 +48,7 @@ void console_tx_flush(void) } } -static void __console_tx_byte(unsigned char byte) +void console_tx_byte(unsigned char byte) { struct console_driver *driver; for(driver = console_drivers; driver < econsole_drivers; driver++) { @@ -56,13 +56,6 @@ static void __console_tx_byte(unsigned char byte) } } -void console_tx_byte(unsigned char byte) -{ - if (byte == '\n') - __console_tx_byte('\r'); - __console_tx_byte(byte); -} - unsigned char console_rx_byte(void) { struct console_driver *driver; diff --git a/src/console/printk.c b/src/console/printk.c index f60af61..c7c6117 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -13,6 +13,13 @@ DECLARE_SPIN_LOCK(console_lock) +void do_putchar(unsigned char byte) +{ + if (byte == '\n') + console_tx_byte('\r'); + console_tx_byte(byte); +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -30,7 +37,7 @@ int do_printk(int msg_level, const char *fmt, ...) spin_lock(&console_lock); va_start(args, fmt); - i = vtxprintf(console_tx_byte, fmt, args); + i = vtxprintf(do_putchar, fmt, args); va_end(args); console_tx_flush(); @@ -44,7 +51,8 @@ int do_printk(int msg_level, const char *fmt, ...) #if CONFIG_CHROMEOS void do_vtxprintf(const char *fmt, va_list args) { - vtxprintf(console_tx_byte, fmt, args, NULL); + vtxprintf(do_putchar, fmt, args, NULL); console_tx_flush(); } #endif + diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 6e9822e..644cab7 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -29,9 +29,6 @@ void console_tx_flush(void) void console_tx_byte(unsigned char byte) { - if (byte == '\n') - console_tx_byte('\r'); - #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif diff --git a/src/include/console/console.h b/src/include/console/console.h index ee7f885..0dbec42 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -62,25 +62,26 @@ void post_log_clear(void); /* this function is weak and can be overridden by a mainboard function. */ void mainboard_post(u8 value); void __attribute__ ((noreturn)) die(const char *msg); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #if defined(__BOOT_BLOCK__) && !CONFIG_BOOTBLOCK_CONSOLE || \ defined(__SMM__) && !CONFIG_DEBUG_SMI || \ (defined(__PRE_RAM__) && !defined(__BOOT_BLOCK__)) && !CONFIG_EARLY_CONSOLE -static inline void printk(int LEVEL, const char *fmt, ...); -static inline void printk(int LEVEL, const char *fmt, ...) { - /* Do nothing. */ -} +/* Do nothing. */ +static inline void printk(int LEVEL, const char *fmt, ...) {} +static inline void do_putchar(unsigned char byte) {} -#else /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#else + +int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); +void do_putchar(unsigned char byte); #define printk(LEVEL, fmt, args...) \ do { \ do_printk(LEVEL, fmt, ##args); \ } while(0) -#endif /* defined(__PRE_RAM__) && !CONFIG_EARLY_CONSOLE */ +#endif #if CONFIG_CHROMEOS /* FIXME: Collision of varargs with AMD headers without guard. */ diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 316f7fd..1e020f9 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -166,7 +166,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* Pass console handler in pei_data */ - pei_data->tx_byte = console_tx_byte; + pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ entry = (unsigned long)cbfs_get_file_content( diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index bfb4033..61e1545 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -248,7 +248,7 @@ void sdram_initialize(struct pei_data *pei_data) } /* Pass console handler in pei_data */ - pei_data->tx_byte = console_tx_byte; + pei_data->tx_byte = do_putchar; /* Locate and call UEFI System Agent binary. */ /* TODO make MRC blob (0xab?) defined in cbfs_core.h. */ diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 7bcd54f..98d389e 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -55,7 +55,7 @@ static void enable_smbus(void) static void ABI_X86 send_to_console(unsigned char b) { - console_tx_byte(b); + do_putchar(b); } static void print_dram_info(void)

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Patch set updated for coreboot: 88ab681 console: Simplify vtxprintf
by Kyösti Mälkki 06 Mar '14

06 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5334 -gerrit commit 88ab68192bfd3786d4cefb97b5fae05e754ca9e3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 4 14:28:17 2014 +0200 console: Simplify vtxprintf We do not need ROMCC support here and using wrappers for console_tx_byte we can simplify this code. Change-Id: I7f3b5acdfd0bde1d832b16418339dd5e232627e7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/printk.c | 10 ++++++++-- src/console/vsprintf.c | 2 +- src/console/vtxprintf.c | 42 ++++++++--------------------------------- src/include/console/console.h | 1 + src/include/console/vtxprintf.h | 7 ++----- 5 files changed, 20 insertions(+), 42 deletions(-) diff --git a/src/console/printk.c b/src/console/printk.c index c7c6117..4fc66ab 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -5,6 +5,7 @@ * */ +#include <stddef.h> #include <smp/node.h> #include <smp/spinlock.h> #include <console/vtxprintf.h> @@ -20,6 +21,11 @@ void do_putchar(unsigned char byte) console_tx_byte(byte); } +void wrap_putchar(unsigned char byte, void *data) +{ + do_putchar(byte); +} + int do_printk(int msg_level, const char *fmt, ...) { va_list args; @@ -37,7 +43,7 @@ int do_printk(int msg_level, const char *fmt, ...) spin_lock(&console_lock); va_start(args, fmt); - i = vtxprintf(do_putchar, fmt, args); + i = vtxprintf(wrap_putchar, fmt, args, NULL); va_end(args); console_tx_flush(); @@ -51,7 +57,7 @@ int do_printk(int msg_level, const char *fmt, ...) #if CONFIG_CHROMEOS void do_vtxprintf(const char *fmt, va_list args) { - vtxprintf(do_putchar, fmt, args, NULL); + vtxprintf(wrap_putchar, fmt, args, NULL); console_tx_flush(); } #endif diff --git a/src/console/vsprintf.c b/src/console/vsprintf.c index 1fb834f..fd6646b 100644 --- a/src/console/vsprintf.c +++ b/src/console/vsprintf.c @@ -48,7 +48,7 @@ static int vsnprintf(char *buf, size_t size, const char *fmt, va_list args) ctx.str_buf = buf; ctx.buf_limit = size ? size - 1 : 0; - i = vtxdprintf(str_tx_byte, fmt, args, &ctx); + i = vtxprintf(str_tx_byte, fmt, args, &ctx); if (size) *ctx.str_buf = '\0'; diff --git a/src/console/vtxprintf.c b/src/console/vtxprintf.c index 502d53e..d4d70b6 100644 --- a/src/console/vtxprintf.c +++ b/src/console/vtxprintf.c @@ -8,15 +8,7 @@ #include <console/console.h> #include <console/vtxprintf.h> -#if !defined (__ROMCC__) && !defined(__SMM__) -#define DATA_ARG , data -#define DATA_ARG_DECL , void *data -#else -#define DATA_ARG -#define DATA_ARG_DECL -#endif - -#define call_tx(x) tx_byte(x DATA_ARG) +#define call_tx(x) tx_byte(x, data) /* haha, don't need ctype.c */ #define isdigit(c) ((c) >= '0' && (c) <= '9') @@ -40,9 +32,9 @@ static int skip_atoi(const char **s) #define SPECIAL 32 /* 0x */ #define LARGE 64 /* use 'ABCDEF' instead of 'abcdef' */ -static int number(void (*tx_byte)(unsigned char byte DATA_ARG_DECL), - unsigned long long num, int base, int size, int precision, int type - DATA_ARG_DECL) +static int number(void (*tx_byte)(unsigned char byte, void *data), + unsigned long long num, int base, int size, int precision, int type, + void *data) { char c,sign,tmp[66]; const char *digits="0123456789abcdefghijklmnopqrstuvwxyz"; @@ -112,12 +104,8 @@ static int number(void (*tx_byte)(unsigned char byte DATA_ARG_DECL), } -#if !defined (__ROMCC__) && !defined(__SMM__) -int vtxdprintf(void (*tx_byte)(unsigned char byte, void *data), +int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data) -#else -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) -#endif { int len; unsigned long long num; @@ -135,7 +123,7 @@ int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args #if defined(__SMM__) && CONFIG_SMM_TSEG /* Fix pointer in TSEG */ - tx_byte = console_tx_byte; + tx_byte = wrap_putchar; #endif for (count=0; *fmt ; ++fmt) { @@ -236,7 +224,7 @@ repeat: } count += number(tx_byte, (unsigned long) va_arg(args, void *), 16, - field_width, precision, flags DATA_ARG); + field_width, precision, flags, data); continue; case 'n': @@ -300,21 +288,7 @@ repeat: } else { num = va_arg(args, unsigned int); } - count += number(tx_byte, num, base, field_width, precision, flags DATA_ARG); + count += number(tx_byte, num, base, field_width, precision, flags, data); } return count; } - - -#if !defined (__ROMCC__) && !defined(__SMM__) -static void wrap_tx_byte (unsigned char byte, void *data) -{ - void (*tx_byte)(unsigned char byte) = data; - tx_byte (byte); -} - -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args) -{ - return vtxdprintf(wrap_tx_byte, fmt, args, tx_byte); -} -#endif diff --git a/src/include/console/console.h b/src/include/console/console.h index 0dbec42..ad605d0 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -75,6 +75,7 @@ static inline void do_putchar(unsigned char byte) {} int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); void do_putchar(unsigned char byte); +void wrap_putchar(unsigned char byte, void *data); #define printk(LEVEL, fmt, args...) \ do { \ diff --git a/src/include/console/vtxprintf.h b/src/include/console/vtxprintf.h index c5daf9d..3f0c63e 100644 --- a/src/include/console/vtxprintf.h +++ b/src/include/console/vtxprintf.h @@ -34,10 +34,7 @@ typedef __builtin_va_list va_list; #include <stdarg.h> #endif -int vtxprintf(void (*tx_byte)(unsigned char byte), const char *fmt, va_list args); - -#if !defined (__ROMCC__) && !defined (__SMM__) -int vtxdprintf(void (*tx_byte)(unsigned char byte, void *data), const char *fmt, va_list args, void *data); -#endif +int vtxprintf(void (*tx_byte)(unsigned char byte, void *data), + const char *fmt, va_list args, void *data); #endif

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coreboot-gerrit March 2014