coreboot-gerrit March 2014

coreboot-gerrit@coreboot.org

1 participants
584 discussions

Patch set updated for coreboot: 0685198 console: Hide global console_loglevel
by Kyösti Mälkki 05 Mar '14

05 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5333 -gerrit commit 06851980f85024341f6a562fe16fe893f1832aa5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 28 14:37:27 2014 +0200 console: Hide global console_loglevel Change-Id: I7bdc468bc3f74516abb2c583bdb5b6d7555d987c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 21 +++++++-------------- src/console/init.c | 10 ++++++++++ src/console/printk.c | 6 +----- src/include/console/console.h | 10 +--------- 4 files changed, 19 insertions(+), 28 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 3f8f62f..7d2fa5c 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -17,18 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <stdint.h> -#include <console/loglevel.h> -#include <console/post_codes.h> #include <console/uart.h> #include <console/ne2k.h> -/* __PRE_RAM__ */ -/* Using a global varible can cause problems when we reset the stack - * from cache as ram to ram. If we make this a define USE_SHARED_STACK - * we could use the same code on all architectures. - */ -#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL +/* While in romstage, console loglevel is built-time constant. */ +#define console_show(msg_level) (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= msg_level) #if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" @@ -60,7 +53,7 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { - if (console_loglevel >= loglevel) { + if (console_show(loglevel)) { #if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif @@ -73,7 +66,7 @@ static void __console_tx_char(int loglevel, unsigned char byte) static void __console_tx_hex8(int loglevel, unsigned char value) { - if (console_loglevel >= loglevel) { + if (console_show(loglevel)) { __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); } @@ -84,7 +77,7 @@ static void __console_tx_hex8(int loglevel, unsigned char value) static void __console_tx_hex16(int loglevel, unsigned short value) { - if (console_loglevel >= loglevel) { + if (console_show(loglevel)) { __console_tx_nibble((value >> 12U) & 0x0fU); __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); @@ -97,7 +90,7 @@ static void __console_tx_hex16(int loglevel, unsigned short value) static void __console_tx_hex32(int loglevel, unsigned int value) { - if (console_loglevel >= loglevel) { + if (console_show(loglevel)) { __console_tx_nibble((value >> 28U) & 0x0fU); __console_tx_nibble((value >> 24U) & 0x0fU); __console_tx_nibble((value >> 20U) & 0x0fU); @@ -114,7 +107,7 @@ static void __console_tx_hex32(int loglevel, unsigned int value) static void __console_tx_string(int loglevel, const char *str) { - if (console_loglevel >= loglevel) { + if (console_show(loglevel)) { unsigned char ch; while((ch = *str++) != '\0') { if (ch == '\n') diff --git a/src/console/init.c b/src/console/init.c index 28934e7..d2a5121 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -29,6 +29,16 @@ #include <device/pci.h> #endif +#if !defined(__ROMCC__) +/* While in romstage, console loglevel is built-time constant. */ +static ROMSTAGE_CONST int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; + +int console_show(int msg_level) +{ + return (console_loglevel >= msg_level); +} +#endif + void console_init(void) { #if !defined(__PRE_RAM__) diff --git a/src/console/printk.c b/src/console/printk.c index 6c2e6e4..a3b91ad 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -11,9 +11,6 @@ #include <console/console.h> #include <trace.h> -int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -int default_console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; - DECLARE_SPIN_LOCK(console_lock) int do_printk(int msg_level, const char *fmt, ...) @@ -21,9 +18,8 @@ int do_printk(int msg_level, const char *fmt, ...) va_list args; int i; - if (msg_level > console_loglevel) { + if (!console_show(msg_level)) return 0; - } #if CONFIG_SQUELCH_EARLY_SMP && defined(__PRE_RAM__) if (!boot_cpu()) diff --git a/src/include/console/console.h b/src/include/console/console.h index 6d1b01a..f4b3c46 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -40,18 +40,10 @@ struct console_driver { /* Defined by the linker... */ extern struct console_driver console_drivers[]; extern struct console_driver econsole_drivers[]; - -extern int console_loglevel; -#else -/* __PRE_RAM__ */ -/* Using a global variable can cause problems when we reset the stack - * from cache as ram to ram. If we make this a define USE_SHARED_STACK - * we could use the same code on all architectures. - */ -#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL #endif #ifndef __ROMCC__ +int console_show(int msg_level); void console_init(void); void console_hw_init(void); void console_tx_byte(unsigned char byte);

1 0

Patch set updated for coreboot: 5ed866f src/vendorcode/amd: correct spelling of MTRR
by Idwer Vollering 05 Mar '14

05 Mar '14

Idwer Vollering (vidwer(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4806 -gerrit commit 5ed866f22fee5ea6ad5e270fdc20d2315cc85e0d Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sat Jan 25 15:59:31 2014 +0100 src/vendorcode/amd: correct spelling of MTRR Change-Id: I7576591b42fa62da2b3bd74f961fb297b85e250d Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c | 4 ++-- src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c | 12 ++++++------ src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm | 2 +- src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c | 2 +- src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f10/cpcarmac.inc | 6 +++--- src/vendorcode/amd/agesa/f10/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c | 6 +++--- src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c | 2 +- src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f12/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f12/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c | 6 +++--- src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f14/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f14/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c | 6 +++--- src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f15/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f15/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c | 6 +++--- .../amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c | 2 +- src/vendorcode/amd/agesa/f15tn/cpcarmac.inc | 2 +- src/vendorcode/amd/agesa/f15tn/gcccar.inc | 2 +- src/vendorcode/amd/agesa/f16kb/Include/Filecode.h | 4 ++-- src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c | 6 +++--- .../amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c | 6 +++--- src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S | 2 +- src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c | 2 +- .../amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c | 2 +- .../amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c | 2 +- src/vendorcode/amd/agesa/f16kb/gcccar.inc | 2 +- 40 files changed, 69 insertions(+), 69 deletions(-) diff --git a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c index 1dbe440..3a3be35 100644 --- a/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f10/Legacy/Proc/hobTransfer.c @@ -120,7 +120,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -151,7 +151,7 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c index 10f4f5c..87dda2a 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/Feature/cpuCacheInit.c @@ -208,7 +208,7 @@ AllocateExecutionCache ( GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **)&CacheInfoPtr, &Ignored, StdHeader); - // Setup MTTRs for region 0 to region 2 + // Setup MTRRs for region 0 to region 2 VariableMttrBase = AMD_MTRR_VARIABLE_BASE6; for (i = 0; i < 3; i++) { // Exit if no more cache available @@ -265,7 +265,7 @@ AllocateExecutionCache ( if (StartAddr < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region if ((StartAddr + ExeCacheSize) > 0xFFFFF) { ExeCacheSize = 0xFFFFF - StartAddr; AgesaStatus = AGESA_WARNING; @@ -276,7 +276,7 @@ AllocateExecutionCache ( i, StartAddr, ExeCacheSize, 0, StdHeader); } - // Find start and end of MTTR + // Find start and end of MTRR StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((StartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + (((StartAddr + ExeCacheSize) >> 15) & 0x7); @@ -290,14 +290,14 @@ AllocateExecutionCache ( } } - // Setup MTTRs + // Setup MTRRs MsrData = WP_IO; for (CurrentMtrr = StartFixMtrr; CurrentMtrr <= EndFixMtrr; CurrentMtrr++) { LibAmdMsrWrite (CurrentMtrr, &MsrData, StdHeader); } } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region if (VariableMttrBase > AMD_MTRR_VARIABLE_BASE7) { AgesaStatus = AGESA_ERROR; AgesaInfo = AGESA_THREE_CACHE_REGIONS_ABOVE_1MB; @@ -373,7 +373,7 @@ AllocateExecutionCache ( } } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm index 0b796c8..e92c945 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.asm @@ -147,7 +147,7 @@ EFLoop: .endw .endif - ; restore variable MTTR6 and MTTR7 to default states + ; restore variable MTRR6 and MTRR7 to default states mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6 xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 xor edx, edx diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c index 2421bb9..789a6bd 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cahalt.c @@ -156,7 +156,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); } - // restore variable MTTR6 and MTTR7 to default states + // restore variable MTRR6 and MTRR7 to default states for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared __writemsr (msrno, 0); diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c index b5be972..aa79b16 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/heapManager.c @@ -153,7 +153,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f10/cpcarmac.inc b/src/vendorcode/amd/agesa/f10/cpcarmac.inc index f7119d1..e893d1e 100644 --- a/src/vendorcode/amd/agesa/f10/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f10/cpcarmac.inc @@ -187,7 +187,7 @@ SetupDramMap: inc cl .endw - ; setup MTTR for stacks + ; setup MTRR for stacks mov ebx, WB_DRAM_TYPE .if (di == 0) ;core 0 .if (si > 3) ; node 0 to 3 located at 40000h, node 4 to 7 located at 50000h @@ -198,7 +198,7 @@ SetupDramMap: or edx, ebx _WRMSR .else ;core 1 to core 7 start at 60000h - .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTTR + .if (si < 4) ; node 0 to 3 using AMD_MTRR_FIX64K_6000 and AMD_MTRR_FIX64K_7000 MTRR shl ebx, 16 .if (si > 1) shl ebx, 8 @@ -207,7 +207,7 @@ SetupDramMap: _RDMSR or edx, ebx _WRMSR - .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTTR + .else ; node 4 to 7 uses AMD_MTRR_FIX16K_80000 and AMD_MTRR_FIX16K_9000 MTRR mov ecx, AMD_MTRR_FIX16k_80000 _RDMSR .if (si < 6) ; node 4 and node 5 diff --git a/src/vendorcode/amd/agesa/f10/gcccar.inc b/src/vendorcode/amd/agesa/f10/gcccar.inc index 61a8d3e..1526eef 100644 --- a/src/vendorcode/amd/agesa/f10/gcccar.inc +++ b/src/vendorcode/amd/agesa/f10/gcccar.inc @@ -1353,7 +1353,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c index bf8e6d2..eac7c2a 100644 --- a/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c @@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFFull; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c index fbc1b5e..d84e689 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c index 1bad891..57483a9 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cahalt.c @@ -148,7 +148,7 @@ PrimaryCoreFunctions (AP_MTRR_SETTINGS *ApMtrrSettingsList) __writemsr (ApMtrrSettingsList [index].MsrAddr, ApMtrrSettingsList [index].MsrData); } - // restore variable MTTR6 and MTTR7 to default states + // restore variable MTRR6 and MTRR7 to default states for (msrno = 0x20F; msrno <= 0x20C; msrno--) // decrement so that the pair is disable before the base is cleared __writemsr (msrno, 0); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c index dacaded..e9e41cb 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c @@ -188,7 +188,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f12/cpcarmac.inc b/src/vendorcode/amd/agesa/f12/cpcarmac.inc index b4add85..5bd41d0 100644 --- a/src/vendorcode/amd/agesa/f12/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f12/cpcarmac.inc @@ -220,7 +220,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f12/gcccar.inc b/src/vendorcode/amd/agesa/f12/gcccar.inc index d7da81d..a256633 100644 --- a/src/vendorcode/amd/agesa/f12/gcccar.inc +++ b/src/vendorcode/amd/agesa/f12/gcccar.inc @@ -1347,7 +1347,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c index bb23204..3e97fe6 100644 --- a/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f14/Legacy/Proc/hobTransfer.c @@ -140,7 +140,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -171,14 +171,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **)&CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c index 6d06745..dbe4717 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuCacheInit.c @@ -280,7 +280,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -298,7 +298,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -324,7 +324,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm index 3ffe146..de5201d 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahalt.asm @@ -173,7 +173,7 @@ EFLoop: .endw .endif - ; restore variable MTTR6 and MTTR7 to default states + ; restore variable MTRR6 and MTRR7 to default states mov ecx, AMD_MTRR_VARIABLE_BASE6 ; clear MTRRPhysBase6 MTRRPhysMask6 xor eax, eax ; and MTRRPhysBase7 MTRRPhysMask7 xor edx, edx diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S index 48ee5d0..137261c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cahaltasm.S @@ -157,7 +157,7 @@ EFLoop: jmp 5b /* .endw */ 4: /* .endif */ - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ movl $AMD_MTRR_VARIABLE_BASE6, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ xor %eax, %eax /* and MTRRPhysBase7 MTRRPhysMask7 */ xor %edx, %edx diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c index f6b409f..0e4bce9 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c @@ -192,7 +192,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f14/cpcarmac.inc b/src/vendorcode/amd/agesa/f14/cpcarmac.inc index b703b7f..54e7f95 100644 --- a/src/vendorcode/amd/agesa/f14/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f14/cpcarmac.inc @@ -215,7 +215,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f14/gcccar.inc b/src/vendorcode/amd/agesa/f14/gcccar.inc index 7037344..7ff9a86 100644 --- a/src/vendorcode/amd/agesa/f14/gcccar.inc +++ b/src/vendorcode/amd/agesa/f14/gcccar.inc @@ -1361,7 +1361,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c index b2accb2..3eb908e 100644 --- a/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f15/Legacy/Proc/hobTransfer.c @@ -138,7 +138,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -169,14 +169,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c index ca60b2b..274844b 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/Feature/cpuCacheInit.c @@ -282,7 +282,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -300,7 +300,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -326,7 +326,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S index 221805a..012c4f7 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cahaltasm.S @@ -187,7 +187,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c index f42c35d..e1fc324 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/heapManager.c @@ -189,7 +189,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15/cpcarmac.inc b/src/vendorcode/amd/agesa/f15/cpcarmac.inc index 24a6073..8947491 100644 --- a/src/vendorcode/amd/agesa/f15/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f15/cpcarmac.inc @@ -221,7 +221,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15/gcccar.inc b/src/vendorcode/amd/agesa/f15/gcccar.inc index b20c77e..03e676f 100644 --- a/src/vendorcode/amd/agesa/f15/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15/gcccar.inc @@ -1368,7 +1368,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c index 7ed5f16..9f5243f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f15tn/Legacy/Proc/hobTransfer.c @@ -137,7 +137,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -168,14 +168,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c index fcd7bf4..e9c8922 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S index 4ab535a..c1e7ab7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cahaltasm.S @@ -187,7 +187,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c index 2e45471..fdf2581 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.c @@ -188,7 +188,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc index 98c7696..19044bd 100644 --- a/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc +++ b/src/vendorcode/amd/agesa/f15tn/cpcarmac.inc @@ -220,7 +220,7 @@ AMD_ENABLE_STACK MACRO mov ecx, TOP_MEM2 ; MSR:C001_001D _WRMSR - ; setup MTTRs for stacks + ; setup MTRRs for stacks ; A speculative read can be generated by a speculative fetch mis-aligned in a code zone ; or due to a data zone being interpreted as code. When a speculative read occurs outside a ; controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f15tn/gcccar.inc b/src/vendorcode/amd/agesa/f15tn/gcccar.inc index c76ad16..4f6bb9c 100644 --- a/src/vendorcode/amd/agesa/f15tn/gcccar.inc +++ b/src/vendorcode/amd/agesa/f15tn/gcccar.inc @@ -1677,7 +1677,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction. diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h index a3b3472..dcec443 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/Filecode.h @@ -575,7 +575,7 @@ #define PROC_MEM_TECH_DDR3_MTTECC3_FILECODE (0XF588) #define PROC_MEM_TECH_DDR3_MTLRDIMM3_FILECODE (0XF589) #define PROC_MEM_TECH_MTTHRCSEEDTRAIN_FILECODE (0XF58A) -#define PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE (0XF58B) -#define PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) +#define PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE (0XF58B) +#define PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE (0XF58C) #endif // _FILECODE_H_ diff --git a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c index 7f03e13..a795b2e 100644 --- a/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c +++ b/src/vendorcode/amd/agesa/f16kb/Legacy/Proc/hobTransfer.c @@ -141,7 +141,7 @@ CopyHeapToTempRamAtPost ( // if (AmdHeapRamAddress < 0x100000) { // Region below 1MB - // Fixed MTTR region + // Fixed MTRR region // turn on modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -172,14 +172,14 @@ CopyHeapToTempRamAtPost ( LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader); } - // Turn on MTTR enable bit and turn off modification bit + // Turn on MTRR enable bit and turn off modification bit LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x40000; MsrData &= 0xFFFFFFFFFFF7FFFF; LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader); } else { // Region above 1MB - // Variable MTTR region + // Variable MTRR region // Get family specific cache Info GetCpuServicesOfCurrentCore ((CONST CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader); FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (CONST VOID **) &CacheInfoPtr, &Ignored, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c index b5a38b8..d8243ad 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/Feature/cpuCacheInit.c @@ -281,7 +281,7 @@ AllocateExecutionCache ( RequestSize = AmdExeAddrMapPtr[i].ExeCacheSize; if (RequestStartAddr < 0x100000) { - // Region starts below 1MB - Fixed MTTR region, + // Region starts below 1MB - Fixed MTRR region, // turn on modification bit: MtrrFixDramModEn LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader); MsrData |= 0x80000; @@ -299,7 +299,7 @@ AllocateExecutionCache ( i, RequestStartAddr, RequestSize, 0, StdHeader); } - // Find start MTTR and end MTTR for the requested region + // Find start MTRR and end MTRR for the requested region StartFixMtrr = AMD_MTRR_FIX4K_BASE + ((RequestStartAddr >> 15) & 0x7); EndFixMtrr = AMD_MTRR_FIX4K_BASE + ((((RequestStartAddr + RequestSize) - 1) >> 15) & 0x7); @@ -325,7 +325,7 @@ AllocateExecutionCache ( } else { - // Region above 1MB - Variable MTTR region + // Region above 1MB - Variable MTRR region // Need to check both VarMTRRs for each requested region for match or overlap // diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S index 97f6f16..5803c26 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cahaltasm.S @@ -179,7 +179,7 @@ EFLoop: AMD_DISABLE_STACK_FAMILY_HOOK - /* restore variable MTTR6 and MTTR7 to default states */ + /* restore variable MTRR6 and MTRR7 to default states */ bt $FLAG_IS_PRIMARY, %esi /* .if (esi & 1h) */ jz 6f movl $AMD_MTRR_VARIABLE_MASK7, %ecx /* clear MTRRPhysBase6 MTRRPhysMask6 */ diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c index 42a6afa..3f3dbda 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/heapManager.c @@ -191,7 +191,7 @@ HeapManagerInit ( MsrData = (UINT64) (AMD_TEMP_TOM); LibAmdMsrWrite (TOP_MEM, &MsrData, StdHeader); - // Enable variable MTTRs + // Enable variable MTRRs LibAmdMsrRead (SYS_CFG, &MsrData, StdHeader); MsrData |= AMD_VAR_MTRR_ENABLE_BIT; LibAmdMsrWrite (SYS_CFG, &MsrData, StdHeader); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c index a568f9e..832e807 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DEyeRimSearch.c @@ -64,7 +64,7 @@ CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_MTTRDDQS2DEYERIMSEARCH_FILECODE +#define FILECODE PROC_MEM_TECH_MTRRDDQS2DEYERIMSEARCH_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c index 0fc13f9..08c7730 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Tech/mttRdDqs2DTraining.c @@ -70,7 +70,7 @@ CODE_GROUP (G1_PEICC) RDATA_GROUP (G1_PEICC) -#define FILECODE PROC_MEM_TECH_MTTRDDQS2DTRAINING_FILECODE +#define FILECODE PROC_MEM_TECH_MTRRDDQS2DTRAINING_FILECODE /*---------------------------------------------------------------------------- * DEFINITIONS AND MACROS * diff --git a/src/vendorcode/amd/agesa/f16kb/gcccar.inc b/src/vendorcode/amd/agesa/f16kb/gcccar.inc index 90c8cc6..357ad89 100644 --- a/src/vendorcode/amd/agesa/f16kb/gcccar.inc +++ b/src/vendorcode/amd/agesa/f16kb/gcccar.inc @@ -1042,7 +1042,7 @@ SetupStack: mov $TOP_MEM2, %ecx # MSR:C001_001D _WRMSR - # setup MTTRs for stacks + # setup MTRRs for stacks # A speculative read can be generated by a speculative fetch mis-aligned in a code zone # or due to a data zone being interpreted as code. When a speculative read occurs outside a # controlled region (intentionally used by software), it could cause an unwanted cache eviction.

1 0

New patch to review for coreboot: 3fc671f Rename mainboard vendor Google to GOOGLE
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5346 -gerrit commit 3fc671f7e4256aae58fb3a6a85d6304b04982a49 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Mon Apr 8 16:48:10 2013 -0700 Rename mainboard vendor Google to GOOGLE This is what was built into all our products, so make sure that no utilities get confused by a difference in spelling. The linux kernel has DMI matching code for GOOGLE. Without the proper spelling the drivers won't be bound correctly. Signed-off-by: Stefan Reinauer <reinauer(a)google.com> BUG=none TEST=emerge-link chromeos-coreboot-link produces a bootable image BRANCH=none Change-Id: I96bf3e6076b05824825b46e5d8da5cf0c6e08507 Original-Change-Id: Icef8a5a6f976f9f87cb7e065284541ecaa213c1b Reviewed-on: https://gerrit.chromium.org/gerrit/47607 Reviewed-by: Ronald G. Minnich <rminnich(a)chromium.org> Commit-Queue: Stefan Reinauer <reinauer(a)google.com> Tested-by: Stefan Reinauer <reinauer(a)google.com> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/Kconfig b/src/mainboard/google/Kconfig index 85c8592..a66bcf2 100644 --- a/src/mainboard/google/Kconfig +++ b/src/mainboard/google/Kconfig @@ -60,6 +60,6 @@ source "src/mainboard/google/stout/Kconfig" config MAINBOARD_VENDOR string "Mainboard Vendor" - default "Google" + default "GOOGLE" endif # VENDOR_GOOGLE

1 0

Patch set updated for coreboot: 81cada3 chromeos: provide option to dynamically allocate ram oops buffer
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5257 -gerrit commit 81cada3cbd92ec41d9dd126f525d443c3cbf3111 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Feb 14 00:30:04 2014 -0600 chromeos: provide option to dynamically allocate ram oops buffer Fixing the location of the ram oops buffer can lead to certain kernel and boot loaders being confused when there is a ram reservation low in the address space. Alternatively provide a mechanism to allocate the ram oops buffer in cbmem. As cbmem is usually high in the address space it avoids low reservation confusion. The patch uncondtionally provides a GOOG9999 ACPI device with a single memory resource describing the memory region used for the ramoops region. BUG=None BRANCH=baytrail,haswell TEST=Built and booted with and w/o dynamic ram oops. With the corresponding kernel change things behave correctly. Change-Id: Ide2bb4434768c9f9b90e125adae4324cb1d2d073 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/cbmem.h | 1 + src/lib/cbmem_info.c | 1 + src/vendorcode/google/chromeos/Kconfig | 7 +- src/vendorcode/google/chromeos/Makefile.inc | 1 + src/vendorcode/google/chromeos/acpi/chromeos.asl | 2 + src/vendorcode/google/chromeos/acpi/gnvs.asl | 4 +- src/vendorcode/google/chromeos/acpi/ramoops.asl | 43 ++++++++++ src/vendorcode/google/chromeos/chromeos.h | 15 ++++ src/vendorcode/google/chromeos/gnvs.c | 2 + src/vendorcode/google/chromeos/gnvs.h | 4 +- src/vendorcode/google/chromeos/ramoops.c | 99 ++++++++++++++++++++++++ 11 files changed, 176 insertions(+), 3 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 7cb12b2..f103b30 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -62,6 +62,7 @@ #define CBMEM_ID_REFCODE 0x04efc0de #define CBMEM_ID_REFCODE_CACHE 0x4efc0de5 #define CBMEM_ID_SMM_SAVE_SPACE 0x07e9acee +#define CBMEM_ID_RAM_OOPS 0x05430095 #define CBMEM_ID_NONE 0x00000000 #define CBMEM_ID_AGESA_RUNTIME 0x41474553 #define CBMEM_ID_HOB_POINTER 0x484f4221 diff --git a/src/lib/cbmem_info.c b/src/lib/cbmem_info.c index 339e6b9..42348e4 100644 --- a/src/lib/cbmem_info.c +++ b/src/lib/cbmem_info.c @@ -52,6 +52,7 @@ static struct cbmem_id_to_name { { CBMEM_ID_REFCODE, "REFCODE " }, { CBMEM_ID_SMM_SAVE_SPACE, "SMM BACKUP " }, { CBMEM_ID_REFCODE_CACHE, "REFCODE $ " }, + { CBMEM_ID_RAM_OOPS, "RAMOOPS " }, }; void cbmem_print_entry(int n, u32 id, u64 base, u64 size) diff --git a/src/vendorcode/google/chromeos/Kconfig b/src/vendorcode/google/chromeos/Kconfig index 2f17b7e..ed358f8 100644 --- a/src/vendorcode/google/chromeos/Kconfig +++ b/src/vendorcode/google/chromeos/Kconfig @@ -53,10 +53,15 @@ config CHROMEOS_RAMOOPS bool "Reserve space for Chrome OS ramoops" default y +config CHROMEOS_RAMOOPS_DYNAMIC + bool "Allocate RAM oops buffer in cbmem" + default n + depends on CHROMEOS_RAMOOPS + config CHROMEOS_RAMOOPS_RAM_START hex "Physical address of preserved RAM" default 0x00f00000 - depends on CHROMEOS_RAMOOPS + depends on CHROMEOS_RAMOOPS && !CHROMEOS_RAMOOPS_DYNAMIC config CHROMEOS_RAMOOPS_RAM_SIZE hex "Size of preserved RAM" diff --git a/src/vendorcode/google/chromeos/Makefile.inc b/src/vendorcode/google/chromeos/Makefile.inc index 4fa22ea..007bd57 100644 --- a/src/vendorcode/google/chromeos/Makefile.inc +++ b/src/vendorcode/google/chromeos/Makefile.inc @@ -25,6 +25,7 @@ romstage-$(CONFIG_ARCH_X86) += vboot.c ramstage-y += gnvs.c romstage-y += fmap.c ramstage-y += fmap.c +ramstage-$(CONFIG_CHROMEOS_RAMOOPS) += ramoops.c smm-y += fmap.c ifneq ($(wildcard src/mainboard/$(MAINBOARDDIR)/chromeos.c),) ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/chromeos.c diff --git a/src/vendorcode/google/chromeos/acpi/chromeos.asl b/src/vendorcode/google/chromeos/acpi/chromeos.asl index 278296c..8f63f12 100644 --- a/src/vendorcode/google/chromeos/acpi/chromeos.asl +++ b/src/vendorcode/google/chromeos/acpi/chromeos.asl @@ -107,3 +107,5 @@ Device (CRHW) Return (TSLM) } } + +#include "ramoops.asl" diff --git a/src/vendorcode/google/chromeos/acpi/gnvs.asl b/src/vendorcode/google/chromeos/acpi/gnvs.asl index dc4a0bf..5377a85 100644 --- a/src/vendorcode/google/chromeos/acpi/gnvs.asl +++ b/src/vendorcode/google/chromeos/acpi/gnvs.asl @@ -34,4 +34,6 @@ VBT9, 32, // 0x196 - FMAP base address CHVD, 24576, // 0x19a - VDAT space filled by verified boot VBTA, 32, // 0xd9a - pointer to smbios FWID MEHH, 256, // 0xd9e - Management Engine Hash - // 0xdbe +RMOB, 32, // 0xdbe - RAM oops base address +RMOL, 32, // 0xdc2 - RAM oops length + // 0xdc6 diff --git a/src/vendorcode/google/chromeos/acpi/ramoops.asl b/src/vendorcode/google/chromeos/acpi/ramoops.asl new file mode 100644 index 0000000..e435489 --- /dev/null +++ b/src/vendorcode/google/chromeos/acpi/ramoops.asl @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +Scope (\_SB) +{ + Device(RMOP) + { + Name (_HID, "GOOG9999") + Name (_CID, "GOOG9999") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, MRES) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^MRES._BAS, RBAS) + CreateDwordField (^RBUF, ^MRES._LEN, RLEN) + Store (\RMOB, RBAS) + Store (\RMOL, RLEN) + Return (^RBUF) + } + } +} diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index 7fe8f06..2a781ef 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -51,4 +51,19 @@ void init_chromeos(int bootmode); int vboot_get_handoff_info(void **addr, uint32_t *size); #endif +#if CONFIG_CHROMEOS_RAMOOPS +#include "gnvs.h" +struct device; + +void chromeos_ram_oops_init(chromeos_acpi_t *chromeos); +#if CONFIG_CHROMEOS_RAMOOPS_DYNAMIC +static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} +#else /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ +void chromeos_reserve_ram_oops(struct device *dev, int idx); +#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ +#else /* !CONFIG_CHROMEOS_RAMOOPS */ +static inline void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) {} +static inline void chromeos_reserve_ram_oops(struct device *dev, int idx) {} +#endif /* CONFIG_CHROMEOS_RAMOOPS */ + #endif diff --git a/src/vendorcode/google/chromeos/gnvs.c b/src/vendorcode/google/chromeos/gnvs.c index 9f51097..528143c 100644 --- a/src/vendorcode/google/chromeos/gnvs.c +++ b/src/vendorcode/google/chromeos/gnvs.c @@ -72,6 +72,8 @@ void chromeos_init_vboot(chromeos_acpi_t *chromeos) reason ? reason : ELOG_CROS_RECOVERY_MODE_BUTTON); } #endif + + chromeos_ram_oops_init(chromeos); } void chromeos_set_me_hash(u32 *hash, int len) diff --git a/src/vendorcode/google/chromeos/gnvs.h b/src/vendorcode/google/chromeos/gnvs.h index 00fe443..fe7d77a 100644 --- a/src/vendorcode/google/chromeos/gnvs.h +++ b/src/vendorcode/google/chromeos/gnvs.h @@ -58,7 +58,9 @@ typedef struct { u8 vdat[3072]; // 19a u32 vbt10; // d9a smbios bios version u32 mehh[8]; // d9e management engine hash - // dbe + u32 ramoops_base; // dbe ramoops base address + u32 ramoops_len; // dc2 ramoops length + u8 pad[314]; // dc6-eff } __attribute__((packed)) chromeos_acpi_t; extern chromeos_acpi_t *vboot_data; diff --git a/src/vendorcode/google/chromeos/ramoops.c b/src/vendorcode/google/chromeos/ramoops.c new file mode 100644 index 0000000..500bc90 --- /dev/null +++ b/src/vendorcode/google/chromeos/ramoops.c @@ -0,0 +1,99 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <stddef.h> +#include <stdint.h> +#include <bootstate.h> +#include <console/console.h> +#include <cbmem.h> +#include <device/device.h> +#include "chromeos.h" + +static void set_ramoops(chromeos_acpi_t *chromeos, void *ram_oops, size_t size) +{ + if (chromeos == NULL) { + printk(BIOS_DEBUG, "chromeos gnvs is NULL. ramoops not set.\n"); + return; + } + + printk(BIOS_DEBUG, "Ramoops buffer: 0x%zx(a)0x%p.\n", size, ram_oops); + chromeos->ramoops_base = (uintptr_t)ram_oops; + chromeos->ramoops_len = size; +} + +static void reserve_ram_oops_dynamic(chromeos_acpi_t *chromeos) +{ + const size_t size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; + void *ram_oops; + + if (!IS_ENABLED(CONFIG_CHROMEOS_RAMOOPS_DYNAMIC)) + return; + + ram_oops = cbmem_add(CBMEM_ID_RAM_OOPS, size); + + set_ramoops(chromeos, ram_oops, size); +} + +#if CONFIG_CHROMEOS_RAMOOPS_DYNAMIC +static inline void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) {} +#else /* !CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ + +static const unsigned long ramoops_base = CONFIG_CHROMEOS_RAMOOPS_RAM_START; +static const unsigned long ramoops_size = CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE; + +/* + * Save pointer to chromeos structure in memory. This is needed because the + * memory reservation is not done when chromeos_init() is called. However, + * the pointer to the chromeos_acpi_t structure is needed to update the + * fields with the rserved base and size. + */ +static chromeos_acpi_t *g_chromeos; + +static void set_global_chromeos_pointer(chromeos_acpi_t *chromeos) +{ + g_chromeos = chromeos; +} + +static void update_gnvs(void *arg) +{ + chromeos_acpi_t **chromeos = arg; + + set_ramoops(*chromeos, (void *)ramoops_base, ramoops_size); +} + +static BOOT_STATE_CALLBACK(bscb_ramoops, update_gnvs, &g_chromeos); + +void chromeos_reserve_ram_oops(struct device *dev, int idx) +{ + const unsigned long base = ramoops_base >> 10; + const unsigned long size = ramoops_size >> 10; + + reserved_ram_resource(dev, idx, base, size); + + boot_state_sched_on_exit(&bscb_ramoops, BS_WRITE_TABLES); +} +#endif /* CONFIG_CHROMEOS_RAMOOPS_DYNAMIC */ + +void chromeos_ram_oops_init(chromeos_acpi_t *chromeos) +{ + set_global_chromeos_pointer(chromeos); + reserve_ram_oops_dynamic(chromeos); +} +

1 0

Patch set updated for coreboot: 6c81841 OxPCIe uart: Split PCI bridge control
by Kyösti Mälkki 04 Mar '14

04 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237 -gerrit commit 6c81841f2a7c7dfcdb471df11a198aabf3d4c53b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 12:45:09 2014 +0200 OxPCIe uart: Split PCI bridge control None of the bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid but originate from lumpy and/or stumpy devices. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 9 ++- src/device/Kconfig | 29 ++++++++ src/device/Makefile.inc | 1 + src/device/pci_early.c | 115 +++++++++++++++++++++++++++++++ src/drivers/oxford/oxpcie/Kconfig | 64 +---------------- src/drivers/oxford/oxpcie/oxpcie_early.c | 89 +++++------------------- src/include/console/uart.h | 1 - src/include/device/pci.h | 2 + src/southbridge/intel/bd82x6x/Kconfig | 16 +++++ 9 files changed, 191 insertions(+), 135 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index 9e9e4e2..c46d996 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -28,6 +28,11 @@ #include <arch/hlt.h> #include <arch/io.h> +#if CONFIG_EARLY_PCI_BRIDGE +/* FIXME: ROMCC chokes on PCI headers. */ +#include <device/pci.h> +#endif + #ifndef __PRE_RAM__ #include <string.h> #include <types.h> @@ -101,8 +106,8 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_DRIVERS_OXFORD_OXPCIE - oxford_init(); +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); #endif #if CONFIG_CONSOLE_SERIAL uart_init(); diff --git a/src/device/Kconfig b/src/device/Kconfig index eaa0c04..932b4de 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -237,6 +237,35 @@ config PCIEXP_ASPM config PCI_BUS_SEGN_BITS int default 0 + +config EARLY_PCI_BRIDGE + bool "Early PCI bridge" + depends on PCI + default n + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. + + This option enables static configuration for a single pre-defined + PCI bridge function on bus 0. + +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex "bridge device" + default 0x0 + +config EARLY_PCI_BRIDGE_FUNCTION + hex "bridge function" + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex "MMIO window base" + default 0x0 + +endif # EARLY_PCI_BRIDGE + endmenu menu "VGA BIOS" diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index ce412b7..bd41b12 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -11,6 +11,7 @@ ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +ramstage-$(CONFIG_PCI) += pci_early.c ramstage-y += smbus_ops.c romstage-y += device_romstage.c diff --git a/src/device/pci_early.c b/src/device/pci_early.c index c15a4d0..627e5ac 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2011 Google Inc + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,9 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> +#include <delay.h> + +#ifdef __PRE_RAM__ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) { @@ -66,3 +73,111 @@ unsigned pci_find_capability(device_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } +#endif + + +#if CONFIG_EARLY_PCI_BRIDGE + +static void pci_bridge_reset_secondary(device_t p2p_bridge) +{ + u16 reg16; + /* Disable all access through bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + + /* First we reset the secondary bus. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 |= (1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); + + /* Assume we don't have to wait here forever */ + + /* Read back and clear reset bit. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 &= ~(1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); +} + +static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +{ + /* Disable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); + /* Enable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); +} + +static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size) +{ + u16 reg16; + + /* Disable MMIO window behind the bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10); + + if (!size) + return; + + /* Enable MMIO window behind the bridge. */ + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, + ((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0)); + + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); +} + +void pci_early_bridge_init(void) +{ + int timeout, ret = -1; + + /* No PCI-to-PCI bridges are enabled yet, so the one we try to + * configure must have its primary on bus 0. + */ + pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + /* Secondary bus number is mostly irrelevant as we disable + * configuration transactions right after the probe. + */ + u8 secondary = 15; + u8 dev = 0; + u32 mmio_base = CONFIG_EARLY_PCI_MMIO_BASE; + + /* Enable configuration and MMIO over bridge. */ + pci_bridge_reset_secondary(p2p_bridge); + pci_bridge_set_secondary(p2p_bridge, secondary); + pci_bridge_set_mmio(p2p_bridge, mmio_base, 0x4000); + + for (timeout = 20000; timeout && (dev < 32) && ret; timeout--) { + u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID); + + /* Retry request. */ + if (id == 0xffff0001) { + udelay(10); + continue; + } + + /* Empty slot. */ + if (id == 0xffffffff || id == 0) { + dev++; + continue; + } + ret = pci_early_device_probe(secondary, dev, mmio_base); + } + + /* Disable MMIO window if we found no suitable device. */ + if (ret) + pci_bridge_set_mmio(p2p_bridge, 0, 0); + + /* Resource allocator will reconfigure bridges and secondary bus + * number may change. Thus early device cannot reliably use config + * transactions from here on, so we may as well disable them. + */ + pci_bridge_set_secondary(p2p_bridge, 0); +} +#endif /* CONFIG_EARLY_PCI_BRIDGE */ diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 5ad42aa..c2ea7b6 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,68 +1,10 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n + depends on PCI select DRIVERS_UART_8250MEM + select EARLY_PCI_BRIDGE help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 will work. - NOTE: Right now you have to set the base address of your OXPCIe952 - card to exactly the value that the device allocator would set them - later on, or serial console functionality will stop as soon as the - resource allocator assigns a new base address to the device. - -config OXFORD_OXPCIE_BRIDGE_BUS - hex "OXPCIe's PCIe bridge bus number" - default 0x0 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_DEVICE - hex "OXPCIe's PCIe bridge device number" - default 0x1c - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_FUNCTION - hex "OXPCIe's PCIe bridge function number" - default 0x2 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_SUBORDINATE - hex "OXPCIe's PCIe bridge subordinate bus" - default 0x3 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BASE_ADDRESS - hex "Base address for rom stage console" - default 0xe0400000 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up a temporary address - for the OXPCIe952 controller. - + 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 7de9da6..b81fa89 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -23,101 +23,53 @@ #include <stddef.h> #include <arch/io.h> #include <arch/early_variables.h> -#include <delay.h> #include <boot/coreboot_tables.h> #include <console/uart.h> #include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; -#define PCIE_BRIDGE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) - -#define OXPCIE_DEVICE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) - -#define OXPCIE_DEVICE_3 \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) - -static void oxpcie_init_bridge(void) +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { - u16 reg16; - - /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Assume we don't have to wait here forever */ + pci_devfn_t device = PCI_DEV(bus, dev, 0); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Set up subordinate bus number */ - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - - /* Memory window for the OXPCIe952 card */ - // XXX is the calculation of base and limit correct? - pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); - - /* Enable memory access through bridge */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - - u32 timeout = 20000; // Timeout in 10s of microseconds. - u32 id = 0; - for (;;) { - id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); - if (!timeout-- || (id != 0 && id != 0xffffffff)) - break; - udelay(10); - } - - u32 device = OXPCIE_DEVICE; /* unknown default */ + u32 id = pci_read_config32(device, PCI_VENDOR_ID); switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI */ + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and * function 3 is the serial port. So let's go look for * the UART. */ - id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; - device = OXPCIE_DEVICE_3; + return -1; break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ case 0xc1581415: /* e.g. Startech MPEX2S952 */ - device = OXPCIE_DEVICE; break; default: /* No UART here. */ - return; + return -1; } + /* Sanity-check, we assume fixed location. */ + if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) + return -1; + /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); + return 0; } static int oxpcie_uart_active(void) @@ -157,8 +109,3 @@ unsigned int uart_platform_refclk(void) { return 62500000; } - -void oxford_init(void) -{ - oxpcie_init_bridge(); -} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 4516b71..7d92a21 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -47,7 +47,6 @@ int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); -void oxford_init(void); void oxford_remap(unsigned int new_base); #endif /* CONSOLE_UART_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 29d988f..f729c27 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -102,6 +102,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); +void pci_early_bridge_init(void); +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); #endif /* CONFIG_PCI */ diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 9cfa5d5..14281e6 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -41,6 +41,22 @@ config EHCI_BAR hex default 0xfef00000 +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + default 0xe0400000 + +endif + config DRAM_RESET_GATE_GPIO int default 60

1 0

Patch set updated for coreboot: 821b74b console: Refactor uart8250/NE2K
by Kyösti Mälkki 04 Mar '14

04 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5330 -gerrit commit 821b74bad5e2ce8b5ada9fcea0b7a793851c5bf2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Jan 28 11:34:38 2014 +0200 console: Refactor uart8250/NE2K Do this for symmetry with romstage_console.c. Change-Id: If17acfc3da07b1dbefa87162c3c7168deb7b354a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/lib/romcc_console.c | 35 ++++++++++++++++------------------- src/arch/x86/lib/romstage_console.c | 2 +- src/include/console/ne2k.h | 4 ++++ 3 files changed, 21 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 4bd3ad4..15f34d4 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -48,6 +48,16 @@ static void __console_tx_byte(unsigned char byte) #endif } +static void __console_tx_flush(void) +{ +#if CONFIG_CONSOLE_SERIAL + uart_tx_flush(); +#endif +#if CONFIG_CONSOLE_NE2K + ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); +#endif +} + static void __console_tx_nibble(unsigned nibble) { unsigned char digit; @@ -61,13 +71,8 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { -#if CONFIG_CONSOLE_SERIAL - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_NE2K - ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + __console_tx_byte(byte); + __console_tx_flush(); } } @@ -76,10 +81,8 @@ static void __console_tx_hex8(int loglevel, unsigned char value) if (console_loglevel >= loglevel) { __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_hex16(int loglevel, unsigned short value) @@ -89,10 +92,8 @@ static void __console_tx_hex16(int loglevel, unsigned short value) __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_hex32(int loglevel, unsigned int value) @@ -106,10 +107,8 @@ static void __console_tx_hex32(int loglevel, unsigned int value) __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); + __console_tx_flush(); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif } static void __console_tx_string(int loglevel, const char *str) @@ -121,9 +120,7 @@ static void __console_tx_string(int loglevel, const char *str) __console_tx_byte('\r'); __console_tx_byte(ch); } -#if CONFIG_CONSOLE_NE2K - ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT); -#endif + __console_tx_flush(); } } diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 0337245..8393d95 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -38,7 +38,7 @@ void console_tx_byte(unsigned char byte) usb_tx_byte(0, byte); #endif #if CONFIG_CONSOLE_NE2K - ne2k_append_data(&byte, 1, CONFIG_CONSOLE_NE2K_IO_PORT); + ne2k_append_data_byte(byte, CONFIG_CONSOLE_NE2K_IO_PORT); #endif #if CONFIG_CONSOLE_CBMEM && (CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__)) cbmemc_tx_byte(byte); diff --git a/src/include/console/ne2k.h b/src/include/console/ne2k.h index 62424f1..cb3c1ec 100644 --- a/src/include/console/ne2k.h +++ b/src/include/console/ne2k.h @@ -22,4 +22,8 @@ void ne2k_append_data(unsigned char *d, int len, unsigned int base); int ne2k_init(unsigned int eth_nic_base); void ne2k_transmit(unsigned int eth_nic_base); + +#ifndef __ROMCC__ +#define ne2k_append_data_byte(d, base) ne2k_append_data(&d, 1, base) +#endif #endif /* _NE2K_H */

1 0

Patch set updated for coreboot: 5a17088 OxPCIe uart: Move under drivers/uart
by Kyösti Mälkki 04 Mar '14

04 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5329 -gerrit commit 5a17088f0d682d0eb50632f8d898ec72942c8f7f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 28 15:15:12 2014 +0200 OxPCIe uart: Move under drivers/uart This driver is only a thin shell for uart8250mem and we could extend it with further compatible PCI IDs from other vendors/brands. Change-Id: Ic115b1baa0be0dbaa81e4a17a2e466019d3f4a67 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/drivers/Kconfig | 1 - src/drivers/Makefile.inc | 1 - src/drivers/oxford/Kconfig | 1 - src/drivers/oxford/Makefile.inc | 1 - src/drivers/oxford/oxpcie/Kconfig | 10 --- src/drivers/oxford/oxpcie/Makefile.inc | 4 -- src/drivers/oxford/oxpcie/oxpcie.c | 73 -------------------- src/drivers/oxford/oxpcie/oxpcie_early.c | 111 ------------------------------- src/drivers/uart/Kconfig | 11 +++ src/drivers/uart/Makefile.inc | 5 ++ src/drivers/uart/oxpcie.c | 73 ++++++++++++++++++++ src/drivers/uart/oxpcie_early.c | 111 +++++++++++++++++++++++++++++++ 12 files changed, 200 insertions(+), 202 deletions(-) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index 5267ff8..1a5f8ff 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -27,7 +27,6 @@ source src/drivers/ics/Kconfig source src/drivers/intel/Kconfig source src/drivers/ipmi/Kconfig source src/drivers/maxim/Kconfig -source src/drivers/oxford/Kconfig source src/drivers/parade/Kconfig if PC80_SYSTEM source src/drivers/pc80/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 148e257..f11e4b8 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -25,7 +25,6 @@ subdirs-y += i2c subdirs-y += intel subdirs-y += maxim subdirs-y += net -subdirs-y += oxford subdirs-y += parade subdirs-y += realtek subdirs-y += sil diff --git a/src/drivers/oxford/Kconfig b/src/drivers/oxford/Kconfig deleted file mode 100644 index cd7c27c..0000000 --- a/src/drivers/oxford/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source src/drivers/oxford/oxpcie/Kconfig diff --git a/src/drivers/oxford/Makefile.inc b/src/drivers/oxford/Makefile.inc deleted file mode 100644 index 732face..0000000 --- a/src/drivers/oxford/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_DRIVERS_OXFORD_OXPCIE) += oxpcie diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig deleted file mode 100644 index c2ea7b6..0000000 --- a/src/drivers/oxford/oxpcie/Kconfig +++ /dev/null @@ -1,10 +0,0 @@ -config DRIVERS_OXFORD_OXPCIE - bool "Oxford OXPCIe952" - default n - depends on PCI - select DRIVERS_UART_8250MEM - select EARLY_PCI_BRIDGE - help - Support for Oxford OXPCIe952 serial port PCIe cards. - Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc deleted file mode 100644 index 5e3e6e5..0000000 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ /dev/null @@ -1,4 +0,0 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL),y) -ramstage-y += oxpcie_early.c oxpcie.c -romstage-y += oxpcie_early.c -endif diff --git a/src/drivers/oxford/oxpcie/oxpcie.c b/src/drivers/oxford/oxpcie/oxpcie.c deleted file mode 100644 index 76119d2..0000000 --- a/src/drivers/oxford/oxpcie/oxpcie.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <console/console.h> -#include <console/uart.h> -#include <arch/io.h> - -static void oxford_oxpcie_enable(device_t dev) -{ - printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); - - struct resource *res = find_resource(dev, 0x10); - if (!res) { - printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); - return; - } - - printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", - (read32(res->base) >> 8), (read32(res->base) & 0xff)); - printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", - (read32(res->base + 4) & 3)); - printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); -} - - -static void oxford_oxpcie_set_resources(struct device *dev) -{ - pci_dev_set_resources(dev); - - /* Re-initialize OXPCIe base address after set_resources */ - u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); - oxford_remap(mmio_base & ~0xf); -} - -static struct device_operations oxford_oxpcie_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = oxford_oxpcie_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = oxford_oxpcie_enable, - .scan_bus = 0, -}; - -static const struct pci_driver oxford_oxpcie_driver __pci_driver = { - .ops = &oxford_oxpcie_ops, - .vendor = 0x1415, - .device = 0xc158, -}; - -static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = { - .ops = &oxford_oxpcie_ops, - .vendor = 0x1415, - .device = 0xc11b, -}; diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c deleted file mode 100644 index b81fa89..0000000 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ /dev/null @@ -1,111 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Google Inc - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#define __SIMPLE_DEVICE__ - -#include <stdint.h> -#include <stddef.h> -#include <arch/io.h> -#include <arch/early_variables.h> -#include <boot/coreboot_tables.h> -#include <console/uart.h> -#include <device/pci.h> -#include <device/pci_def.h> - -static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; - -int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) -{ - pci_devfn_t device = PCI_DEV(bus, dev, 0); - - u32 id = pci_read_config32(device, PCI_VENDOR_ID); - switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ - /* On this device function 0 is the parallel port, and - * function 3 is the serial port. So let's go look for - * the UART. - */ - device = PCI_DEV(bus, dev, 3); - id = pci_read_config32(device, PCI_VENDOR_ID); - if (id != 0xc11b1415) - return -1; - break; - case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ - case 0xc1581415: /* e.g. Startech MPEX2S952 */ - break; - default: - /* No UART here. */ - return -1; - } - - /* Sanity-check, we assume fixed location. */ - if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) - return -1; - - /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); - - /* Enable memory on device */ - u16 reg16 = pci_read_config16(device, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(device, PCI_COMMAND, reg16); - - car_set_var(oxpcie_present, 1); - return 0; -} - -static int oxpcie_uart_active(void) -{ - return (car_get_var(oxpcie_present)); -} - -unsigned int uart_platform_base(int idx) -{ - if (idx == 0 && oxpcie_uart_active()) - return uart0_base; - if (idx == 1 && oxpcie_uart_active()) - return uart1_base; - return 0; -} - -#ifndef __PRE_RAM__ -void oxford_remap(u32 new_base) -{ - uart0_base = new_base + 0x1000; - uart1_base = new_base + 0x2000; -} - -void uart_fill_lb(void *data) -{ - struct lb_serial serial; - serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial.baseaddr = uart_platform_base(0); - serial.baud = default_baudrate(); - lb_add_serial(&serial, data); - - lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); -} -#endif - -unsigned int uart_platform_refclk(void) -{ - return 62500000; -} diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 889c69a..a979437 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -21,6 +21,17 @@ config HAVE_UART_SPECIAL bool default n +config DRIVERS_UART_OXPCIE + bool "Oxford OXPCIe952" + default n + depends on PCI + select DRIVERS_UART_8250MEM + select EARLY_PCI_BRIDGE + help + Support for Oxford OXPCIe952 serial port PCIe cards. + Currently only devices with the vendor ID 0x1415 and device ID + 0xc158 or 0xc11b will work. + config DRIVERS_UART_PL011 bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 286bff2..5164282 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -18,6 +18,11 @@ ramstage-y += uart8250mem.c smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif +ifeq ($(CONFIG_DRIVERS_UART_OXPCIE),y) +ramstage-y += oxpcie_early.c oxpcie.c +romstage-y += oxpcie_early.c +endif + ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c new file mode 100644 index 0000000..76119d2 --- /dev/null +++ b/src/drivers/uart/oxpcie.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <console/console.h> +#include <console/uart.h> +#include <arch/io.h> + +static void oxford_oxpcie_enable(device_t dev) +{ + printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); + + struct resource *res = find_resource(dev, 0x10); + if (!res) { + printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); + return; + } + + printk(BIOS_DEBUG, "OXPCIe952: Class=%x Revision ID=%x\n", + (read32(res->base) >> 8), (read32(res->base) & 0xff)); + printk(BIOS_DEBUG, "OXPCIe952: %d UARTs detected.\n", + (read32(res->base + 4) & 3)); + printk(BIOS_DEBUG, "OXPCIe952: UART BAR: 0x%x\n", (u32)res->base); +} + + +static void oxford_oxpcie_set_resources(struct device *dev) +{ + pci_dev_set_resources(dev); + + /* Re-initialize OXPCIe base address after set_resources */ + u32 mmio_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0); + oxford_remap(mmio_base & ~0xf); +} + +static struct device_operations oxford_oxpcie_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = oxford_oxpcie_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = oxford_oxpcie_enable, + .scan_bus = 0, +}; + +static const struct pci_driver oxford_oxpcie_driver __pci_driver = { + .ops = &oxford_oxpcie_ops, + .vendor = 0x1415, + .device = 0xc158, +}; + +static const struct pci_driver oxford_oxpcie_driver_2 __pci_driver = { + .ops = &oxford_oxpcie_ops, + .vendor = 0x1415, + .device = 0xc11b, +}; diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c new file mode 100644 index 0000000..b81fa89 --- /dev/null +++ b/src/drivers/uart/oxpcie_early.c @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <stddef.h> +#include <arch/io.h> +#include <arch/early_variables.h> +#include <boot/coreboot_tables.h> +#include <console/uart.h> +#include <device/pci.h> +#include <device/pci_def.h> + +static unsigned int oxpcie_present CAR_GLOBAL; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; + +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) +{ + pci_devfn_t device = PCI_DEV(bus, dev, 0); + + u32 id = pci_read_config32(device, PCI_VENDOR_ID); + switch (id) { + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ + /* On this device function 0 is the parallel port, and + * function 3 is the serial port. So let's go look for + * the UART. + */ + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); + if (id != 0xc11b1415) + return -1; + break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ + case 0xc1581415: /* e.g. Startech MPEX2S952 */ + break; + default: + /* No UART here. */ + return -1; + } + + /* Sanity-check, we assume fixed location. */ + if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) + return -1; + + /* Setup base address on device */ + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); + + /* Enable memory on device */ + u16 reg16 = pci_read_config16(device, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(device, PCI_COMMAND, reg16); + + car_set_var(oxpcie_present, 1); + return 0; +} + +static int oxpcie_uart_active(void) +{ + return (car_get_var(oxpcie_present)); +} + +unsigned int uart_platform_base(int idx) +{ + if (idx == 0 && oxpcie_uart_active()) + return uart0_base; + if (idx == 1 && oxpcie_uart_active()) + return uart1_base; + return 0; +} + +#ifndef __PRE_RAM__ +void oxford_remap(u32 new_base) +{ + uart0_base = new_base + 0x1000; + uart1_base = new_base + 0x2000; +} + +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif + +unsigned int uart_platform_refclk(void) +{ + return 62500000; +}

1 0

New patch to review for coreboot: c6c96ed lenovo/t60: Enable native intel gfx init.
by Vladimir Serbinenko 04 Mar '14

04 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5345 -gerrit commit c6c96edcb903e46165cd4e4ab226698d66a285f2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Mar 4 18:08:26 2014 +0100 lenovo/t60: Enable native intel gfx init. Tested on T60 with intel graphics. Change-Id: Id74d0a1315749052e7313135242e6b64862aa5e1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t60/Kconfig | 3 +++ src/mainboard/lenovo/t60/devicetree.cb | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 6a743d5..0efdbf2 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -21,9 +21,12 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHANNEL_XOR_RANDOMIZATION select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME + select MAINBOARD_HAS_NATIVE_VGA_INIT select EARLY_CBMEM_INIT select H8_DOCK_EARLY_INIT select HAVE_CMOS_DEFAULT + select INTEL_EDID + config MAINBOARD_DIR string default lenovo/t60 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index b87a223..7ecd263 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,6 +22,11 @@ chip northbridge/intel/i945 + register "gpu_hotplug" = "0x00000220" + register "gpu_lvds_use_spread_spectrum_clock" = "1" + register "gpu_lvds_is_dual_channel" = "1" + register "gpu_backlight" = "0x1280128" + device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 device lapic 0 on end

1 0

New patch to review for coreboot: 045d5d0 lenovo/t60: Implement intel VGA callbacks.
by Vladimir Serbinenko 04 Mar '14

04 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5344 -gerrit commit 045d5d02e7db3ac0cb31b74a313ed1908dcdc6a5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Tue Mar 4 17:43:57 2014 +0100 lenovo/t60: Implement intel VGA callbacks. Without it option ROM run results in just a black screen. Change-Id: Id203f55ca0f02c290a3f40ac1ec7c5f23c5580bf Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/t60/mainboard.c | 39 ++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 9d72eee..5b8ea8c 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -34,8 +34,11 @@ #include <northbridge/intel/i945/i945.h> #include <pc80/mc146818rtc.h> #include <arch/x86/include/arch/acpigen.h> +#include <arch/interrupt.h> #include <smbios.h> #include <build.h> +#include <x86emu/x86emu.h> +#define PANEL INT15_5F35_CL_DISPLAY_DEFAULT static acpi_cstate_t cst_entries[] = { { 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } }, @@ -43,6 +46,37 @@ static acpi_cstate_t cst_entries[] = { { 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } }, }; +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE +static int int15_handler(void) +{ + /* The right way to do this is to move this handler code into + * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. + */ + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, X86_AX, X86_BX, X86_CX, X86_DX); + + switch (X86_AX) { + case 0x5f35: /* Boot Display */ + X86_AX = 0x005f; // Success + X86_CL = PANEL; + break; + case 0x5f40: /* Boot Panel Type */ + X86_AX = 0x005f; // Success + X86_CL = 3; + printk(BIOS_DEBUG, "DISPLAY=%x\n", X86_CL); + break; + default: + /* Interrupt was not handled */ + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX); + return 0; + } + + /* Interrupt handled */ + return 1; +} +#endif + int get_cst_entries(acpi_cstate_t **entries) { *entries = cst_entries; @@ -63,6 +97,11 @@ static void mainboard_enable(device_t dev) struct southbridge_intel_i82801gx_config *config; device_t dev0, idedev; +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL || CONFIG_PCI_OPTION_ROM_RUN_REALMODE + /* Install custom int15 handler for VGA OPROM */ + mainboard_interrupt_handlers(0x15, &int15_handler); +#endif + /* If we're resuming from suspend, blink suspend LED */ dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC)

1 0

Patch set updated for coreboot: b34a04d apple/macbook21: EC handline ACPI implementation.
by Vladimir Serbinenko 04 Mar '14

04 Mar '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5323 -gerrit commit b34a04da2962a93289016029ef04845c9ab9c34e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Mar 2 20:24:21 2014 +0100 apple/macbook21: EC handline ACPI implementation. Now battery indicator and lid work. Change-Id: I2f747a408e331a245d91dd5f9c7ead0729f02a67 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/apple/macbook21/acpi/ec.asl | 218 ++++++++++++++++++++++++++++ src/mainboard/apple/macbook21/devicetree.cb | 5 +- src/mainboard/apple/macbook21/dsdt.asl | 1 - 3 files changed, 220 insertions(+), 4 deletions(-) diff --git a/src/mainboard/apple/macbook21/acpi/ec.asl b/src/mainboard/apple/macbook21/acpi/ec.asl index e69de29..01bfb0c 100644 --- a/src/mainboard/apple/macbook21/acpi/ec.asl +++ b/src/mainboard/apple/macbook21/acpi/ec.asl @@ -0,0 +1,218 @@ +Device(EC) +{ + Name(_HID, EISAID("PNP0C09")) + Name(_UID, 0) + + Name(_GPE, 0x17) + Mutex(ECLK, 0) + + OperationRegion(ERAM, EmbeddedControl, 0x00, 0x100) + Field(ERAM, ByteAcc, NoLock, Preserve) + { + Offset(0x01), + LIDS, 1, /* Lid status */ + HPAC, 1, + Offset(0x02), + WKLD, 1, /* Lid wake */ + + Offset(0x20), + SPTR, 8, + SSTS, 8, + SADR, 8, + SCMD, 8, + SBFR, 256, + } + Field(ERAM, ByteAcc, Lock, Preserve) + { + Offset(0x24), + SBDW, 16, + } + + Method(SBPC, 0, NotSerialized) + { + Store(1000, Local0) + While(Local0) + { + If(LEqual(SPTR, 0x00)) + { + Return() + } + + Sleep(1) + Decrement(Local0) + } + } + + Method(SBRW, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x09, SPTR) + SBPC() + Store(SBDW, Local0) + Release(ECLK) + Return(Local0) + } + + Method(SBRB, 2, NotSerialized) + { + Acquire(ECLK, 0xFFFF) + Store(ShiftLeft(Arg0, 0x01), SADR) + Store(Arg1, SCMD) + Store(0x0B, SPTR) + SBPC() + Store(SBFR, Local0) + Release(ECLK) + Return(Local0) + } + + /* LID status change. */ + Method(_Q20, 0, NotSerialized) + { + Notify(LID, 0x80) + } + + /* AC status change. */ + Method(_Q21, 0, NotSerialized) + { + Notify(AC, 0x80) + } + + Method(_CRS, 0) + { + Name(ECMD, ResourceTemplate() + { + IO(Decode16, 0x62, 0x62, 1, 1) + IO(Decode16, 0x66, 0x66, 1, 1) + }) + Return(ECMD) + } + + Method(_INI, 0, NotSerialized) + { + } + + Device(LID) + { + Name(_HID, "PNP0C0D") + + Method(_LID, 0, NotSerialized) + { + return(LIDS) + } + } + + Device(AC) + { + Name(_HID, "ACPI0003") + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB } ) + + Method(_PSR, 0, NotSerialized) + { + return(HPAC) + } + + Method(_STA, 0, NotSerialized) + { + Return(0x0f) + } + } + + Device(BAT0) + { + Name(_HID, EisaId("PNP0C0A")) + Name(_UID, 0x00) + Name(_PCL, Package() { \_SB }) + + Name(BATS, Package() + { + 0x00, // 0: PowerUnit: Report in mWh + 0xFFFFFFFF, // 1: Design cap + 0xFFFFFFFF, // 2: Last full charge cap + 0x01, // 3: Battery Technology + 10800, // 4: Design Voltage(mV) + 0x00, // 5: Warning design capacity + 200, // 6: Low design capacity + 10, // 7: granularity1 + 10, // 8: granularity2 + "", // 9: Model number + "", // A: Serial number + "", // B: Battery Type + "" // C: OEM information + }) + + Name(BATI, Package() + { + 0, // Battery State + // Bit 0 - discharge + // Bit 1 - charge + // Bit 2 - critical state + 0, // Battery present Rate + 0, // Battery remaining capacity + 0 // Battery present voltage + }) + + Method(_BIF, 0, NotSerialized) + { + Multiply(^^SBRW(0x0B, 0x18), 10, Index(BATS, 0x01)) + Multiply(^^SBRW(0x0B, 0x10), 10, Index(BATS, 0x02)) + Store(^^SBRW(0x0B, 0x19), Index(BATS, 0x04)) + Store(^^SBRB(0x0B, 0x21), Index(BATS, 0x09)) + Store(^^SBRB(0x0B, 0x22), Index(BATS, 0x0B)) + Store(^^SBRB(0x0B, 0x20), Index(BATS, 0x0C)) + + Return(BATS) + } + + Method(_STA, 0, NotSerialized) + { + If(And(^^SBRW(0x0A, 0x01), 0x01)) { + Return(0x1f) + } else { + Return(0x0f) + } + } + + Method(_BST, 0, NotSerialized) + { + /* Check for battery presence. */ + If(LNot(And(^^SBRW(0x0A, 0x01), 0x01))) { + Return(Package(4) { + 0, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }) + } + Store(^^SBRW(0x0B, 0x09), Local1) + Store(Local1, Index(BATI, 0x03)) + Store(^^SBRW(0x0B, 0x0A), Local0) + /* Sign-extend Local0. */ + If(And(Local0, 0x8000)) + { + Not(Local0, Local0) + And(Increment(Local0), 0xFFFF, Local0) + } + + Multiply(Local0, Local1, Local0) + Divide(Local0, 1000, , Index(BATI, 1)) + Multiply(^^SBRW(0x0B, 0x0F), 10, Index(BATI, 2)) + If(HPAC) + { + If(LNot(And(^^SBRW(0x0B, 0x16), 0x40))) { + Store(2, Index(BATI, 0)) + } Else { + Store(0, Index(BATI, 0)) + } + } + Else + { + Store(0x01, Index(BATI, 0)) + } + + Return(BATI) + } + } +} diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 3a740e0..d7814f4 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -57,9 +57,8 @@ chip northbridge/intel/i945 # 0 No effect (default) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set) - register "gpi13_routing" = "2" - register "gpi12_routing" = "1" - register "gpi8_routing" = "2" + register "gpi1_routing" = "2" + register "gpi7_routing" = "2" register "sata_ahci" = "0x1" register "sata_ports_implemented" = "0x04" diff --git a/src/mainboard/apple/macbook21/dsdt.asl b/src/mainboard/apple/macbook21/dsdt.asl index e654d20..5ba7b09 100644 --- a/src/mainboard/apple/macbook21/dsdt.asl +++ b/src/mainboard/apple/macbook21/dsdt.asl @@ -19,7 +19,6 @@ * MA 02110-1301 USA */ -#define THINKPAD_EC_GPE 28 #define BRIGHTNESS_UP \DSPC.BRTU #define BRIGHTNESS_DOWN \DSPC.BRTD #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0

1 0

← Newer
1
...
38
39
40
41
42
43
44
...
59
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2014