coreboot-gerrit March 2014

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Patch set updated for coreboot: d3e8184 uart: Prepare to support multiple base addresses
by Kyösti Mälkki 04 Mar '14

04 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5309 -gerrit commit d3e8184e9c49ec40cf103894ea21e526abce3ec0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Feb 24 20:51:30 2014 +0200 uart: Prepare to support multiple base addresses Prepare low-level register access to take UART base address as a parameter. This is done to support a list of base addresses defined in the platform. Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart_console.c | 15 ++++++++--- src/cpu/samsung/exynos5250/uart.c | 50 +++++++++++++++++------------------- src/cpu/samsung/exynos5420/uart.c | 44 +++++++++++++++---------------- src/cpu/ti/am335x/uart.c | 30 +++++++++++----------- src/drivers/uart/pl011.c | 13 ++++++---- 5 files changed, 78 insertions(+), 74 deletions(-) diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index aea1189..5cc1a66 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -43,9 +43,14 @@ unsigned int uart_platform_refclk(void) return 24000000; } +unsigned int uart_platform_base(int idx) +{ + return (unsigned int)get_console_uart_base_addr(); +} + void uart_init(void) { - void *uart_base = get_console_uart_base_addr(); + void *uart_base = (void *) uart_platform_base(0); /* Use default 8N1 encoding */ a10_uart_configure(uart_base, default_baudrate(), @@ -55,18 +60,20 @@ void uart_init(void) unsigned char uart_rx_byte(void) { - return a10_uart_rx_blocking(get_console_uart_base_addr()); + void *uart_base = (void *) uart_platform_base(0); + return a10_uart_rx_blocking(uart_base); } void uart_tx_byte(unsigned char data) { - a10_uart_tx_blocking(get_console_uart_base_addr(), data); + void *uart_base = (void *) uart_platform_base(0); + a10_uart_tx_blocking(uart_base, data); } #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return (uint32_t) get_console_uart_base_addr(); + return uart_platform_base(0); } #endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 14d140c..82e221d 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - // TODO initialize with correct peripheral id by base_port. exynos_pinmux_uart3(); @@ -102,12 +96,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -130,14 +123,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -147,49 +138,54 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } -static void exynos5_uart_tx_flush(void) +static void exynos5_uart_tx_flush(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - while (readl(&uart->ufstat) & 0x1ff0000); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { - exynos5_uart_tx_flush(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_flush(uart); } diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index d05adcd..e3ae88d 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -28,9 +28,6 @@ #define RX_FIFO_FULL_MASK (1 << 8) #define TX_FIFO_FULL_MASK (1 << 24) -/* FIXME(dhendrix): exynos5 has 4 UARTs and its functions in u-boot take a - base_port argument. However console_driver functions do not. */ -static uint32_t base_port = CONFIG_CONSOLE_SERIAL_UART_ADDRESS; /* * The coefficient, used to calculate the baudrate on S5P UARTs is @@ -58,9 +55,8 @@ static const int udivslot[] = { 0xffdf, }; -static void serial_setbrg_dev(void) +static void serial_setbrg_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; u32 uclk; u32 val; @@ -87,10 +83,8 @@ static void serial_setbrg_dev(void) * Initialise the serial port with the given baudrate. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void exynos5_init_dev(void) +static void exynos5_init_dev(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* enable FIFOs */ writel(0x1, &uart->ufcon); writel(0, &uart->umcon); @@ -99,12 +93,11 @@ static void exynos5_init_dev(void) /* No interrupts, no DMA, pure polling */ writel(0x245, &uart->ucon); - serial_setbrg_dev(); + serial_setbrg_dev(uart); } -static int exynos5_uart_err_check(int op) +static int exynos5_uart_err_check(struct s5p_uart *uart, int op) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; unsigned int mask; /* @@ -127,14 +120,12 @@ static int exynos5_uart_err_check(int op) * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -static unsigned char exynos5_uart_rx_byte(void) +static unsigned char exynos5_uart_rx_byte(struct s5p_uart *uart) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for character to arrive */ while (!(readl(&uart->ufstat) & (RX_FIFO_COUNT_MASK | RX_FIFO_FULL_MASK))) { - if (exynos5_uart_err_check(0)) + if (exynos5_uart_err_check(uart, 0)) return 0; } @@ -144,41 +135,48 @@ static unsigned char exynos5_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void exynos5_uart_tx_byte(unsigned char data) +static void exynos5_uart_tx_byte(struct s5p_uart *uart, unsigned char data) { - struct s5p_uart *uart = (struct s5p_uart *)base_port; - /* wait for room in the tx FIFO */ while ((readl(&uart->ufstat) & TX_FIFO_FULL_MASK)) { - if (exynos5_uart_err_check(1)) + if (exynos5_uart_err_check(uart, 1)) return; } writeb(data, &uart->utxh); } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return base_port; + return uart_platform_base(0); } #endif void uart_init(void) { - exynos5_init_dev(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_init_dev(uart); } unsigned char uart_rx_byte(void) { - return exynos5_uart_rx_byte(); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + return exynos5_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - exynos5_uart_tx_byte(data); + struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); + exynos5_uart_tx_byte(uart, data); } void uart_tx_flush(void) { + /* Exynos5250 implements this too. */ } diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index 27051ea..faea640 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -35,10 +35,8 @@ * Initialise the serial port with the given baudrate divisor. The settings * are always 8 data bits, no parity, 1 stop bit, no start bits. */ -static void am335x_uart_init(uint16_t div) +static void am335x_uart_init(struct am335x_uart *uart, uint16_t div) { - struct am335x_uart *uart = (struct am335x_uart *) - CONFIG_CONSOLE_SERIAL_UART_ADDRESS; uint16_t lcr_orig, efr_orig, mcr_orig; /* reset the UART */ @@ -131,11 +129,8 @@ static void am335x_uart_init(uint16_t div) * otherwise. When the function is successful, the character read is * written into its argument c. */ -static unsigned char am335x_uart_rx_byte(void) +static unsigned char am335x_uart_rx_byte(struct am335x_uart *uart) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_RXFIFOE)); return read8(&uart->rhr); @@ -144,11 +139,8 @@ static unsigned char am335x_uart_rx_byte(void) /* * Output a single byte to the serial port. */ -static void am335x_uart_tx_byte(unsigned char data) +static void am335x_uart_tx_byte(struct am335x_uart *uart, unsigned char data) { - struct am335x_uart *uart = - (struct am335x_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS; - while (!(read16(&uart->lsr) & LSR_TXFIFOE)); return write8(data, &uart->thr); @@ -159,28 +151,36 @@ unsigned int uart_platform_refclk(void) return 48000000; } +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; +} + #if !defined(__PRE_RAM__) uint32_t uartmem_getbaseaddr(void) { - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + return uart_platform_base(0); } #endif void uart_init(void) { + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); uint16_t div = (uint16_t) uart_baudrate_divisor( default_baudrate(), uart_platform_refclk(), 16); - am335x_uart_init(div); + am335x_uart_init(uart, div); } unsigned char uart_rx_byte(void) { - return am335x_uart_rx_byte(); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + return am335x_uart_rx_byte(uart); } void uart_tx_byte(unsigned char data) { - am335x_uart_tx_byte(data); + struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); + am335x_uart_tx_byte(uart, data); } void uart_tx_flush(void) diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2202de7..2a37d9d 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -15,12 +15,14 @@ #include <console/uart.h> -static void pl011_uart_tx_byte(unsigned char data) +static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) { - static volatile unsigned int *uart0_address = - (unsigned int *) CONFIG_CONSOLE_SERIAL_UART_ADDRESS; + *uart_base = (unsigned int)data; +} - *uart0_address = (unsigned int)data; +unsigned int uart_platform_base(int idx) +{ + return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } #if !defined(__PRE_RAM__) @@ -36,7 +38,8 @@ void uart_init(void) void uart_tx_byte(unsigned char data) { - pl011_uart_tx_byte(data); + unsigned int *uart_base = (unsigned int *) uart_platform_base(0); + pl011_uart_tx_byte(uart_base, data); } void uart_tx_flush(void)

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Patch set updated for coreboot: 2344b2a console uart: Fill coreboot table entries
by Kyösti Mälkki 04 Mar '14

04 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5310 -gerrit commit 2344b2a8b85df0ff06c30d7e49bc36ab2558c37d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Feb 18 11:54:57 2014 +0200 console uart: Fill coreboot table entries Also fixes the reported baudrate to take get_option() into account. Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/allwinner/a10/uart_console.c | 18 ++++++--- src/cpu/samsung/exynos5250/uart.c | 21 ++++++---- src/cpu/samsung/exynos5420/uart.c | 21 ++++++---- src/cpu/ti/am335x/uart.c | 21 ++++++---- src/drivers/oxford/oxpcie/oxpcie_early.c | 12 +++++- src/drivers/uart/pl011.c | 21 ++++++---- src/drivers/uart/uart8250io.c | 22 +++++++++++ src/include/boot/coreboot_tables.h | 4 ++ src/include/console/uart.h | 1 - src/lib/coreboot_table.c | 66 +++++++++----------------------- 10 files changed, 122 insertions(+), 85 deletions(-) diff --git a/src/cpu/allwinner/a10/uart_console.c b/src/cpu/allwinner/a10/uart_console.c index 5cc1a66..0b80938 100644 --- a/src/cpu/allwinner/a10/uart_console.c +++ b/src/cpu/allwinner/a10/uart_console.c @@ -10,6 +10,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/allwinner/a10/uart.h> @@ -70,14 +71,19 @@ void uart_tx_byte(unsigned char data) a10_uart_tx_blocking(uart_base, data); } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) +void uart_tx_flush(void) { - return uart_platform_base(0); } -#endif -void uart_tx_flush(void) +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) { -} + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5250/uart.c b/src/cpu/samsung/exynos5250/uart.c index 82e221d..5458e7b 100644 --- a/src/cpu/samsung/exynos5250/uart.c +++ b/src/cpu/samsung/exynos5250/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -159,13 +160,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); @@ -189,3 +183,16 @@ void uart_tx_flush(void) struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); exynos5_uart_tx_flush(uart); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/samsung/exynos5420/uart.c b/src/cpu/samsung/exynos5420/uart.c index e3ae88d..0928111 100644 --- a/src/cpu/samsung/exynos5420/uart.c +++ b/src/cpu/samsung/exynos5420/uart.c @@ -19,6 +19,7 @@ #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include "uart.h" #include "clk.h" #include "cpu.h" @@ -151,13 +152,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct s5p_uart *uart = (struct s5p_uart *) uart_platform_base(0); @@ -180,3 +174,16 @@ void uart_tx_flush(void) { /* Exynos5250 implements this too. */ } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/cpu/ti/am335x/uart.c b/src/cpu/ti/am335x/uart.c index faea640..be41653 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/cpu/ti/am335x/uart.c @@ -20,6 +20,7 @@ #include <types.h> #include <console/uart.h> #include <arch/io.h> +#include <boot/coreboot_tables.h> #include <cpu/ti/am335x/uart.h> #define EFR_ENHANCED_EN (1 << 4) @@ -156,13 +157,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return uart_platform_base(0); -} -#endif - void uart_init(void) { struct am335x_uart *uart = (struct am335x_uart *) uart_platform_base(0); @@ -186,3 +180,16 @@ void uart_tx_byte(unsigned char data) void uart_tx_flush(void) { } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index d7f473e..7de9da6 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -24,7 +24,9 @@ #include <arch/io.h> #include <arch/early_variables.h> #include <delay.h> +#include <boot/coreboot_tables.h> #include <console/uart.h> +#include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; @@ -139,9 +141,15 @@ void oxford_remap(u32 new_base) uart1_base = new_base + 0x2000; } -uint32_t uartmem_getbaseaddr(void) +void uart_fill_lb(void *data) { - return uart_platform_base(0); + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); } #endif diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index 2a37d9d..b652f36 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <boot/coreboot_tables.h> #include <console/uart.h> static void pl011_uart_tx_byte(unsigned int *uart_base, unsigned char data) @@ -25,13 +26,6 @@ unsigned int uart_platform_base(int idx) return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; } -#if !defined(__PRE_RAM__) -uint32_t uartmem_getbaseaddr(void) -{ - return CONFIG_CONSOLE_SERIAL_UART_ADDRESS; -} -#endif - void uart_init(void) { } @@ -50,3 +44,16 @@ unsigned char uart_rx_byte(void) { return 0; } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); +} +#endif diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index e4e8b6c..1eebb18 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -23,6 +23,10 @@ #include <trace.h> #include "uart8250reg.h" +#ifndef __ROMCC__ +#include <boot/coreboot_tables.h> +#endif + /* Should support 8250, 16450, 16550, 16550A type UARTs */ /* Nominal values only, good for the range of choices Kconfig offers for @@ -102,6 +106,11 @@ static void uart8250_init(unsigned base_port, unsigned divisor) */ static const unsigned bases[1] = { CONFIG_TTYS0_BASE }; +unsigned int uart_platform_base(int idx) +{ + return bases[idx]; +} + void uart_init(void) { unsigned int div; @@ -129,3 +138,16 @@ void uart_tx_flush(void) { uart8250_tx_flush(bases[0]); } + +#ifndef __PRE_RAM__ +void uart_fill_lb(void *data) +{ + struct lb_serial serial; + serial.type = LB_SERIAL_TYPE_IO_MAPPED; + serial.baseaddr = uart_platform_base(0); + serial.baud = default_baudrate(); + lb_add_serial(&serial, data); + + lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); +} +#endif diff --git a/src/include/boot/coreboot_tables.h b/src/include/boot/coreboot_tables.h index c4ad572..08a89bc 100644 --- a/src/include/boot/coreboot_tables.h +++ b/src/include/boot/coreboot_tables.h @@ -340,4 +340,8 @@ unsigned long write_coreboot_table( void fill_lb_gpios(struct lb_gpios *gpios); +void uart_fill_lb(void *data); +void lb_add_serial(struct lb_serial *serial, void *data); +void lb_add_console(uint16_t consoletype, void *data); + #endif /* COREBOOT_TABLES_H */ diff --git a/src/include/console/uart.h b/src/include/console/uart.h index f0371a2..4516b71 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -46,7 +46,6 @@ unsigned char uart_rx_byte(void); int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); -uint32_t uartmem_getbaseaddr(void); void oxford_init(void); void oxford_remap(unsigned int new_base); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 9bfe34f..e4554d7 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -102,43 +102,22 @@ static struct lb_memory *lb_memory(struct lb_header *header) return mem; } -static struct lb_serial *lb_serial(struct lb_header *header) +void lb_add_serial(struct lb_serial *new_serial, void *data) { -#if CONFIG_CONSOLE_SERIAL8250 - struct lb_record *rec; + struct lb_header *header = (struct lb_header *)data; struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; + + serial = (struct lb_serial *)lb_new_record(header); serial->tag = LB_TAG_SERIAL; serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_IO_MAPPED; - serial->baseaddr = CONFIG_TTYS0_BASE; - serial->baud = CONFIG_TTYS0_BAUD; - return serial; -#elif CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - if (uartmem_getbaseaddr()) { - struct lb_record *rec; - struct lb_serial *serial; - rec = lb_new_record(header); - serial = (struct lb_serial *)rec; - serial->tag = LB_TAG_SERIAL; - serial->size = sizeof(*serial); - serial->type = LB_SERIAL_TYPE_MEMORY_MAPPED; - serial->baseaddr = uartmem_getbaseaddr(); - serial->baud = CONFIG_TTYS0_BAUD; - return serial; - } else { - return NULL; - } -#else - return NULL; -#endif + serial->type = new_serial->type; + serial->baseaddr = new_serial->baseaddr; + serial->baud = new_serial->baud; } -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || \ - CONFIG_CONSOLE_SERIAL_UART || CONFIG_CONSOLE_USB -static void add_console(struct lb_header *header, u16 consoletype) +void lb_add_console(uint16_t consoletype, void *data) { + struct lb_header *header = (struct lb_header *)data; struct lb_console *console; console = (struct lb_console *)lb_new_record(header); @@ -146,20 +125,6 @@ static void add_console(struct lb_header *header, u16 consoletype) console->size = sizeof(*console); console->type = consoletype; } -#endif - -static void lb_console(struct lb_header *header) -{ -#if CONFIG_CONSOLE_SERIAL8250 - add_console(header, LB_TAG_CONSOLE_SERIAL8250); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART - add_console(header, LB_TAG_CONSOLE_SERIAL8250MEM); -#endif -#if CONFIG_CONSOLE_USB - add_console(header, LB_TAG_CONSOLE_EHCI); -#endif -} static void lb_framebuffer(struct lb_header *header) { @@ -423,10 +388,15 @@ unsigned long write_coreboot_table( /* Record our motherboard */ lb_mainboard(head); - /* Record the serial port, if present */ - lb_serial(head); - /* Record our console setup */ - lb_console(head); + + /* Record the serial ports and consoles */ +#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART + uart_fill_lb(head); +#endif +#if CONFIG_CONSOLE_USB + lb_add_console(LB_TAG_CONSOLE_EHCI, head); +#endif + /* Record our various random string information */ lb_strings(head); /* Record our framebuffer */

1 0

Patch set updated for coreboot: af7173f uart: Redefine Kconfig options
by Kyösti Mälkki 04 Mar '14

04 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5311 -gerrit commit af7173f6cbff17af5d983719fb1decef100ba7a3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Feb 13 17:16:22 2014 +0200 uart: Redefine Kconfig options Option DRIVERS_UART builds with support for UART hardware. Option CONSOLE_SERIAL enables the console output for UART. Those x86 boards that do not have serial port on SuperIO should select NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration. Removes: CONSOLE_SERIAL_UART HAVE_UART_IO_MAPPED HAVE_UART_MEMORY_MAPPED Renames: CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/armv7/early_console.c | 4 +-- src/arch/x86/lib/romcc_console.c | 6 ++--- src/arch/x86/lib/romstage_console.c | 10 ++----- src/console/Kconfig | 43 +++++++++++++----------------- src/console/uart_console.c | 2 +- src/cpu/allwinner/a10/Kconfig | 2 +- src/cpu/allwinner/a10/Makefile.inc | 12 ++++----- src/cpu/samsung/exynos5250/Kconfig | 4 +-- src/cpu/samsung/exynos5250/Makefile.inc | 6 ++--- src/cpu/samsung/exynos5420/Kconfig | 4 +-- src/cpu/samsung/exynos5420/Makefile.inc | 6 ++--- src/cpu/ti/am335x/Makefile.inc | 7 +++-- src/cpu/x86/smm/smiutil.c | 10 ++----- src/drivers/Makefile.inc | 2 +- src/drivers/oxford/oxpcie/Kconfig | 2 +- src/drivers/oxford/oxpcie/Makefile.inc | 2 +- src/drivers/uart/Kconfig | 15 ++++++++--- src/drivers/uart/Makefile.inc | 13 ++++----- src/lib/coreboot_table.c | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 2 +- src/mainboard/samsung/lumpy/romstage.c | 4 +-- src/mainboard/samsung/stumpy/romstage.c | 4 +-- src/mainboard/ti/beaglebone/Kconfig | 4 +-- src/superio/via/vt1211/vt1211.c | 2 +- 24 files changed, 79 insertions(+), 89 deletions(-) diff --git a/src/arch/armv7/early_console.c b/src/arch/armv7/early_console.c index 93ea38d..7614531 100644 --- a/src/arch/armv7/early_console.c +++ b/src/arch/armv7/early_console.c @@ -28,7 +28,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_CBMEM && !defined(__BOOT_BLOCK__) @@ -38,7 +38,7 @@ void console_tx_byte(unsigned char byte) static void _console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif } diff --git a/src/arch/x86/lib/romcc_console.c b/src/arch/x86/lib/romcc_console.c index 66c81db..4bd3ad4 100644 --- a/src/arch/x86/lib/romcc_console.c +++ b/src/arch/x86/lib/romcc_console.c @@ -30,7 +30,7 @@ */ #define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO #include "drivers/uart/util.c" #include "drivers/uart/uart8250io.c" #endif @@ -40,7 +40,7 @@ static void __console_tx_byte(unsigned char byte) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K @@ -61,7 +61,7 @@ static void __console_tx_nibble(unsigned nibble) static void __console_tx_char(int loglevel, unsigned char byte) { if (console_loglevel >= loglevel) { -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/arch/x86/lib/romstage_console.c b/src/arch/x86/lib/romstage_console.c index 5e7923e..0337245 100644 --- a/src/arch/x86/lib/romstage_console.c +++ b/src/arch/x86/lib/romstage_console.c @@ -31,10 +31,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif #if CONFIG_CONSOLE_USB && (CONFIG_USBDEBUG_IN_ROMSTAGE || !defined(__PRE_RAM__)) @@ -53,10 +50,7 @@ void console_tx_byte(unsigned char byte) void console_tx_flush(void) { -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_flush(); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_flush(); #endif #if CONFIG_CONSOLE_NE2K diff --git a/src/console/Kconfig b/src/console/Kconfig index bb64f29..9377a78 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -29,37 +29,29 @@ config SQUELCH_EARLY_SMP config CONSOLE_SERIAL bool "Serial port console output" default y + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM || HAVE_UART_SPECIAL help - Send coreboot debug output to a serial port (should be one or more of - CONSOLE_SERIAL8250, CONSOLE_SERIAL8250MEM, CONSOLE_SERIAL_UART) + Send coreboot debug output to a serial port. -config CONSOLE_SERIAL8250 - bool "Serial port console output (I/O mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_IO_MAPPED - default y - help - Send coreboot debug output to an I/O mapped serial port console. + The type of serial port driver selected based on your configuration is + shown on the following menu line. Supporting multiple different types + of UARTs in one build is not supported. -config CONSOLE_SERIAL8250MEM - bool "Serial port console output (memory mapped, 8250-compatible)" - depends on CONSOLE_SERIAL - depends on HAVE_UART_MEMORY_MAPPED - help - Send coreboot debug output to a memory mapped serial port console. +if CONSOLE_SERIAL + + comment "I/O mapped, 8250-compatible" + depends on DRIVERS_UART_8250IO -config CONSOLE_SERIAL_UART - bool "Serial port console output (device-specific UART)" - depends on CONSOLE_SERIAL + comment "memory mapped, 8250-compatible" + depends on DRIVERS_UART_8250MEM + + comment "device-specific UART" depends on HAVE_UART_SPECIAL - default y - help - Send coreboot debug output to a device-specific serial port console. choice prompt "Serial port for 8250" default CONSOLE_SERIAL_COM1 - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO config CONSOLE_SERIAL_COM1 bool "COM1/ttyS0, I/O port 0x3f8" @@ -82,7 +74,7 @@ endchoice config TTYS0_BASE hex - depends on CONSOLE_SERIAL8250 + depends on DRIVERS_UART_8250IO default 0x3f8 if CONSOLE_SERIAL_COM1 default 0x2f8 if CONSOLE_SERIAL_COM2 default 0x3e8 if CONSOLE_SERIAL_COM3 @@ -93,7 +85,6 @@ config TTYS0_BASE choice prompt "Baud rate" default CONSOLE_SERIAL_115200 - depends on CONSOLE_SERIAL config CONSOLE_SERIAL_115200 bool "115200" @@ -133,7 +124,9 @@ config TTYS0_BAUD config TTYS0_LCS int default 3 - depends on CONSOLE_SERIAL8250 || CONSOLE_SERIAL8250MEM + depends on DRIVERS_UART_8250IO || DRIVERS_UART_8250MEM + +endif # CONSOLE_SERIAL config SPKMODEM bool "spkmodem (console on speaker) console output" diff --git a/src/console/uart_console.c b/src/console/uart_console.c index e2cd6a8..f5535d7 100644 --- a/src/console/uart_console.c +++ b/src/console/uart_console.c @@ -43,7 +43,7 @@ static unsigned char uartmem_rx_byte(void) /* This only relevant with x86 with GDB_STUB enabled.*/ static int uartmem_tst_byte(void) { -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_DRIVERS_UART_8250IO || CONFIG_DRIVERS_UART_8250MEM return uart_can_rx_byte(); #else return 0; diff --git a/src/cpu/allwinner/a10/Kconfig b/src/cpu/allwinner/a10/Kconfig index 72e3630..8512c38 100644 --- a/src/cpu/allwinner/a10/Kconfig +++ b/src/cpu/allwinner/a10/Kconfig @@ -76,7 +76,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index a86d719..716e463 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -4,8 +4,6 @@ bootblock-y += gpio.c bootblock-y += pinmux.c bootblock-y += raminit.c bootblock-y += timer.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c -bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c romstage-y += cbmem.c @@ -13,8 +11,6 @@ romstage-y += clock.c romstage-y += pinmux.c romstage-y += timer.c romstage-y += twi.c -romstage-y += uart.c -romstage-y += uart_console.c ramstage-y += bootblock_media.c ramstage-y += cbmem.c @@ -23,8 +19,12 @@ ramstage-y += cpu.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c -ramstage-y += uart.c -ramstage-y += uart_console.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c uart_console.c +romstage-y += uart.c uart_console.c +ramstage-y += uart.c uart_console.c +endif real-target: $(obj)/BOOT0 diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 63038c3..9320184 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -91,7 +91,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -117,7 +117,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5250/Makefile.inc b/src/cpu/samsung/exynos5250/Makefile.inc index 6d7ae16..3d5b5b4 100644 --- a/src/cpu/samsung/exynos5250/Makefile.inc +++ b/src/cpu/samsung/exynos5250/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index dd35c35..5f78cc5 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -93,7 +93,7 @@ config SYS_SDRAM_BASE choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART3 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -119,7 +119,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x12c00000 if CONSOLE_SERIAL_UART0 default 0x12c10000 if CONSOLE_SERIAL_UART1 default 0x12c20000 if CONSOLE_SERIAL_UART2 diff --git a/src/cpu/samsung/exynos5420/Makefile.inc b/src/cpu/samsung/exynos5420/Makefile.inc index 4169a2e..844b835 100644 --- a/src/cpu/samsung/exynos5420/Makefile.inc +++ b/src/cpu/samsung/exynos5420/Makefile.inc @@ -9,7 +9,7 @@ bootblock-y += pinmux.c mct.c power.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock_init.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += clock.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif bootblock-y += wakeup.c @@ -25,7 +25,7 @@ romstage-y += dmc_init_ddr3.c romstage-y += power.c romstage-y += mct.c romstage-y += monotonic_timer.c -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) +ifeq ($(CONFIG_DRIVERS_UART),y) romstage-$(CONFIG_EARLY_CONSOLE) += uart.c endif romstage-y += wakeup.c @@ -40,7 +40,7 @@ ramstage-y += clock.c ramstage-y += clock_init.c ramstage-y += pinmux.c ramstage-y += power.c -ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c +ramstage-$(CONFIG_DRIVERS_UART) += uart.c ramstage-y += cpu.c ramstage-y += tmu.c ramstage-y += mct.c diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/cpu/ti/am335x/Makefile.inc index ff00733..5b10bd8 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/cpu/ti/am335x/Makefile.inc @@ -1,16 +1,19 @@ bootblock-y += dmtimer.c bootblock-y += bootblock_media.c bootblock-y += pinmux.c -bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c romstage-y += nand.c -romstage-y += uart.c ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c ramstage-y += timer.c + +ifeq ($(CONFIG_DRIVERS_UART),y) +bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c +romstage-y += uart.c ramstage-y += uart.c +endif $(call add-class,omap-header) diff --git a/src/cpu/x86/smm/smiutil.c b/src/cpu/x86/smm/smiutil.c index 3325c32..6e9822e 100644 --- a/src/cpu/x86/smm/smiutil.c +++ b/src/cpu/x86/smm/smiutil.c @@ -32,10 +32,7 @@ void console_tx_byte(unsigned char byte) if (byte == '\n') console_tx_byte('\r'); -#if CONFIG_CONSOLE_SERIAL8250MEM - uart_tx_byte(byte); -#endif -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL uart_tx_byte(byte); #endif } @@ -45,10 +42,7 @@ void console_init(void) { #if CONFIG_DEBUG_SMI console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#if CONFIG_CONSOLE_SERIAL8250 - uart_init(); -#endif -#if CONFIG_CONSOLE_SERIAL8250MEM +#if CONFIG_CONSOLE_SERIAL uart_init(); #endif #endif diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 197a900..148e257 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -30,7 +30,7 @@ subdirs-y += parade subdirs-y += realtek subdirs-y += sil subdirs-y += trident -subdirs-y += uart +subdirs-$(CONFIG_DRIVERS_UART) += uart subdirs-y += usb subdirs-y += ics subdirs-y += spi diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 899a153..5ad42aa 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,7 +1,7 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n - select HAVE_UART_MEMORY_MAPPED + select DRIVERS_UART_8250MEM help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID diff --git a/src/drivers/oxford/oxpcie/Makefile.inc b/src/drivers/oxford/oxpcie/Makefile.inc index 1922425..5e3e6e5 100644 --- a/src/drivers/oxford/oxpcie/Makefile.inc +++ b/src/drivers/oxford/oxpcie/Makefile.inc @@ -1,4 +1,4 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_CONSOLE_SERIAL),y) ramstage-y += oxpcie_early.c oxpcie.c romstage-y += oxpcie_early.c endif diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index 5c9a9d1..889c69a 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -1,10 +1,19 @@ -# This should default to N and be set by SuperI/O drivers that have an UART -config HAVE_UART_IO_MAPPED +config DRIVERS_UART bool + default y if CONSOLE_SERIAL + default n + +config DRIVERS_UART_8250IO + bool "Serial port on SuperIO" depends on !ARCH_ARMV7 + default n if NO_UART_ON_SUPERIO default y if ARCH_X86 -config HAVE_UART_MEMORY_MAPPED +# Select this for mainboard without SuperIO serial port. +config NO_UART_ON_SUPERIO + def_bool n + +config DRIVERS_UART_8250MEM bool default n diff --git a/src/drivers/uart/Makefile.inc b/src/drivers/uart/Makefile.inc index 415c5bb..286bff2 100644 --- a/src/drivers/uart/Makefile.inc +++ b/src/drivers/uart/Makefile.inc @@ -1,28 +1,25 @@ -ifeq ($(CONFIG_CONSOLE_SERIAL),y) romstage-y += util.c ramstage-y += util.c bootblock-y += util.c smm-$(CONFIG_DEBUG_SMI) += util.c -endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250),y) +# Add the driver, only one can be enabled. The driver files may +# be located in the soc/ or cpu/ directories instead of here. + +ifeq ($(CONFIG_DRIVERS_UART_8250IO),y) romstage-y += uart8250io.c ramstage-y += uart8250io.c smm-$(CONFIG_DEBUG_SMI) += uart8250io.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y) +ifeq ($(CONFIG_DRIVERS_UART_8250MEM),y) romstage-y += uart8250mem.c ramstage-y += uart8250mem.c smm-$(CONFIG_DEBUG_SMI) += uart8250mem.c endif -ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) - ifeq ($(CONFIG_DRIVERS_UART_PL011),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += pl011.c romstage-$(CONFIG_EARLY_CONSOLE) += pl011.c ramstage-y += pl011.c endif - -endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index e4554d7..8e7f85d 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -390,7 +390,7 @@ unsigned long write_coreboot_table( lb_mainboard(head); /* Record the serial ports and consoles */ -#if CONFIG_CONSOLE_SERIAL8250 || CONFIG_CONSOLE_SERIAL8250MEM || CONFIG_CONSOLE_SERIAL_UART +#if CONFIG_CONSOLE_SERIAL uart_fill_lb(head); #endif #if CONFIG_CONSOLE_USB diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index edba627..040ed9c 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -50,7 +50,7 @@ config DRAM_SIZE_MB config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x10009000 # Memory map for qemu vexpress-a9: diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 9933459..55c1f0a 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/msr.h> #include "option_table.h" #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -53,7 +53,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + EC + KBC + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index e5b55b5..3e27a6a 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -40,7 +40,7 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include "gpio.h" -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO #include "superio/smsc/lpc47n207/lpc47n207.h" #include "superio/smsc/lpc47n207/early_serial.c" #endif @@ -62,7 +62,7 @@ static void pch_enable_lpc(void) /* Set COM1/COM2 decode range */ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010); -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_DRIVERS_UART_8250IO /* Enable SuperIO + PS/2 Keyboard/Mouse + COM1 + lpc47n207 config*/ pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN | KBC_LPC_EN |\ CNF2_LPC_EN | COMA_LPC_EN); diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index df7ebeb..c842a5d 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -64,7 +64,7 @@ config CBFS_HEADER_ROM_OFFSET choice CONSOLE_SERIAL_UART_CHOICES prompt "Serial Console UART" default CONSOLE_SERIAL_UART0 - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL config CONSOLE_SERIAL_UART0 bool "UART0" @@ -100,7 +100,7 @@ endchoice config CONSOLE_SERIAL_UART_ADDRESS hex - depends on CONSOLE_SERIAL_UART + depends on CONSOLE_SERIAL default 0x44e09000 if CONSOLE_SERIAL_UART0 default 0x48022000 if CONSOLE_SERIAL_UART1 default 0x48024000 if CONSOLE_SERIAL_UART2 diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/vt1211.c index 551f6f0..f7a5cd9 100644 --- a/src/superio/via/vt1211/vt1211.c +++ b/src/superio/via/vt1211/vt1211.c @@ -117,7 +117,7 @@ static void vt1211_pnp_set_resources(struct device *dev) { struct resource *res; -#if CONFIG_CONSOLE_SERIAL8250 +#if CONFIG_CONSOLE_SERIAL && CONFIG_DRIVERS_UART_8250IO /* TODO: Do the same for SP2? */ if (dev->path.pnp.device == VT1211_SP1) { for (res = dev->resource_list; res; res = res->next) {

1 0

Patch set updated for coreboot: d682ff7 OxPCIe uart: Split PCI bridge control
by Kyösti Mälkki 04 Mar '14

04 Mar '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/5237 -gerrit commit d682ff7aec91780ec7c9c23aed3551bee283e649 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Feb 14 12:45:09 2014 +0200 OxPCIe uart: Split PCI bridge control None of the bridge management here is specific to the PCI UART device/function. Also the Kconfig variable defaults are not globally valid but originate from lumpy and/or stumpy devices. Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/console/console.c | 5 +- src/device/Kconfig | 29 ++++++++ src/device/Makefile.inc | 1 + src/device/pci_early.c | 115 +++++++++++++++++++++++++++++++ src/drivers/oxford/oxpcie/Kconfig | 64 +---------------- src/drivers/oxford/oxpcie/oxpcie_early.c | 89 +++++------------------- src/include/console/uart.h | 1 - src/include/device/pci.h | 2 + src/southbridge/intel/bd82x6x/Kconfig | 16 +++++ 9 files changed, 187 insertions(+), 135 deletions(-) diff --git a/src/console/console.c b/src/console/console.c index 9e9e4e2..3eedb84 100644 --- a/src/console/console.c +++ b/src/console/console.c @@ -27,6 +27,7 @@ #include <build.h> #include <arch/hlt.h> #include <arch/io.h> +#include <device/pci.h> #ifndef __PRE_RAM__ #include <string.h> @@ -101,8 +102,8 @@ void console_init(void) #if defined(__BOOT_BLOCK__) && CONFIG_BOOTBLOCK_CONSOLE || \ !defined(__BOOT_BLOCK__) && CONFIG_EARLY_CONSOLE -#if CONFIG_DRIVERS_OXFORD_OXPCIE - oxford_init(); +#if CONFIG_EARLY_PCI_BRIDGE + pci_early_bridge_init(); #endif #if CONFIG_CONSOLE_SERIAL uart_init(); diff --git a/src/device/Kconfig b/src/device/Kconfig index eaa0c04..932b4de 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -237,6 +237,35 @@ config PCIEXP_ASPM config PCI_BUS_SEGN_BITS int default 0 + +config EARLY_PCI_BRIDGE + bool "Early PCI bridge" + depends on PCI + default n + help + While coreboot is executing code from ROM, the coreboot resource + allocator has not been running yet. Hence PCI devices living behind + a bridge are not yet visible to the system. + + This option enables static configuration for a single pre-defined + PCI bridge function on bus 0. + +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex "bridge device" + default 0x0 + +config EARLY_PCI_BRIDGE_FUNCTION + hex "bridge function" + default 0x0 + +config EARLY_PCI_MMIO_BASE + hex "MMIO window base" + default 0x0 + +endif # EARLY_PCI_BRIDGE + endmenu menu "VGA BIOS" diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index ce412b7..bd41b12 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -11,6 +11,7 @@ ramstage-$(CONFIG_CARDBUS_PLUGIN_SUPPORT) += cardbus_device.c ramstage-$(CONFIG_AZALIA_PLUGIN_SUPPORT) += azalia_device.c ramstage-$(CONFIG_ARCH_X86) += pnp_device.c ramstage-$(CONFIG_PCI) += pci_ops.c +ramstage-$(CONFIG_PCI) += pci_early.c ramstage-y += smbus_ops.c romstage-y += device_romstage.c diff --git a/src/device/pci_early.c b/src/device/pci_early.c index c15a4d0..627e5ac 100644 --- a/src/device/pci_early.c +++ b/src/device/pci_early.c @@ -1,6 +1,8 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2011 Google Inc + * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; version 2 of the License. @@ -15,9 +17,14 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA */ +#define __SIMPLE_DEVICE__ + #include <arch/io.h> #include <device/pci.h> #include <device/pci_def.h> +#include <delay.h> + +#ifdef __PRE_RAM__ unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last) { @@ -66,3 +73,111 @@ unsigned pci_find_capability(device_t dev, unsigned cap) { return pci_find_next_capability(dev, cap, 0); } +#endif + + +#if CONFIG_EARLY_PCI_BRIDGE + +static void pci_bridge_reset_secondary(device_t p2p_bridge) +{ + u16 reg16; + /* Disable all access through bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + + /* First we reset the secondary bus. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 |= (1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); + + /* Assume we don't have to wait here forever */ + + /* Read back and clear reset bit. */ + reg16 = pci_read_config16(p2p_bridge, PCI_BRIDGE_CONTROL); + reg16 &= ~(1 << 6); /* SRESET */ + pci_write_config16(p2p_bridge, PCI_BRIDGE_CONTROL, reg16); +} + +static void pci_bridge_set_secondary(device_t p2p_bridge, u8 secondary) +{ + /* Disable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, 0x00); + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, 0x00); + /* Enable config transaction forwarding. */ + pci_write_config8(p2p_bridge, PCI_SECONDARY_BUS, secondary); + pci_write_config8(p2p_bridge, PCI_SUBORDINATE_BUS, secondary); +} + +static void pci_bridge_set_mmio(device_t p2p_bridge, u32 base, u32 size) +{ + u16 reg16; + + /* Disable MMIO window behind the bridge. */ + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, 0x10); + + if (!size) + return; + + /* Enable MMIO window behind the bridge. */ + pci_write_config32(p2p_bridge, PCI_MEMORY_BASE, + ((base + size - 1) & 0xfff00000) | ((base >> 16) & 0xfff0)); + + reg16 = pci_read_config16(p2p_bridge, PCI_COMMAND); + reg16 |= PCI_COMMAND_MEMORY; + pci_write_config16(p2p_bridge, PCI_COMMAND, reg16); +} + +void pci_early_bridge_init(void) +{ + int timeout, ret = -1; + + /* No PCI-to-PCI bridges are enabled yet, so the one we try to + * configure must have its primary on bus 0. + */ + pci_devfn_t p2p_bridge = PCI_DEV(0, CONFIG_EARLY_PCI_BRIDGE_DEVICE, + CONFIG_EARLY_PCI_BRIDGE_FUNCTION); + + /* Secondary bus number is mostly irrelevant as we disable + * configuration transactions right after the probe. + */ + u8 secondary = 15; + u8 dev = 0; + u32 mmio_base = CONFIG_EARLY_PCI_MMIO_BASE; + + /* Enable configuration and MMIO over bridge. */ + pci_bridge_reset_secondary(p2p_bridge); + pci_bridge_set_secondary(p2p_bridge, secondary); + pci_bridge_set_mmio(p2p_bridge, mmio_base, 0x4000); + + for (timeout = 20000; timeout && (dev < 32) && ret; timeout--) { + u32 id = pci_read_config32(PCI_DEV(secondary, dev, 0), PCI_VENDOR_ID); + + /* Retry request. */ + if (id == 0xffff0001) { + udelay(10); + continue; + } + + /* Empty slot. */ + if (id == 0xffffffff || id == 0) { + dev++; + continue; + } + ret = pci_early_device_probe(secondary, dev, mmio_base); + } + + /* Disable MMIO window if we found no suitable device. */ + if (ret) + pci_bridge_set_mmio(p2p_bridge, 0, 0); + + /* Resource allocator will reconfigure bridges and secondary bus + * number may change. Thus early device cannot reliably use config + * transactions from here on, so we may as well disable them. + */ + pci_bridge_set_secondary(p2p_bridge, 0); +} +#endif /* CONFIG_EARLY_PCI_BRIDGE */ diff --git a/src/drivers/oxford/oxpcie/Kconfig b/src/drivers/oxford/oxpcie/Kconfig index 5ad42aa..c2ea7b6 100644 --- a/src/drivers/oxford/oxpcie/Kconfig +++ b/src/drivers/oxford/oxpcie/Kconfig @@ -1,68 +1,10 @@ config DRIVERS_OXFORD_OXPCIE bool "Oxford OXPCIe952" default n + depends on PCI select DRIVERS_UART_8250MEM + select EARLY_PCI_BRIDGE help Support for Oxford OXPCIe952 serial port PCIe cards. Currently only devices with the vendor ID 0x1415 and device ID - 0xc158 will work. - NOTE: Right now you have to set the base address of your OXPCIe952 - card to exactly the value that the device allocator would set them - later on, or serial console functionality will stop as soon as the - resource allocator assigns a new base address to the device. - -config OXFORD_OXPCIE_BRIDGE_BUS - hex "OXPCIe's PCIe bridge bus number" - default 0x0 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_DEVICE - hex "OXPCIe's PCIe bridge device number" - default 0x1c - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_FUNCTION - hex "OXPCIe's PCIe bridge function number" - default 0x2 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BRIDGE_SUBORDINATE - hex "OXPCIe's PCIe bridge subordinate bus" - default 0x3 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up the PCIe bridge - that controls the OXPCIe952 controller first. - -config OXFORD_OXPCIE_BASE_ADDRESS - hex "Base address for rom stage console" - default 0xe0400000 - depends on DRIVERS_OXFORD_OXPCIE - help - While coreboot is executing code from ROM, the coreboot resource - allocator has not been running yet. Hence PCI devices living behind - a bridge are not yet visible to the system. In order to use an - OXPCIe952 based PCIe card, coreboot has to set up a temporary address - for the OXPCIe952 controller. - + 0xc158 or 0xc11b will work. diff --git a/src/drivers/oxford/oxpcie/oxpcie_early.c b/src/drivers/oxford/oxpcie/oxpcie_early.c index 7de9da6..b81fa89 100644 --- a/src/drivers/oxford/oxpcie/oxpcie_early.c +++ b/src/drivers/oxford/oxpcie/oxpcie_early.c @@ -23,101 +23,53 @@ #include <stddef.h> #include <arch/io.h> #include <arch/early_variables.h> -#include <delay.h> #include <boot/coreboot_tables.h> #include <console/uart.h> #include <device/pci.h> #include <device/pci_def.h> static unsigned int oxpcie_present CAR_GLOBAL; -static ROMSTAGE_CONST u32 uart0_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x1000; -static ROMSTAGE_CONST u32 uart1_base = CONFIG_OXFORD_OXPCIE_BASE_ADDRESS + 0x2000; +static ROMSTAGE_CONST u32 uart0_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x1000; +static ROMSTAGE_CONST u32 uart1_base = CONFIG_EARLY_PCI_MMIO_BASE + 0x2000; -#define PCIE_BRIDGE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_BUS, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_DEVICE, \ - CONFIG_OXFORD_OXPCIE_BRIDGE_FUNCTION) - -#define OXPCIE_DEVICE \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 0) - -#define OXPCIE_DEVICE_3 \ - PCI_DEV(CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE, 0, 3) - -static void oxpcie_init_bridge(void) +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base) { - u16 reg16; - - /* First we reset the secondary bus */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 |= (1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Assume we don't have to wait here forever */ + pci_devfn_t device = PCI_DEV(bus, dev, 0); - /* Read back and clear reset bit. */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL); - reg16 &= ~(1 << 6); /* SRESET */ - pci_write_config16(PCIE_BRIDGE, PCI_BRIDGE_CONTROL, reg16); - - /* Set up subordinate bus number */ - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, 0x00); - pci_write_config8(PCIE_BRIDGE, PCI_SECONDARY_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - pci_write_config8(PCIE_BRIDGE, PCI_SUBORDINATE_BUS, - CONFIG_OXFORD_OXPCIE_BRIDGE_SUBORDINATE); - - /* Memory window for the OXPCIe952 card */ - // XXX is the calculation of base and limit correct? - pci_write_config32(PCIE_BRIDGE, PCI_MEMORY_BASE, - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS & 0xffff0000) | - ((CONFIG_OXFORD_OXPCIE_BASE_ADDRESS >> 16) & 0xff00))); - - /* Enable memory access through bridge */ - reg16 = pci_read_config16(PCIE_BRIDGE, PCI_COMMAND); - reg16 |= PCI_COMMAND_MEMORY; - pci_write_config16(PCIE_BRIDGE, PCI_COMMAND, reg16); - - u32 timeout = 20000; // Timeout in 10s of microseconds. - u32 id = 0; - for (;;) { - id = pci_read_config32(OXPCIE_DEVICE, PCI_VENDOR_ID); - if (!timeout-- || (id != 0 && id != 0xffffffff)) - break; - udelay(10); - } - - u32 device = OXPCIE_DEVICE; /* unknown default */ + u32 id = pci_read_config32(device, PCI_VENDOR_ID); switch (id) { - case 0xc1181415: /* e.g. Startech PEX1S1PMINI */ + case 0xc1181415: /* e.g. Startech PEX1S1PMINI function 0 */ /* On this device function 0 is the parallel port, and * function 3 is the serial port. So let's go look for * the UART. */ - id = pci_read_config32(OXPCIE_DEVICE_3, PCI_VENDOR_ID); + device = PCI_DEV(bus, dev, 3); + id = pci_read_config32(device, PCI_VENDOR_ID); if (id != 0xc11b1415) - return; - device = OXPCIE_DEVICE_3; + return -1; break; + case 0xc11b1415: /* e.g. Startech PEX1S1PMINI function 3 */ case 0xc1581415: /* e.g. Startech MPEX2S952 */ - device = OXPCIE_DEVICE; break; default: /* No UART here. */ - return; + return -1; } + /* Sanity-check, we assume fixed location. */ + if (mmio_base != CONFIG_EARLY_PCI_MMIO_BASE) + return -1; + /* Setup base address on device */ - pci_write_config32(device, PCI_BASE_ADDRESS_0, - CONFIG_OXFORD_OXPCIE_BASE_ADDRESS); + pci_write_config32(device, PCI_BASE_ADDRESS_0, mmio_base); /* Enable memory on device */ - reg16 = pci_read_config16(device, PCI_COMMAND); + u16 reg16 = pci_read_config16(device, PCI_COMMAND); reg16 |= PCI_COMMAND_MEMORY; pci_write_config16(device, PCI_COMMAND, reg16); car_set_var(oxpcie_present, 1); + return 0; } static int oxpcie_uart_active(void) @@ -157,8 +109,3 @@ unsigned int uart_platform_refclk(void) { return 62500000; } - -void oxford_init(void) -{ - oxpcie_init_bridge(); -} diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 4516b71..7d92a21 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -47,7 +47,6 @@ int uart_can_rx_byte(void); unsigned int uart_platform_base(int idx); -void oxford_init(void); void oxford_remap(unsigned int new_base); #endif /* CONSOLE_UART_H */ diff --git a/src/include/device/pci.h b/src/include/device/pci.h index 29d988f..f729c27 100644 --- a/src/include/device/pci.h +++ b/src/include/device/pci.h @@ -102,6 +102,8 @@ static inline const struct pci_operations *ops_pci(device_t dev) unsigned pci_find_next_capability(device_t dev, unsigned cap, unsigned last); unsigned pci_find_capability(device_t dev, unsigned cap); +void pci_early_bridge_init(void); +int pci_early_device_probe(u8 bus, u8 dev, u32 mmio_base); #endif /* CONFIG_PCI */ diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index 9cfa5d5..14281e6 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -41,6 +41,22 @@ config EHCI_BAR hex default 0xfef00000 +if EARLY_PCI_BRIDGE + +config EARLY_PCI_BRIDGE_DEVICE + hex + default 0x1c + +config EARLY_PCI_BRIDGE_FUNCTION + hex + default 0x2 + +config EARLY_PCI_MMIO_BASE + hex + default 0xe0400000 + +endif + config DRAM_RESET_GATE_GPIO int default 60

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Patch set updated for coreboot: 0870766 baytrail: add ccu iosf access functions
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4927 -gerrit commit 087076680be3f4470a650db7401a65016a0eaf28 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 1 14:19:24 2013 -0500 baytrail: add ccu iosf access functions The clock control unit needs to be accessed to configure some of the devices properly. Therefore. provide a way to access the CCU. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built. Change-Id: I30ed06e6aef81ee99c6d7ab3cbe8f83818b8dee5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175492 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iosf.h | 18 ++++++++++++++++++ src/soc/intel/baytrail/iosf.c | 14 ++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iosf.h b/src/soc/intel/baytrail/baytrail/iosf.h index 9b59fbc..83e03a5 100644 --- a/src/soc/intel/baytrail/baytrail/iosf.h +++ b/src/soc/intel/baytrail/baytrail/iosf.h @@ -70,6 +70,8 @@ uint32_t iosf_ushphy_read(int reg); void iosf_ushphy_write(int reg, uint32_t val); uint32_t iosf_lpss_read(int reg); void iosf_lpss_write(int reg, uint32_t val); +uint32_t iosf_ccu_read(int reg); +void iosf_ccu_write(int reg, uint32_t val); /* IOSF ports. */ #define IOSF_PORT_AUNIT 0x00 /* IO Arbiter unit */ @@ -86,6 +88,7 @@ void iosf_lpss_write(int reg, uint32_t val); #define IOSF_PORT_LPSS 0xa0 /* LPSS - Low Power Subsystem */ #define IOSF_PORT_SATAPHY 0xa3 /* SATA PHY */ #define IOSF_PORT_PCIEPHY 0xa3 /* PCIE PHY */ +#define IOSF_PORT_CCU 0xa9 /* Clock control unit. */ /* Read and write opcodes differ per port. */ #define IOSF_OP_READ_AUNIT 0x10 @@ -112,6 +115,8 @@ void iosf_lpss_write(int reg, uint32_t val); #define IOSF_OP_WRITE_SATAPHY (IOSF_OP_READ_SATAPHY | 1) #define IOSF_OP_READ_PCIEPHY 0x00 #define IOSF_OP_WRITE_PCIEPHY (IOSF_OP_READ_PCIEPHY | 1) +#define IOSF_OP_READ_CCU 0x06 +#define IOSF_OP_WRITE_CCU (IOSF_OP_READ_CCU | 1) /* @@ -195,5 +200,18 @@ void iosf_lpss_write(int reg, uint32_t val); # define LPSS_CTL_NOSNOOP (1 << 19) # define LPSS_CTL_PM_CAP_PRSNT (1 << 1) +/* + * CCU Registers + */ + +#define PLT_CLK_CTRL_0 0x3c +#define PLT_CLK_CTRL_1 0x40 +#define PLT_CLK_CTRL_2 0x44 +#define PLT_CLK_CTRL_3 0x48 +#define PLT_CLK_CTRL_4 0x4c +#define PLT_CLK_CTRL_5 0x50 +# define PLT_CLK_CTRL_19P2MHZ_FREQ (0 << 1) +# define PLT_CLK_CTRL_25MHZ_FREQ (1 << 1) +# define PLT_CLK_CTRL_SELECT_FREQ (1 << 0) #endif /* _BAYTRAIL_IOSF_H_ */ diff --git a/src/soc/intel/baytrail/iosf.c b/src/soc/intel/baytrail/iosf.c index a7f7a90..7e0dacb 100644 --- a/src/soc/intel/baytrail/iosf.c +++ b/src/soc/intel/baytrail/iosf.c @@ -154,3 +154,17 @@ void iosf_lpss_write(int reg, uint32_t val) IOSF_PORT(IOSF_PORT_LPSS); return iosf_write_port(cr, reg, val); } + +uint32_t iosf_ccu_read(int reg) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_CCU) | + IOSF_PORT(IOSF_PORT_CCU); + return iosf_read_port(cr, reg); +} + +void iosf_ccu_write(int reg, uint32_t val) +{ + uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_CCU) | + IOSF_PORT(IOSF_PORT_CCU); + return iosf_write_port(cr, reg, val); +}

1 0

Patch set updated for coreboot: 64a23d6 baytrail: HDA function disable workaround
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4926 -gerrit commit 64a23d670690b2e30d2fa458fbf882d6e94a9a04 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 17:07:46 2013 -0500 baytrail: HDA function disable workaround Parts of the audio path are common between the HDA and LPE. However, those parts are power-controlled by the D-state of the HDA device. Therefore, one cannot put the HDA into D3Hot because those audio paths will be shutdown. BUG=chrome-os-partner:22871 BRANCH=None TEST=Built and booted through depthcharge. Disabling HDA still causes a shutdown when performing warm reset, however I was able to verify the magic sequence was being performed. Change-Id: I3b01356d85a4b7b902bd896b8eb9e7bc509fcc42 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175491 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/baytrail/iomap.h | 1 + src/soc/intel/baytrail/southcluster.c | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+) diff --git a/src/soc/intel/baytrail/baytrail/iomap.h b/src/soc/intel/baytrail/baytrail/iomap.h index fa34105..d46a0fe 100644 --- a/src/soc/intel/baytrail/baytrail/iomap.h +++ b/src/soc/intel/baytrail/baytrail/iomap.h @@ -31,6 +31,7 @@ #define PUNIT_BASE_ADDRESS 0xfed05000 #define RCBA_BASE_ADDRESS 0xfed1c000 #define HPET_BASE_ADDRESS 0xfed00000 +#define TEMP_BASE_ADDRESS 0xfd000000 /* IO Port base */ #define ACPI_BASE_ADDRESS 0x0400 diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 42349fa..c71ab7e 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -238,10 +238,37 @@ static inline void set_d3hot_bits(device_t dev, int offset) pci_write_config8(dev, offset + 4, reg8); } +/* Parts of the audio subsystem are powered by the HDA device. Therefore, one + * cannot put HDA into D3Hot. Instead perform this workaround to make some of + * the audio paths work for LPE audio. */ +static void hda_work_around(device_t dev) +{ + unsigned long gctl = TEMP_BASE_ADDRESS + 0x8; + + /* Need to set magic register 0x43 to 0xd7 in config space. */ + pci_write_config8(dev, 0x43, 0xd7); + + /* Need to set bit 0 of GCTL to take the device out of reset. However, + * that requires setting up the 64-bit BAR. */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, TEMP_BASE_ADDRESS); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); + write32(gctl, read32(gctl) | 0x1); + pci_write_config8(dev, PCI_COMMAND, 0); + pci_write_config32(dev, PCI_BASE_ADDRESS_0, 0); +} + static int place_device_in_d3hot(device_t dev) { unsigned offset; + /* Parts of the HDA block are used for LPE audio as well. + * Therefore assume the HDA will never be put into D3Hot. */ + if (dev->path.pci.devfn == PCI_DEVFN(HDA_DEV, HDA_FUNC)) { + hda_work_around(dev); + return 0; + } + offset = pci_find_capability(dev, PCI_CAP_ID_PM); if (offset != 0) {

1 0

Patch set updated for coreboot: 41dead2 baytrail: allow function disable on TXE
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4925 -gerrit commit 41dead2a123f6700a55dfcc1141769855c4e35c9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Oct 30 17:08:59 2013 -0500 baytrail: allow function disable on TXE Previously it was not known how to put the TXE pci device into D3Hot. It's been disseminated that this is not a requirement for disabling the TXE pci device in the function disable register. Therefore, allow this by returning 0 from place_device_in_d3hot(). BUG=chrome-os-partner:22871 BRANCH=None TEST=Temporarily set TXE to be disabled. Noted FUNC_DIS was being set accordingly. Change-Id: Ibf537bf8ba718859591dc89bdf41e57c1ea9d836 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175490 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/southcluster.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index eacabf3..42349fa 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -322,7 +322,8 @@ static int place_device_in_d3hot(device_t dev) offset = 0x50; break; case PCI_DEVFN(TXE_DEV, TXE_FUNC): - break; + /* TXE cannot be placed in D3Hot. */ + return 0; case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): offset = 0xa0; break;

1 0

Patch set updated for coreboot: c6d206f baytrail: Switch graphics init to use reg_script
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4924 -gerrit commit c6d206f39ba85839787ab7d28c1ff7c033e6b886 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Oct 31 08:27:29 2013 -0700 baytrail: Switch graphics init to use reg_script This is an example consumer of the register script handler. BUG=chrome-os-partner:23507 BRANCH=rambi TEST=build and boot on rambi and see recovery screen Change-Id: I4954a5defd0a345b179819b9f6bb15ea340a6715 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175214 Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Tested-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/gfx.c | 461 ++++++++++++++++++------------------------- 1 file changed, 190 insertions(+), 271 deletions(-) diff --git a/src/soc/intel/baytrail/gfx.c b/src/soc/intel/baytrail/gfx.c index 09cd662..28b73d5 100644 --- a/src/soc/intel/baytrail/gfx.c +++ b/src/soc/intel/baytrail/gfx.c @@ -23,186 +23,14 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include <reg_script.h> #include <baytrail/gfx.h> #include <baytrail/iosf.h> #include <baytrail/pci_devs.h> #include <baytrail/ramstage.h> -struct gt_reg { - u32 reg; - u32 andmask; - u32 ormask; -}; - -static const struct gt_reg gfx_powermeter_weights[] = { - /* SET1 */ - { 0xA800, 0xFFFFFFFF, 0x00000000 }, - { 0xA804, 0xFFFFFFFF, 0x00000000 }, - { 0xA808, 0xFFFFFFFF, 0x0000ff0A }, - { 0xA80C, 0xFFFFFFFF, 0x1D000000 }, - { 0xA810, 0xFFFFFFFF, 0xAC004900 }, - { 0xA814, 0xFFFFFFFF, 0x000F0000 }, - { 0xA818, 0xFFFFFFFF, 0x5A000000 }, - { 0xA81C, 0xFFFFFFFF, 0x2600001F }, - { 0xA820, 0xFFFFFFFF, 0x00090000 }, - { 0xA824, 0xFFFFFFFF, 0x2000ff00 }, - { 0xA828, 0xFFFFFFFF, 0xff090016 }, - { 0xA82C, 0xFFFFFFFF, 0x00000000 }, - { 0xA830, 0xFFFFFFFF, 0x00000100 }, - { 0xA834, 0xFFFFFFFF, 0x00A00F51 }, - { 0xA838, 0xFFFFFFFF, 0x000B0000 }, - { 0xA83C, 0xFFFFFFFF, 0xcb7D3307 }, - { 0xA840, 0xFFFFFFFF, 0x003C0000 }, - { 0xA844, 0xFFFFFFFF, 0xFFFF0000 }, - { 0xA848, 0xFFFFFFFF, 0x00220000 }, - { 0xA84c, 0xFFFFFFFF, 0x43000000 }, - { 0xA850, 0xFFFFFFFF, 0x00000800 }, - { 0xA854, 0xFFFFFFFF, 0x00000F00 }, - { 0xA858, 0xFFFFFFFF, 0x00000021 }, - { 0xA85c, 0xFFFFFFFF, 0x00000000 }, - { 0xA860, 0xFFFFFFFF, 0x00190000 }, - { 0xAA80, 0xFFFFFFFF, 0x00FF00FF }, - { 0xAA84, 0xFFFFFFFF, 0x00000000 }, - { 0x1300A4, 0xFFFFFFFF, 0x00000000 }, - - /* SET2 */ - { 0xA900, 0xFFFFFFFF, 0x00000000 }, - { 0xA904, 0xFFFFFFFF, 0x00000000 }, - { 0xA908, 0xFFFFFFFF, 0x00000000 }, - { 0xa90c, 0xFFFFFFFF, 0x1D000000 }, - { 0xa910, 0xFFFFFFFF, 0xAC005000 }, - { 0xa914, 0xFFFFFFFF, 0x000F0000 }, - { 0xa918, 0xFFFFFFFF, 0x5A000000 }, - { 0xa91c, 0xFFFFFFFF, 0x2600001F }, - { 0xa920, 0xFFFFFFFF, 0x00090000 }, - { 0xa924, 0xFFFFFFFF, 0x2000ff00 }, - { 0xa928, 0xFFFFFFFF, 0xff090016 }, - { 0xa92c, 0xFFFFFFFF, 0x00000000 }, - { 0xa930, 0xFFFFFFFF, 0x00000100 }, - { 0xa934, 0xFFFFFFFF, 0x00A00F51 }, - { 0xa938, 0xFFFFFFFF, 0x000B0000 }, - { 0xA93C, 0xFFFFFFFF, 0xcb7D3307 }, - { 0xA940, 0xFFFFFFFF, 0x003C0000 }, - { 0xA944, 0xFFFFFFFF, 0xFFFF0000 }, - { 0xA948, 0xFFFFFFFF, 0x00220000 }, - { 0xA94C, 0xFFFFFFFF, 0x43000000 }, - { 0xA950, 0xFFFFFFFF, 0x00000800 }, - { 0xA954, 0xFFFFFFFF, 0x00000000 }, - { 0xA960, 0xFFFFFFFF, 0x00000000 }, - - /* SET3 */ - { 0xaa3c, 0xFFFFFFFF, 0x00000000 }, - { 0xaa54, 0xFFFFFFFF, 0x00000000 }, - { 0xaa60, 0xFFFFFFFF, 0x00000000 }, - - /* Enable PowerMeter Counters */ - { 0xA248, 0xFFFFFFFF, 0x00000058 }, - - { 0 } -}; - -static const struct gt_reg gfx_rc6_registers[] = { - { 0xA090, 0xFFFFFFFF, 0x00000000 }, - - /* RC1e - RC6/6p - RC6pp Wake Rate Limits */ - { 0xA09C, 0xFFFFFFFF, 0x00280000 }, - { 0xA0A8, 0xFFFFFFFF, 0x0001E848 }, - { 0xA0AC, 0xFFFFFFFF, 0x00000019 }, - - /* RC Sleep / RCx Thresholds */ - { 0xA0B0, 0xFFFFFFFF, 0x00000000 }, - { 0xA0B8, 0xFFFFFFFF, 0x00000557 }, - - { 0 } -}; - -static const struct gt_reg gfx_turbo_registers[] = { - /* Render/Video/Blitter Idle Max Count */ - { 0x2054, 0xFFFFFFFF, 0x0000000A }, - { 0x12054, 0xFFFFFFFF, 0x0000000A }, - { 0x22054, 0xFFFFFFFF, 0x0000000A }, - - /* RP Down Timeout */ - { 0xA010, 0xFFFFFFFF, 0x000F4240 }, - - { 0 } -}; - -static const struct gt_reg gfx_turbo_ctl_registers[] = { - /* RP Up/Down Threshold */ - { 0xA02C, 0xFFFFFFFF, 0x0000E8E8 }, - { 0xA030, 0xFFFFFFFF, 0x0003BD08 }, - - /* RP Up/Down EI */ - { 0xA068, 0xFFFFFFFF, 0x000101D0 }, - { 0xA06C, 0xFFFFFFFF, 0x00055730 }, - - { 0 } -}; - -static struct resource *gtt_res = NULL; - -static inline unsigned long gtt_read(unsigned long reg) -{ - u32 val; - val = read32(gtt_res->base + reg); - return val; - -} - -static inline void gtt_write(unsigned long reg, unsigned long data) -{ - write32(gtt_res->base + reg, data); -} - -static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask) -{ - u32 val = gtt_read(reg); - val &= andmask; - val |= ormask; - gtt_write(reg, val); -} - -static void gtt_write_regs(const struct gt_reg *gt) -{ - for (; gt && gt->reg; gt++) - gtt_rmw(gt->reg, gt->andmask, gt->ormask); -} - -#define GFX_POLL_RETRY 10000 - -static int gtt_poll(u32 reg, u32 mask, u32 value) -{ - unsigned try = GFX_POLL_RETRY; - u32 data; - - while (try--) { - data = gtt_read(reg); - if ((data & mask) == value) - return 1; - udelay(100); - } - - printk(BIOS_ERR, "GTT timeout\n"); - return 0; -} - -static int gfx_poll_power_gate(u32 mask, u32 value) -{ - unsigned try = GFX_POLL_RETRY; - u32 data; - - while (try--) { - data = iosf_punit_read(PUNIT_PWRGT_STATUS); - if ((data & mask) == value) - return 1; - udelay(100); - } - - printk(BIOS_ERR, "Power Gate timeout\n"); - return 0; -} +#define GFX_TIMEOUT 100000 /* 100ms */ /* * Lock Power Context Base Register to point to a 24KB block @@ -210,6 +38,7 @@ static int gfx_poll_power_gate(u32 mask, u32 value) */ static void gfx_lock_pcbase(device_t dev) { + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); const u16 gms_size_map[17] = { 0,32,64,96,128,160,192,224,256, 288,320,352,384,416,448,480,512 }; u32 pcsize = 24 << 10; /* 24KB */ @@ -227,154 +56,244 @@ static void gfx_lock_pcbase(device_t dev) pcbase += (gmsize-1) * wopcmsz - pcsize; pcbase |= 1; /* Lock */ - gtt_write(0x182120, pcbase); + write32(res->base + 0x182120, pcbase); } -static void gfx_pm_init(device_t dev) -{ - printk(BIOS_INFO, "GFX: Power Management Init\n"); - - /* - * Allow-Wake render/media wells. - * Used by PUNIT as part of S0IX save/restore. - */ - gtt_rmw(0x130090, ~1, 1); - if (!gtt_poll(0x130094, 1, 1)) { - printk(BIOS_ERR, "gfx_pm_init: Unable to allow-wake\n"); - return; - } - +static const struct reg_script gfx_init_script[] = { + /* Allow-Wake render/media wells */ + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x130090, ~1, 1), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x130094, 1, 1, GFX_TIMEOUT), /* Render Force-Wake */ - gtt_write(0x1300B0, 0x80008000); - if (!gtt_poll(0x1300B4, 0x8000, 0x8000)) { - printk(BIOS_ERR, "gfx_pm_init: Unable to force-wake render\n"); - return; - } - + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80008000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0x8000, + GFX_TIMEOUT), /* Media Force-Wake */ - gtt_write(0x1300B8, 0x80008000); - if (!gtt_poll(0x1300BC, 0x8000, 0x8000)) { - printk(BIOS_ERR, "gfx_pm_init: Unable to force-wake media\n"); - return; - }; - + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80008000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0x8000, + GFX_TIMEOUT), /* Workaround - X0:261954/A0:261955 */ - gtt_rmw(0x182060, ~0xf, 1); + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x182060, ~0xf, 1), + + /* + * PowerMeter Weights + */ - /* Program GT PowerMeter weights */ - gtt_write_regs(gfx_powermeter_weights); + /* SET1 */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA800, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA804, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA808, 0x0000ff0A), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA80C, 0x1D000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA810, 0xAC004900), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA814, 0x000F0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA818, 0x5A000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA81C, 0x2600001F), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA820, 0x00090000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA824, 0x2000ff00), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA828, 0xff090016), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA82C, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA830, 0x00000100), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA834, 0x00A00F51), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA838, 0x000B0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA83C, 0xcb7D3307), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA840, 0x003C0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA844, 0xFFFF0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA848, 0x00220000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA84c, 0x43000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA850, 0x00000800), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA854, 0x00000F00), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA858, 0x00000021), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA85c, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA860, 0x00190000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA80, 0x00FF00FF), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xAA84, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x1300A4, 0x00000000), + /* SET2 */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA900, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA904, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA908, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa90c, 0x1D000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa910, 0xAC005000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa914, 0x000F0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa918, 0x5A000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa91c, 0x2600001F), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa920, 0x00090000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa924, 0x2000ff00), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa928, 0xff090016), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa92c, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa930, 0x00000100), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa934, 0x00A00F51), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xa938, 0x000B0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA93C, 0xcb7D3307), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA940, 0x003C0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA944, 0xFFFF0000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA948, 0x00220000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA94C, 0x43000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA950, 0x00000800), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA954, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA960, 0x00000000), + /* SET3 */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa3c, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa54, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xaa60, 0x00000000), + /* Enable PowerMeter Counters */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA248, 0x00000058), /* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */ /* SDP Profile 4 == 0x11940, others 0xcf08 */ - iosf_punit_write(PUNIT_GPU_EC_VIRUS, 0xcf08); + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08), /* GfxPause */ - gtt_write(0xa000, 0x00071388); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388), /* Dynamic EU Control Settings */ - gtt_write(0xa080, 0x00000004); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa080, 0x00000004), /* Lock ECO Bit Settings */ - gtt_write(0xa180, 0x80000000); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa180, 0x80000000), /* DOP Clock Gating */ - gtt_write(0x9424, 0x00000001); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9424, 0x00000001), /* MBCunit will send the VCR (Fuse) writes as NP-W */ - gtt_rmw(0x907c, 0xfffeffff, 0x00010000); + REG_RES_RMW32(PCI_BASE_ADDRESS_0, 0x907c, 0xfffeffff, 0x00010000), - /* RC6 Settings */ - gtt_write_regs(gfx_rc6_registers); + /* + * RC6 Settings + */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA090, 0x00000000), + /* RC1e - RC6/6p - RC6pp Wake Rate Limits */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA09C, 0x00280000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0A8, 0x0001E848), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0AC, 0x00000019), + /* RC Sleep / RCx Thresholds */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B0, 0x00000000), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA0B8, 0x00000557), - /* Turbo Settings */ - gtt_write_regs(gfx_turbo_registers); + /* + * Turbo Settings + */ - /* Turbo Control Settings */ - gtt_write_regs(gfx_turbo_ctl_registers); + /* Render/Video/Blitter Idle Max Count */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x2054, 0x0000000A), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x12054, 0x0000000A), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0x22054, 0x0000000A), + /* RP Down Timeout */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA010, 0x000F4240), + + /* + * Turbo Control Settings + */ + + /* RP Up/Down Threshold */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA02C, 0x0000E8E8), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA030, 0x0003BD08), + /* RP Up/Down EI */ + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA068, 0x000101D0), + REG_RES_OR32(PCI_BASE_ADDRESS_0, 0xA06C, 0x00055730), /* RP Idle Hysteresis */ - gtt_write(0xa070, 0x0000000a); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa070, 0x0000000a), /* HW RC6 Control Settings */ - gtt_write(0xa090, 0x11000000); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa090, 0x11000000), /* RP Control */ - gtt_write(0xa024, 0x00000592); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa024, 0x00000592), /* Enable PM Interrupts */ - gtt_write(0x44024, 0x03000000); - gtt_write(0x4402c, 0x03000076); - gtt_write(0xa168, 0x0000007e); - - /* Lock power context base */ - gfx_lock_pcbase(dev); + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x44024, 0x03000000), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x4402c, 0x03000076), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa168, 0x0000007e), /* Aggressive Clock Gating */ - gtt_write(0x9400, 0); - gtt_write(0x9404, 0); - gtt_write(0x9408, 0); - gtt_write(0x940c, 0); -} + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9400, 0), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9404, 0), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x9408, 0), + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x940c, 0), + REG_SCRIPT_END +}; -static void gfx_pre_vbios_init(device_t dev) -{ +static const struct reg_script gpu_pre_vbios_script[] = { + /* Make sure GFX is bus master with MMIO access */ + REG_PCI_OR32(PCI_COMMAND, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY), /* Display */ - iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xc0); - gfx_poll_power_gate(0xc0, 0xc0); - + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xc0, 0xc0, + GFX_TIMEOUT), /* Tx/Rx Lanes */ - iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xfff0c0); - gfx_poll_power_gate(0xfff0c0, 0xfff0c0); - + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfff0c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfff0c0, 0xfff0c0, + GFX_TIMEOUT), /* Common Lane */ - iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xfffcc0); - gfx_poll_power_gate(0xfffcc0, 0xfffcc0); - + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xfffcc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xfffcc0, + GFX_TIMEOUT), /* Ungating Tx only */ - iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf00cc0); - gfx_poll_power_gate(0xfffcc0, 0xf00cc0); - + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00cc0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffcc0, 0xf00cc0, + GFX_TIMEOUT), /* Ungating Common Lane only */ - iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf000c0); - gfx_poll_power_gate(0xffffc0, 0xf000c0); - + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf000c0), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xffffc0, 0xf000c0, + GFX_TIMEOUT), /* Ungating Display */ - iosf_punit_write(PUNIT_PWRGT_CONTROL, 0xf00000); - gfx_poll_power_gate(0xfffff0, 0xf00000); -} + REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PWRGT_CONTROL, 0xf00000), + REG_IOSF_POLL(IOSF_PORT_PMC, PUNIT_PWRGT_STATUS, 0xfffff0, 0xf00000, + GFX_TIMEOUT), + REG_SCRIPT_END +}; -static void gfx_post_vbios_init(device_t dev) -{ +static const struct reg_script gfx_post_vbios_script[] = { /* Deassert Render Force-Wake */ - gtt_write(0x1300B0, 0x80000000); - gtt_poll(0x1300B4, 0x8000, 0); - + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b0, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300b4, 0x8000, 0, GFX_TIMEOUT), /* Deassert Media Force-Wake */ - gtt_write(0x1300B8, 0x80000000); - gtt_poll(0x1300BC, 0x8000, 0); - + REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0x1300b8, 0x80000000), + REG_RES_POLL32(PCI_BASE_ADDRESS_0, 0x1300bc, 0x8000, 0, GFX_TIMEOUT), /* Set Lock bits */ - pci_write_config32(dev, GGC, pci_read_config32(dev, GGC) | 1); - pci_write_config32(dev, GSM_BASE, pci_read_config32(dev, GSM_BASE) | 1); - pci_write_config32(dev, GTT_BASE, pci_read_config32(dev, GTT_BASE) | 1); + REG_PCI_RMW32(GGC, 0xffffffff, 1), + REG_PCI_RMW32(GSM_BASE, 0xffffffff, 1), + REG_PCI_RMW32(GTT_BASE, 0xffffffff, 1), + REG_SCRIPT_END +}; + +static void gfx_run_script(device_t dev, const struct reg_script *ops) +{ + struct reg_script steps[] = { + REG_SCRIPT_SET_DEV(dev), + REG_SCRIPT_NEXT(ops), + REG_SCRIPT_END, + }; + reg_script_run(&steps[0]); } -static void gfx_init(device_t dev) +static void gfx_pre_vbios_init(device_t dev) { - u32 reg32; + printk(BIOS_INFO, "GFX: Pre VBIOS Init\n"); + gfx_run_script(dev, gpu_pre_vbios_script); +} - /* Find GTT resource */ - gtt_res = find_resource(dev, PCI_BASE_ADDRESS_0); - if (!gtt_res || !gtt_res->base) - return; +static void gfx_pm_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Power Management Init\n"); + gfx_run_script(dev, gfx_init_script); - /* GFX needs to be Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO; - pci_write_config32(dev, PCI_COMMAND, reg32); + /* Lock power context base */ + gfx_lock_pcbase(dev); +} +static void gfx_post_vbios_init(device_t dev) +{ + printk(BIOS_INFO, "GFX: Post VBIOS Init\n"); + gfx_run_script(dev, gfx_post_vbios_script); +} + +static void gfx_init(device_t dev) +{ /* Pre VBIOS Init */ gfx_pre_vbios_init(dev); + + /* Power Management Init */ gfx_pm_init(dev); /* Run VBIOS */

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Patch set updated for coreboot: e9d5be9 baytrail: Reserve memory between ASEG and 1MB and for ramoops
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4932 -gerrit commit e9d5be9468e0e67e6c5788fc1cad8e87a2af6cf6 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sun Nov 3 19:38:12 2013 -0800 baytrail: Reserve memory between ASEG and 1MB and for ramoops Low system tables are in this region, and it is probably safer to keep ASEG reserved. Also keep the region used by ramoops from being used by the OS and from being cleared by developer mode boots. Lots more work needed to make the ACPI tables fully functional. BUG=chrome-os-partner:23505 BRANCH=rambi TEST=boot on rambi and see that the kernel finds RSDP and uses ACPI Change-Id: I4f7064d3cff14a3ecf15b194a1f20c1fa9d5e134 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175554 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/baytrail/northcluster.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 714d532..eca122c 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -117,6 +117,20 @@ static void nc_read_resources(device_t dev) if (bmbound_hi > four_gig_kib) ram_resource(dev, index++, four_gig_kib, bmbound_hi - four_gig_kib); + + /* Reserve everything between A segment and 1MB: + * + * 0xa0000 - 0xbffff: legacy VGA + * 0xc0000 - 0xfffff: RAM + */ + mmio_resource(dev, index++, (0xa0000 >> 10), (0xc0000 - 0xa0000) >> 10); + reserved_ram_resource(dev, index++, (0xc0000 >> 10), + (0x100000 - 0xc0000) >> 10); +#if CONFIG_CHROMEOS_RAMOOPS + reserved_ram_resource(dev, index++, + CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10, + CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); +#endif } static struct device_operations nc_ops = {

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Patch set updated for coreboot: 095dad2 baytrail: add audio clock workaround for LPE
by Aaron Durbin 04 Mar '14

04 Mar '14

Aaron Durbin (adurbin(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4928 -gerrit commit 095dad2e1b5567d77ba590defba627c2752846b3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 1 14:36:03 2013 -0500 baytrail: add audio clock workaround for LPE Apparently the LPE device needs a 25MHz clock. Provide the work around to enable this clock. BUG=chrome-os-partner:23791 BRANCH=None TEST=Built and booted. Confirmed setting being applied. Change-Id: Ibff5563436b3025eb8b61ffee3302bd2da872b39 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175493 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/baytrail/Makefile.inc | 1 + src/soc/intel/baytrail/lpe.c | 53 +++++++++++++++++++++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index d414057..2149e97 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -35,6 +35,7 @@ ramstage-y += southcluster.c ramstage-$(CONFIG_HAVE_REFCODE_BLOB) += refcode.c ramstage-y += sata.c ramstage-y += acpi.c +ramstage-y += lpe.c # Remove as ramstage gets fleshed out ramstage-y += placeholders.c diff --git a/src/soc/intel/baytrail/lpe.c b/src/soc/intel/baytrail/lpe.c new file mode 100644 index 0000000..e422ff6 --- /dev/null +++ b/src/soc/intel/baytrail/lpe.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> + +#include <baytrail/iosf.h> +#include <baytrail/ramstage.h> + +static void lpe_init(device_t dev) +{ + uint32_t reg; + + /* Work around for Audio Clock. */ + reg = iosf_ccu_read(PLT_CLK_CTRL_3); + reg &= ~0xff; + reg |= PLT_CLK_CTRL_25MHZ_FREQ | PLT_CLK_CTRL_SELECT_FREQ; + iosf_ccu_write(PLT_CLK_CTRL_3, reg); +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = NULL, + .init = lpe_init, + .enable = NULL, + .scan_bus = NULL, + .ops_pci = &soc_pci_ops, +}; + +static const struct pci_driver southcluster __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = LPE_DEVID, +};

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coreboot-gerrit March 2014