coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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1346 discussions

New patch to review for coreboot: 53b55ed fsp_baytrail: Update microcode for Gold 3 FSP release
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7647 -gerrit commit 53b55edf41a127c51533ddff3a260b7c83c87187 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Dec 4 18:12:20 2014 -0700 fsp_baytrail: Update microcode for Gold 3 FSP release New microcode for Bay Trail I B2/B3 and D0 parts was released in the Gold 3 Bay Trail FSP release. Change the microcode size to an area instead of the exact size of the patches. This will hopefully reduce updates to the microcode size Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 10 ++++++++-- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 51b6c19..709ff92 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,8 +19,14 @@ unsigned microcode[] = { -/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */ +/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M013067331E.h" // M0130673: Baytrail I B2 / B3 +#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 +#include "M0130679901.h" // M0130679: Baytrail I D0 + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index df6082d..ec55314 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,2 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x19800 +#define MICROCODE_REGION_LENGTH 0x30000

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New patch to review for coreboot: e014d69 FSP platform microcode: Update to remove Kconfig variable
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7646 -gerrit commit e014d69812ffbcaacb9906bfa5414e03b9866a49 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Dec 4 18:06:36 2014 -0700 FSP platform microcode: Update to remove Kconfig variable Move the Kconfig variable into a .h file - this does not need to be in Kconfig. Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 6 ------ src/cpu/intel/fsp_model_206ax/Makefile.inc | 1 + src/cpu/intel/fsp_model_206ax/microcode_blob.h | 4 ++-- src/cpu/intel/fsp_model_206ax/microcode_size.h | 7 +++++++ src/cpu/intel/fsp_model_406dx/Kconfig | 6 ------ src/cpu/intel/fsp_model_406dx/Makefile.inc | 1 + src/cpu/intel/fsp_model_406dx/microcode_blob.c | 4 ++-- src/cpu/intel/fsp_model_406dx/microcode_size.h | 7 +++++++ src/drivers/intel/fsp/cache_as_ram.inc | 3 ++- src/soc/intel/fsp_baytrail/Kconfig | 6 ------ src/soc/intel/fsp_baytrail/microcode/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 2 +- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 ++ 13 files changed, 26 insertions(+), 24 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 043320c..c05b12b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -58,12 +58,6 @@ config CPU_MICROCODE_CBFS_LOC depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff70000 -config CPU_MICROCODE_CBFS_LEN - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0xC000 if CPU_INTEL_FSP_MODEL_306AX - default 0x2800 if CPU_INTEL_FSP_MODEL_206AX - config MICROCODE_INCLUDE_PATH string "Location of the intel microcode patches" default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index e3d3ca5..aee3101 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -10,5 +10,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) +CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax endif endif diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h index e56bef1..6a3eaaf 100644 --- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h +++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.h @@ -19,12 +19,12 @@ */ #if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX) - /* Size is 0x2800 - Update in Kconfigs when any included file changes*/ + /* Size is 0x2800 - Update in microcode_size.h when any included file changes*/ #include <microcode-m12206a7_00000029.h> #endif #if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX) - /* Size is 0xC000 - Update in Kconfigs when any included file changes*/ + /* Size is 0xC000 - Update in microcode_size.h when any included file changes*/ #include <microcode-m12306a2_00000008.h> #include <microcode-m12306a4_00000007.h> #include <microcode-m12306a5_00000007.h> diff --git a/src/cpu/intel/fsp_model_206ax/microcode_size.h b/src/cpu/intel/fsp_model_206ax/microcode_size.h new file mode 100644 index 0000000..0b0364c --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/microcode_size.h @@ -0,0 +1,7 @@ +/* Maximum size of the area that the FSP will search for the correct microcode */ + +#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX) + #define MICROCODE_REGION_LENGTH 0xC000 +#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX) + #define MICROCODE_REGION_LENGTH 0x2800 +#endif diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 11a92a0..5cd4c65 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -62,12 +62,6 @@ config CPU_MICROCODE_CBFS_LOC depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff60040 -config CPU_MICROCODE_CBFS_LEN - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0x14400 if FSP_MODEL_406DX_A1 - default 0x14800 if FSP_MODEL_406DX_B0 - config MICROCODE_INCLUDE_PATH string "Location of the intel microcode patches" default "../intel/cpu/rangeley/microcode" diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index 767cc20..3516bcc 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -27,5 +27,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) +CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx endif endif diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c index a4b7d42..74fe76c 100644 --- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c +++ b/src/cpu/intel/fsp_model_406dx/microcode_blob.c @@ -20,10 +20,10 @@ unsigned microcode[] = { #if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1) - /* Size is 0x14400 */ + /* Size is 0x14400 - update in microcode_size.h when the file changes */ #include <microcode-m01406d000e.h> #elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0) - /* Size is 0x14800 */ + /* Size is 0x14800 - update in microcode_size.h when the file changes */ #include <microcode-m01406d811d.h> #endif }; diff --git a/src/cpu/intel/fsp_model_406dx/microcode_size.h b/src/cpu/intel/fsp_model_406dx/microcode_size.h new file mode 100644 index 0000000..b638ae5 --- /dev/null +++ b/src/cpu/intel/fsp_model_406dx/microcode_size.h @@ -0,0 +1,7 @@ +/* Maximum size of the area that the FSP will search for the correct microcode */ + +#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1) + #define MICROCODE_REGION_LENGTH 0x14400 +#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0) + #define MICROCODE_REGION_LENGTH 0x14800 +#endif diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc index 0fc33cb..9e8b2a2 100644 --- a/src/drivers/intel/fsp/cache_as_ram.inc +++ b/src/drivers/intel/fsp/cache_as_ram.inc @@ -22,6 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <microcode_size.h> #include <cbmem.h> #ifndef CONFIG_FSP_LOC @@ -158,7 +159,7 @@ fake_fsp_stack: CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC - .long CONFIG_CPU_MICROCODE_CBFS_LEN + .long MICROCODE_REGION_LENGTH .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */ .long CACHE_ROM_SIZE /* Total Firmware Length */ diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index e9391c3..85b3d32 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -102,12 +102,6 @@ config CPU_MICROCODE_CBFS_LOC hex default 0xfff10040 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x19800 - help - This should be updated when the microcode patch changes. - config CBFS_SIZE hex default 0x200000 diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc index f6ee135..3a17acb 100644 --- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc @@ -21,5 +21,6 @@ cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) CPPFLAGS_common += -I$(CONFIG_MICROCODE_INCLUDE_PATH) +CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode endif endif diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 43cbf00..51b6c19 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,7 +19,7 @@ unsigned microcode[] = { -/* Size is 0x19800 - update in Kconfig when the patch gets updated. */ +/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */ #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 #include "M013067331E.h" // M0130673: Baytrail I B2 / B3 diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h new file mode 100644 index 0000000..df6082d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -0,0 +1,2 @@ +/* Maximum size of the area that the FSP will search for the correct microcode */ +#define MICROCODE_REGION_LENGTH 0x19800

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New patch to review for coreboot: 2436680 RISCV: one last little nit to make it build and run
by Ronald G. Minnich 04 Dec '14

04 Dec '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7645 -gerrit commit 2436680f507a0b00ef2f083cd7d403536654eddd Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Dec 4 19:24:20 2014 +0000 RISCV: one last little nit to make it build and run Change-Id: I6e9e1dff09c08079774f7d6e60e67a12760d37b4 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 1020fc7..242fd40 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -41,7 +41,9 @@ bootblock-y += \ $(objcbfs)/bootblock.debug: $(src)/arch/riscv/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) -m elf64lriscv --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/riscv/bootblock.ld + $(CC_bootblock) $(CFLAGS_bootblock) -nostartfiles -Wl,--gc-sections -static -o $@ -L$(obj) \ + -T $(src)/arch/riscv/bootblock.ld -Wl,--start-group $(bootblock-objs) \ + $(LIBGCC_FILE_NAME_bootblock) -Wl,--end-group endif

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New patch to review for coreboot: 7c6f9c9 mainboard/lenovo/g505s/Kconfig: Remove used PIRQ legacy bits
by Edward O'Callaghan 04 Dec '14

04 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7644 -gerrit commit 7c6f9c9a87acee661503988f5a7d11994cb10de7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 05:32:35 2014 +1100 mainboard/lenovo/g505s/Kconfig: Remove used PIRQ legacy bits Change-Id: I1068dd99c4cecdd2113484fe24ae2bb86a058cb3 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/Kconfig | 5 ----- 1 file changed, 5 deletions(-) diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index fc3a6ac..2019f95 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_AMD_AGESA_HUDSON select EC_COMPAL_ENE932 select HAVE_OPTION_TABLE - select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_RESUME select HAVE_SMI_HANDLER @@ -56,10 +55,6 @@ config HW_MEM_HOLE_SIZE_AUTO_INC bool default n -config IRQ_SLOT_COUNT - int - default 11 - config ONBOARD_VGA_IS_PRIMARY bool default y

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Patch merged into coreboot/master: fc5dc1c RISCV: get RISCV to build again
by gerrit＠coreboot.org 04 Dec '14

04 Dec '14

the following patch was just integrated into master: commit fc5dc1c3effb82325a77f2c0c66e95bc7f90de05 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Dec 2 04:07:02 2014 +0000 RISCV: get RISCV to build again This makes lzmadecode 64-bit clean (I hope). It also cleans up a few other nits. Change-Id: I24492e9f357e8d3a6de6abc351267f900eb4a19a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/7623 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7623 for details. -gerrit

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New patch to review for coreboot: ea95e8c mainboard/lenovo/g505s: Toggle on IOMMU support
by Edward O'Callaghan 04 Dec '14

04 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7643 -gerrit commit ea95e8c072ab32cdfc0a5dc6d67f35f2cfb850a0 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 04:25:44 2014 +1100 mainboard/lenovo/g505s: Toggle on IOMMU support Change-Id: Ia838f9b70f09ed1180daeb5382edc08c4b74946c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/buildOpts.c | 2 +- src/mainboard/lenovo/g505s/devicetree.cb | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 56de36e..d6328bc 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -186,7 +186,7 @@ #define BLDCFG_UMA_ABOVE4G_SUPPORT FALSE #endif -#define BLDCFG_IOMMU_SUPPORT FALSE +#define BLDCFG_IOMMU_SUPPORT TRUE #define BLDCFG_CFG_GNB_HD_AUDIO TRUE //#define BLDCFG_IGPU_SUBSYSTEM_ID OEM_IGPU_SSID diff --git a/src/mainboard/lenovo/g505s/devicetree.cb b/src/mainboard/lenovo/g505s/devicetree.cb index e9718ba..5e79c03 100644 --- a/src/mainboard/lenovo/g505s/devicetree.cb +++ b/src/mainboard/lenovo/g505s/devicetree.cb @@ -30,6 +30,7 @@ chip northbridge/amd/agesa/family15rl/root_complex chip northbridge/amd/agesa/family15rl # PCI side of HT root complex device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX device pci 1.1 on end # Internal Multimedia device pci 2.0 off end

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New patch to review for coreboot: 092f714 vendorcode/amd/agesa/f15tn: Fix GnbIommuScratch in AGESA compilation
by Edward O'Callaghan 04 Dec '14

04 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7642 -gerrit commit 092f71432297e03192c719e5ca8cdda9fd3ac71d Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 05:01:45 2014 +1100 vendorcode/amd/agesa/f15tn: Fix GnbIommuScratch in AGESA compilation Missing IOMMU support is missing from the libagesa Makefile, it also lacks a header with type-signature and a few bad typecast issues. Change-Id: I7f2ad2104de9baaa66dbb6ffeb0f2b4d35fa5c16 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + .../f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 2 ++ .../f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h | 11 +++++++++++ 3 files changed, 14 insertions(+) diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 4b44cef..278cb8e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -230,6 +230,7 @@ libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c libagesa-y += Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c libagesa-y += Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c libagesa-y += Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index 5ed82bc..4433c69 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -36,6 +36,8 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +#include "GnbIommuScratch.h" + #include "AGESA.h" #include "Ids.h" #include "S3SaveState.h" diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h new file mode 100644 index 0000000..a01b167 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h @@ -0,0 +1,11 @@ +#ifndef _GNBIOMMUSCRATCH_H_ +#define _GNBIOMMUSCRATCH_H_ + +#include "AGESA.h" + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif /* _GNBIOMMUSCRATCH_H_ */

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New patch to review for coreboot: 494606e vendorcode/amd/agesa/f15tn: Trim out ASCII art in GnbIommuScratch.c
by Edward O'Callaghan 04 Dec '14

04 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7641 -gerrit commit 494606eff0c3287208b8aab1725a7a6d2795ea61 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 04:52:52 2014 +1100 vendorcode/amd/agesa/f15tn: Trim out ASCII art in GnbIommuScratch.c TL;DR ASCII art that sucks, remove it. Change-Id: I424736b040fe019bba6155de76903225a266760d Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- .../GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 32 ++-------------------- 1 file changed, 2 insertions(+), 30 deletions(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index 45d0cd7..5ed82bc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -1,11 +1,8 @@ -/* $NoKeywords:$ */ /** * @file * * NB services * - * - * * @xrefitem bom "File Content Label" "Release Content" * @e project: AGESA * @e sub-project: GNB @@ -13,8 +10,6 @@ * */ /* -***************************************************************************** -* * Copyright (c) 2008 - 2012, Advanced Micro Devices, Inc. * All rights reserved. * @@ -39,14 +34,8 @@ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -* *************************************************************************** -* -*/ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- */ + #include "AGESA.h" #include "Ids.h" #include "S3SaveState.h" @@ -57,26 +46,9 @@ #include "GnbRegistersTN.h" #include "heapManager.h" #include "Filecode.h" -#define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ +#define FILECODE PROC_GNB_MODULES_GNBIOMMUSCRATCH_GNBIOMMUSCRATCH_FILECODE -/*----------------------------------------------------------------------------------------*/ /** * Set Iommu Scratch Memory Range * 1) code needs to be executed at Late Init

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Patch set updated for coreboot: b0b09ba RISCV: get RISCV to build again
by Ronald G. Minnich 04 Dec '14

04 Dec '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7623 -gerrit commit b0b09ba468dda9b98febd2bec99d09bc0828ec83 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Dec 2 04:07:02 2014 +0000 RISCV: get RISCV to build again This makes lzmadecode 64-bit clean (I hope). It also cleans up a few other nits. Change-Id: I24492e9f357e8d3a6de6abc351267f900eb4a19a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 4 +--- src/arch/riscv/rom_media.c | 8 -------- src/lib/lzmadecode.c | 3 ++- src/mainboard/emulation/qemu-riscv/uart.c | 1 - 4 files changed, 3 insertions(+), 13 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 394220c..1020fc7 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -41,7 +41,7 @@ bootblock-y += \ $(objcbfs)/bootblock.debug: $(src)/arch/riscv/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) -m elf64-littleriscv --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/riscv/bootblock.ld + $(LD_bootblock) -m elf64lriscv --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/riscv/bootblock.ld endif @@ -58,7 +58,6 @@ romstage-y += \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c -romstage-y += cbmem.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -86,7 +85,6 @@ ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c -ramstage-y += cbmem.c ramstage-y += tables.c ramstage-y += \ $(top)/src/lib/memchr.c \ diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c index 712b7c4..8e858cb 100644 --- a/src/arch/riscv/rom_media.c +++ b/src/arch/riscv/rom_media.c @@ -90,11 +90,3 @@ static int init_rom_media_cbfs(struct cbfs_media *media) { int init_default_cbfs_media(struct cbfs_media *media) { return init_rom_media_cbfs(media); } -// bug in coreboot. Fix me. -// even if you have no use for lzma cbfs demands it. -// and the ulzma code is terrible -- full of bad 32/64 bad things. -unsigned long ulzma(unsigned char *src, unsigned char *dst); -unsigned long ulzma(unsigned char *src, unsigned char *dst) -{ - return 0; -} diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index fb57f4f..ada7226 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -20,6 +20,7 @@ */ #include "lzmadecode.h" +#include <stdint.h> #define kNumTopBits 24 #define kTopValue ((UInt32)1 << kNumTopBits) @@ -30,7 +31,7 @@ /* Use 32-bit reads whenever possible to avoid bad flash performance. */ #define RC_READ_BYTE (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ - : ((((UInt32) Buffer & 3) || ((SizeT) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ + : ((((uintptr_t) Buffer & 3) || ((SizeT) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), (look_ahead_ptr = 1), look_ahead.raw[0]))) #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 40192c9..6647cde 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -21,7 +21,6 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> -#include "frontend.h" static uint8_t *buf = (void *)0x3f8; uintptr_t uart_platform_base(int idx)

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Patch merged into coreboot/master: 2031699 vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementation
by gerrit＠coreboot.org 04 Dec '14

04 Dec '14

the following patch was just integrated into master: commit 20316990113072cdfdc33a231d8f6340f5e3cbc7 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Nov 28 22:58:01 2014 +1100 vendorcode/amd/agesa/f*/cpcar.in: Remove non-GCC CAR implementation We don't actually use nor support these as our implementation makes use of gcccar.inc. They maybe useful as a reference for history so lets keep them in version history. Change-Id: I388251dead449dde14283e57db39c37982d947b2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7596 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/7596 for details. -gerrit

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coreboot-gerrit December 2014