coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: 1a31a9e fsp_baytrail: Allow selection of USB controller by get_option
by Martin Roth 03 Dec '14

03 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7633 -gerrit commit 1a31a9e3241199d2cd7e981b3128ed7ce8b5c4e3 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Dec 2 21:51:03 2014 -0700 fsp_baytrail: Allow selection of USB controller by get_option It was requested to be able to update XHCI vs EHCI via get_option, so I've added it here for minnow max. This could get moved to the chipset_fsp_util.c file later, but I'm adding it here for now. More checking needs to be added to this: - Are both controllers enabled in devicetree? If not, we don't want to allow the switch. Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/minnowmax/cmos.layout | 6 +++++- src/mainboard/intel/minnowmax/romstage.c | 11 +++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index a668188..c7dc88d 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 2 e 8 use_xhci_over_ehci +#413 3 r 0 unused # MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -133,6 +134,9 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 EHCI +8 1 XHCI +8 2 Default # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c index af63cab..a144722 100644 --- a/src/mainboard/intel/minnowmax/romstage.c +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -21,6 +21,8 @@ #include <baytrail/romstage.h> #include <drivers/intel/fsp/fsp_util.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> #include "chip.h" /** @@ -54,6 +56,7 @@ void late_mainboard_romstage_entry() void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; + u8 use_xhci = UpdData->PcdEnableXhci; /* * Minnow Max Board : 1GB SKU uses 2Gb density memory @@ -65,5 +68,13 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) UpdData->PcdMemoryParameters.DIMMDensity += (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT); + /* Update XHCI UPD value if required */ + get_option(&use_xhci, "use_xhci_over_ehci"); + if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) { + UpdData->PcdEnableXhci = use_xhci; + printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n", + UpdData->PcdEnableXhci?"Enabled":"Disabled"); + } + return; }

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Patch set updated for coreboot: 9fd14c0 spi/macronix: Add support for MX25L3239E
by Dave Frodin 03 Dec '14

03 Dec '14

Dave Frodin (dave.frodin(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7631 -gerrit commit 9fd14c0f3566633a5a5fd2864a4fdc83278c0ede Author: Dave Frodin <dave.frodin(a)se-eng.com> Date: Mon Nov 24 10:37:29 2014 -0700 spi/macronix: Add support for MX25L3239E Also update comment for the MX25L3236D part. Change-Id: Ifaeeb71e7672a8db55bbb66e6ce7316e2893478d Signed-off-by: Dave Frodin <dave.frodin(a)se-eng.com> --- src/drivers/spi/macronix.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/drivers/spi/macronix.c b/src/drivers/spi/macronix.c index 5b58e869..1516770 100644 --- a/src/drivers/spi/macronix.c +++ b/src/drivers/spi/macronix.c @@ -93,7 +93,15 @@ static const struct macronix_spi_flash_params macronix_spi_flash_table[] = { .pages_per_sector = 16, .sectors_per_block = 16, .nr_blocks = 64, - .name = "MX25L3235D", /* MX25L3225D/MX25L3235D/MX25L3237D */ + .name = "MX25L3235D", /* MX25L3225D/MX25L3235D/MX25L3236D/MX25L3237D */ + }, + { + .idcode = 0x2536, + .page_size = 256, + .pages_per_sector = 16, + .sectors_per_block = 16, + .nr_blocks = 64, + .name = "MX25L3239E", }, { .idcode = 0x2017,

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Patch merged into coreboot/master: a234f45 build system: fix alignment function
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit a234f45601e6e85a5179ec9cc446f070b86f425b Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Dec 3 11:20:51 2014 +0100 build system: fix alignment function It seriously miscomputed alignment values, always off-by-one, and off-by-an-alignment for aligned values. Change-Id: Ide3477d09d34d7728cb0666bb30dd9f7a3f1056d Reported-by: Dave Frodin <dave.frodin(a)se-eng.com> Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/7635 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Dave Frodin <dave.frodin(a)se-eng.com> See http://review.coreboot.org/7635 for details. -gerrit

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Patch set updated for coreboot: 3b26c10 AMD Hudson boards: Hide HUDSON_LEGACY_FREE prompts.
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7358 -gerrit commit 3b26c1058174f4a06d32d81a6d16fc611d10d5c6 Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Sat Nov 8 17:00:53 2014 +0100 AMD Hudson boards: Hide HUDSON_LEGACY_FREE prompts. The legacy free property depends on the board design and shouldn't be user-selectable. Any legacy keyboard, serial or other controller enabled on FCH or SuperIO invalidates the legacy free setting. In particular, if a serial port is present and used for debugging, setting HUDSON_LEGACY_FREE will cause AGESA to disable FCH/LPC I/O decode of the serial port and prevent many early boot messages from being logged to the serial port. Change-Id: Ibc9297d75917a2dd4e056e554b10c0e86877d3ed Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- src/mainboard/amd/olivehill/Kconfig | 5 +---- src/mainboard/amd/olivehillplus/Kconfig | 5 +---- src/mainboard/amd/parmer/Kconfig | 5 +---- src/mainboard/amd/thatcher/Kconfig | 5 +---- src/mainboard/asrock/imb-a180/Kconfig | 4 ---- src/southbridge/amd/agesa/hudson/Kconfig | 3 ++- 6 files changed, 6 insertions(+), 21 deletions(-) diff --git a/src/mainboard/amd/olivehill/Kconfig b/src/mainboard/amd/olivehill/Kconfig index ea97550..52bd836 100644 --- a/src/mainboard/amd/olivehill/Kconfig +++ b/src/mainboard/amd/olivehill/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA + select HUDSON_LEGACY_FREE config MAINBOARD_DIR string @@ -64,8 +65,4 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config HUDSON_LEGACY_FREE - bool - default y - endif # BOARD_AMD_OLIVEHILL diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 93f0fc6..ab32f7b 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -31,6 +31,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA + select HUDSON_LEGACY_FREE config MAINBOARD_DIR string @@ -64,8 +65,4 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config HUDSON_LEGACY_FREE - bool - default y - endif # BOARD_AMD_OLIVEHILLPLUS diff --git a/src/mainboard/amd/parmer/Kconfig b/src/mainboard/amd/parmer/Kconfig index ff198a6..2e9bebd 100644 --- a/src/mainboard/amd/parmer/Kconfig +++ b/src/mainboard/amd/parmer/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select UDELAY_LAPIC + select HUDSON_LEGACY_FREE config MAINBOARD_DIR string @@ -65,8 +66,4 @@ config VGA_BIOS_ID string default "1002,9900" -config HUDSON_LEGACY_FREE - bool - default y - endif # BOARD_AMD_PARMER diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index c228365..c6de0fe 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -32,6 +32,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_LPC47N217 select BOARD_ROMSIZE_KB_4096 select GFXUMA + select HUDSON_LEGACY_FREE config MAINBOARD_DIR string @@ -65,8 +66,4 @@ config VGA_BIOS_ID string default "1002,9917" -config HUDSON_LEGACY_FREE - bool - default y - endif # BOARD_AMD_THATCHER diff --git a/src/mainboard/asrock/imb-a180/Kconfig b/src/mainboard/asrock/imb-a180/Kconfig index f3c8aa7..6cfb48f 100644 --- a/src/mainboard/asrock/imb-a180/Kconfig +++ b/src/mainboard/asrock/imb-a180/Kconfig @@ -65,10 +65,6 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config HUDSON_LEGACY_FREE - bool - default y - # bit 1,0 - pin 0 # bit 3,2 - pin 1 # bit 5,4 - pin 2 diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 72370ea..ffedd95 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -201,7 +201,8 @@ endif config HUDSON_LEGACY_FREE bool "System is legacy free" help - Select y if there is no keyboard controller in the system. + Select y if there is no keyboard, serial or other legacy controllers + enabled in the system, on both the FCH and any LPC SuperIO or EC. This sets variables in AGESA and ACPI. config ACPI_ENABLE_THERMAL_ZONE

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Patch merged into coreboot/master: b643561 mainboard/hp/pavilion_m6_1035dx: Remove HUDSON_LEGACY_FREE
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit b6435610f579bc53022ec9719f03bb3d75e4594a Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 21:04:13 2014 +1100 mainboard/hp/pavilion_m6_1035dx: Remove HUDSON_LEGACY_FREE The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: Ia487d21faa0fceb2557dbce14ef8822116fada91 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7628 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7628 for details. -gerrit

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Patch merged into coreboot/master: 2963541 util/cbmem: Print name instead of ID of CBMEM_ID_SMM_SAVE_SPACE
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit 29635415a6fadbd9d7bc9b7738babe67f0702db3 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Fri Oct 24 01:15:10 2014 +0200 util/cbmem: Print name instead of ID of CBMEM_ID_SMM_SAVE_SPACE Commit b4b9eb39 (x86: provide infrastructure to backup default SMM region) introduced the new CBMEM type `CBMEM_ID_SMM_SAVE_SPACE`, but did not add its name `SMM BACKUP` to the utility `cbmem`, causing the following output, when running `cbmem` on a system making use of `BACKUP_DEFAULT_SMM_REGION`. 7. 07e9acee 7f7e5000 00010000 Fix that by adding the name `SMM BACKUP` to the struct `cbmem_id_to_name`. Change-Id: Ib24088c07af4daf6b7d8d5854283b5faa2ad6503 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/7176 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7176 for details. -gerrit

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New patch to review for coreboot: 77a1f51 mainboard/lenovo/g505s/romstage.c: Trim off some includes
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7636 -gerrit commit 77a1f51f1f6669fe2a40a8bf4fc04d337e80b5c6 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Dec 3 22:20:40 2014 +1100 mainboard/lenovo/g505s/romstage.c: Trim off some includes Change-Id: Id856f8cbec986806d3aeaeeafba30f1b31a90d8e Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/romstage.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index d142a9d..0d73a42 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -29,15 +29,11 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <cpu/amd/car.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <stdint.h> #include <string.h> #include <southbridge/amd/agesa/hudson/hudson.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - u32 val; agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -54,8 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) report_bist_failure(bist); /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", cpuid_eax(1)); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37);

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Patch set updated for coreboot: 155a4fa mainboard/lenovo/g505s/Kconfig: Toggle some menuconfig options
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7629 -gerrit commit 155a4fab8093ad1bfe7ee20dae1797fa47e55542 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 22:56:17 2014 +1100 mainboard/lenovo/g505s/Kconfig: Toggle some menuconfig options kconfig has a few options on by default that we /do not/ want on and some off that we /do/ want. Toggle these. Change-Id: Idc53738dad6fe48a04d0d872c008e198a9bb3af9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/Kconfig | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index fc3a6ac..efa356b 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -35,6 +35,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select UDELAY_LAPIC + select NO_UART_ON_SUPERIO config MAINBOARD_DIR string @@ -68,4 +69,23 @@ config VGA_BIOS_ID string default "1002,990b" +# # NOTE !!! # +# Disable blobs by-default on board +config HUDSON_IMC_FWM + bool + default n +config HUDSON_XHCI_FWM + bool + default n +config HUDSON_XHCI_ENABLE + bool + default n +# # NOTE !!! # + +# Board does not have a SuperIO UART for serial +# uses EHCI debug port instead! +config USBDEBUG + bool + default y + endif # BOARD_LENOVO_G505S

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Patch merged into coreboot/master: d743e0d mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREE
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit d743e0daf3de88077068c47712d4e5bf12a1732c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 19:35:28 2014 +1100 mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREE The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: I0b4e99cc0d6f89f0261f26ee61b8c175a373c730 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7625 Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7625 for details. -gerrit

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New patch to review for coreboot: 18ec790 build system: fix alignment function
by Patrick Georgi 03 Dec '14

03 Dec '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7635 -gerrit commit 18ec790dfbdc88bcc4de47bd0c49c22705d9efd5 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Wed Dec 3 11:20:51 2014 +0100 build system: fix alignment function It seriously miscomputed alignment values, always off-by-one, and off-by-an-alignment for aligned values. Change-Id: Ide3477d09d34d7728cb0666bb30dd9f7a3f1056d Reported-by: Dave Frodin <dave.frodin(a)se-eng.com> Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 11989d3..880c38d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -91,7 +91,7 @@ $(foreach supported_arch,$(ARCH_SUPPORTED), \ _toint=$(shell printf "%d" $1) _int-add2=$(shell expr $(call _toint,$1) + $(call _toint,$2)) int-add=$(if $(filter 1,$(words $1)),$(strip $1),$(call int-add,$(call _int-add2,$(word 1,$1),$(word 2,$1)) $(wordlist 3,$(words $1),$1))) -int-align=$(shell expr $(call _toint,$1) + $(call _toint,$2) - 1 - $(call _toint,$1) % $(call _toint,$2)) +int-align=$(shell A=$(call _toint,$1) B=$(call _toint,$2); expr $$A + $ \( $$B - \( $$A % $$B $ \) % $$B \) ) file-size=$(shell cat $1 | wc -c) #######################################################################

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coreboot-gerrit December 2014