Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7633
-gerrit
commit de542e0e1a12a42e77430f66850df46b1ca42c8e
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Tue Dec 2 21:51:03 2014 -0700
fsp_baytrail: Allow selection of USB controller by get_option
It was requested to be able to update XHCI vs EHCI via get_option,
so I've added it here for minnow max. This could get moved to the
chipset_fsp_util.c file later, but I'm adding it here for now.
More checking needs to be added to this:
- Are both controllers enabled in devicetree? If not, we don't want
to allow the switch.
Change-Id: I4d8d2229cb9fa0cd9068701454b28ffac6d8e767
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/mainboard/intel/minnowmax/cmos.layout | 6 +++++-
src/mainboard/intel/minnowmax/romstage.c | 11 +++++++++++
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout
index a668188..c7dc88d 100644
--- a/src/mainboard/intel/minnowmax/cmos.layout
+++ b/src/mainboard/intel/minnowmax/cmos.layout
@@ -85,7 +85,8 @@ entries
# coreboot config options: southbridge
408 1 e 1 nmi
409 2 e 7 power_on_after_fail
-#411 5 r 0 unused
+411 2 e 8 use_xhci_over_ehci
+#413 3 r 0 unused
# MRC Scrambler Seed values
896 32 r 0 mrc_scrambler_seed
@@ -133,6 +134,9 @@ enumerations
7 0 Disable
7 1 Enable
7 2 Keep
+8 0 EHCI
+8 1 XHCI
+8 2 Default
# -----------------------------------------------------------------
checksums
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c
index af63cab..a294a00 100644
--- a/src/mainboard/intel/minnowmax/romstage.c
+++ b/src/mainboard/intel/minnowmax/romstage.c
@@ -21,6 +21,8 @@
#include <baytrail/romstage.h>
#include <drivers/intel/fsp/fsp_util.h>
+#include <pc80/mc146818rtc.h>
+#include <console/console.h>
#include "chip.h"
/**
@@ -54,6 +56,7 @@ void late_mainboard_romstage_entry()
void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
{
UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
+ u8 use_xhci = UpdData->PcdEnableXhci;
/*
* Minnow Max Board : 1GB SKU uses 2Gb density memory
@@ -65,5 +68,13 @@ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
UpdData->PcdMemoryParameters.DIMMDensity
+= (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
+ /* Update XHCI UPD value if required */
+ get_option(&use_xhci, "use_xhci_over_ehci");
+ if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
+ UpdData->PcdEnableXhci = use_xhci;
+ printk(FSP_INFO_LEVEL, "Xhci UPDATED:\t\t\t%s\n",
+ UpdData->PcdEnableXhci?"Enabled":"Disabled");
+ }
+
return;
}
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7489
-gerrit
commit 57f22defc5ba08c8f70868db9b3be010408afef9
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Sun Nov 16 20:07:16 2014 -0700
fsp_baytrail: update for UPD_SPD_CHECK macro
Update chipset_fsp_util.c to use the UPD_SPD_CHECK macro. This
makes the code more standardized and easier to read.
Change-Id: I9944e1a4df82e64a205598e98ed0f3b840af1019
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 13 ++-----------
1 file changed, 2 insertions(+), 11 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index 05284e2..bec3c07 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -83,17 +83,8 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
UpdData->AzaliaConfigPtr = (UINT32)&mAzaliaConfig;
/* Set SPD addresses */
- if (config->PcdMrcInitSPDAddr1 == SPD_ADDR_DISABLED)
- UpdData->PcdMrcInitSPDAddr1 = 0x00;
- else if (config->PcdMrcInitSPDAddr1 != SPD_ADDR_DEFAULT)
- UpdData->PcdMrcInitSPDAddr1 = config->PcdMrcInitSPDAddr1;
- printk(BIOS_DEBUG, "SPD Addr1:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr1);
-
- if (config->PcdMrcInitSPDAddr2 == SPD_ADDR_DISABLED)
- UpdData->PcdMrcInitSPDAddr2 = 0x00;
- else if (config->PcdMrcInitSPDAddr2 != SPD_ADDR_DEFAULT)
- UpdData->PcdMrcInitSPDAddr2 = config->PcdMrcInitSPDAddr2;
- printk(BIOS_DEBUG, "SPD Addr2:\t\t0x%02x\n", UpdData->PcdMrcInitSPDAddr2);
+ UPD_SPD_CHECK(PcdMrcInitSPDAddr1);
+ UPD_SPD_CHECK(PcdMrcInitSPDAddr2);
UPD_DEFAULT_CHECK(PcdSataMode);
UPD_DEFAULT_CHECK(PcdLpssSioEnablePciMode);
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7487
-gerrit
commit d94a2c83ffe4a79f283847de84e370aaacc81a09
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Sun Nov 16 17:32:56 2014 -0700
drivers/intel/fsp: add upd macros and #defines
Add macros and #defines for working with the UPD data. This makes
the code look much cleaner.
Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include
the fsp_values header instead. This fixes a conflict.
Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/drivers/intel/fsp/fsp_util.h | 24 ++++++++++++++++++
src/drivers/intel/fsp/fsp_values.h | 41 +++++++++++++++++++++++++++++++
src/northbridge/intel/fsp_rangeley/chip.h | 3 +--
3 files changed, 66 insertions(+), 2 deletions(-)
diff --git a/src/drivers/intel/fsp/fsp_util.h b/src/drivers/intel/fsp/fsp_util.h
index db8b6de..64a5e7f 100644
--- a/src/drivers/intel/fsp/fsp_util.h
+++ b/src/drivers/intel/fsp/fsp_util.h
@@ -21,6 +21,7 @@
#define FSP_UTIL_H
#include <chipset_fsp_util.h>
+#include "fsp_values.h"
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
int save_mrc_data(void *hob_start);
@@ -92,4 +93,27 @@ void update_mrc_cache(void *unused);
extern void *FspHobListPtr;
#endif
+#define UPD_DEFAULT_CHECK(member) \
+ if (config->member != UPD_DEFAULT) { \
+ UpdData->member = config->member - 1; \
+ } \
+ printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
+ config->member ? "(set)" : "(default)");
+
+#define UPD_SPD_CHECK(member) \
+ if (config->member == UPD_SPD_ADDR_DISABLED) { \
+ UpdData->member = 0x00; \
+ } else if (config->member != UPD_SPD_ADDR_DEFAULT) { \
+ UpdData->member = config->member; \
+ } \
+ printk(FSP_INFO_LEVEL, #member ":\t\t0x%02x %s\n", UpdData->member, \
+ config->member ? "(set)" : "(default)");
+
+#define UPD_DEVICE_CHECK(devicename, member, statement) \
+ case devicename: \
+ UpdData->member = dev->enabled; \
+ printk(FSP_INFO_LEVEL, statement "%s\n", \
+ UpdData->member?"Enabled":"Disabled"); \
+ break;
+
#endif /* FSP_UTIL_H */
diff --git a/src/drivers/intel/fsp/fsp_values.h b/src/drivers/intel/fsp/fsp_values.h
new file mode 100644
index 0000000..e5098bb
--- /dev/null
+++ b/src/drivers/intel/fsp/fsp_values.h
@@ -0,0 +1,41 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef FSP_VALUES_H
+#define FSP_VALUES_H
+
+#ifndef FSP_DEBUG_LEVEL
+# define FSP_DEBUG_LEVEL BIOS_SPEW
+#endif
+
+#ifndef FSP_INFO_LEVEL
+# define FSP_INFO_LEVEL BIOS_DEBUG
+#endif
+
+#define INCREMENT_FOR_DEFAULT(x) (x+1)
+
+#define UPD_DEFAULT 0x00
+#define UPD_DISABLE INCREMENT_FOR_DEFAULT(0)
+#define UPD_ENABLE INCREMENT_FOR_DEFAULT(1)
+#define UPD_USE_DEVICETREE 0xff
+
+#define UPD_SPD_ADDR_DEFAULT UPD_DEFAULT
+#define UPD_SPD_ADDR_DISABLED 0xFF
+
+#endif
diff --git a/src/northbridge/intel/fsp_rangeley/chip.h b/src/northbridge/intel/fsp_rangeley/chip.h
index 24609a1..80a22bf 100644
--- a/src/northbridge/intel/fsp_rangeley/chip.h
+++ b/src/northbridge/intel/fsp_rangeley/chip.h
@@ -21,6 +21,7 @@
#define _FSP_RANGELEY_CHIP_H_
#include <arch/acpi.h>
+#include <drivers/intel/fsp/fsp_values.h>
struct northbridge_intel_fsp_rangeley_config {
@@ -36,8 +37,6 @@ struct northbridge_intel_fsp_rangeley_config {
uint8_t SpdBaseAddress_1_0;
uint8_t SpdBaseAddress_1_1;
-#define UPD_ENABLE 1
-#define UPD_DISABLE 0
uint8_t EnableLan;
uint8_t EnableSata2;
uint8_t EnableSata3;
Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7497
-gerrit
commit 28e37e9f39cd43c45dec9740e2cddfc7fdc4345e
Author: Martin Roth <martin.roth(a)se-eng.com>
Date: Sun Nov 16 21:12:16 2014 -0700
fsp_baytrail: Allow selection of USB controller from Kconfig
Allow the selection of EHCI or XHCI from Kconfig instead of just from
the devicetree.
This adds 3 choices:
- Follow devicetree - expects only one of the two controllers to be
enabled in the devicetree, and sets the controller to that mode.
- Use XHCI controller - Selects the XHCI controller and disables the
EHCI controller. The XHCI controller should be enabled in devicetree.
It doesn't matter whether or not the EHCI controller is enabled in
devicetree.
- Use EHCI controller - Selects the EHCI controller and disables the
XHCI controller. The EHCI controller should be enabled in devicetree.
It doesn't matter whether or not the XHCI controller is enabled in
devicetree.
If both EHCI and XHCI controllers are enabled in devicetree, one or
the other should be selected here.
This can be overridden again in the mainboard using CMOS data if
available on that particular platform.
Change-Id: I82d756d5f2ed61b06f936a3f5fcb7a23d43a8244
Signed-off-by: Martin Roth <martin.roth(a)se-eng.com>
---
src/soc/intel/fsp_baytrail/fsp/Kconfig | 26 +++++++++++++++++++++++
src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 8 +++++--
2 files changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig
index 73800d6..cc3c3d0 100644
--- a/src/soc/intel/fsp_baytrail/fsp/Kconfig
+++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig
@@ -39,3 +39,29 @@ config FSP_LOC
The Bay Trail FSP is built with a preferred base address of
0xFFFC0000.
+
+choice
+ prompt "Select the USB Controller to use"
+ default BAYTRAIL_USB_DEVICETREE
+ help
+ This option allows you to select the USB Controller - EHCI or XHCI.
+
+config BAYTRAIL_USB_DEVICETREE
+ bool "Follow devicetree"
+ help
+ Sets the active controller to match the controller that's enabled in
+ the devicetree.cb file.
+
+config BAYTRAIL_USB_XHCI
+ bool "Use XHCI controller"
+ help
+ Sets the active controller to XHCI. The XHCI controller must be enabled
+ in devicetree. The EHCI controller will be ignored if it's enabled.
+
+config BAYTRAIL_USB_EHCI
+ bool "Use EHCI controller"
+ help
+ Sets the active controller to EHCI. The EHCI controller must be enabled
+ in devicetree. The XHCI controller will be ignored if it's enabled.
+endchoice
+
diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
index c6b5f9c..402e2f9 100644
--- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
+++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c
@@ -188,10 +188,14 @@ static void ConfigureDefaultUpdData(FSP_INFO_HEADER *FspInfo, UPD_DATA_REGION *U
UpdData->PcdeMMCBootMode = EMMC_4_5 - EMMC_DISABLED;
break;
case XHCI_DEV_FUNC:
- UpdData->PcdEnableXhci = dev->enabled;
+ if (CONFIG_BAYTRAIL_USB_XHCI ||
+ (CONFIG_BAYTRAIL_USB_DEVICETREE && dev->enabled))
+ UpdData->PcdEnableXhci = 1;
break;
case EHCI_DEV_FUNC:
- UpdData->PcdEnableXhci = !(dev->enabled);
+ if (CONFIG_BAYTRAIL_USB_EHCI ||
+ (CONFIG_BAYTRAIL_USB_DEVICETREE && dev->enabled))
+ UpdData->PcdEnableXhci = 0;
break;
case LPE_DEV_FUNC: