coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

1 participants
1346 discussions

Patch merged into coreboot/master: 546953c Replace hlt with halt()
by gerrit＠coreboot.org 02 Dec '14

02 Dec '14

the following patch was just integrated into master: commit 546953c0c553465761705fb0747964c08d634461 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 29 10:38:17 2014 +0100 Replace hlt with halt() There were instances of unneeded arch/hlt.h includes, various hlt() calls that weren't supposed to exit (but might have) and various forms of endless loops around hlt() calls. All these are sorted out now: unnecessary includes are dropped, hlt() is uniformly replaced with halt() (except in assembly, obviously). Change-Id: I3d38fed6e8d67a28fdeb17be803d8c4b62d383c5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/7608 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7608 for details. -gerrit

1 0

New patch to review for coreboot: e5b6cde superio/smsc/sch311x: New superio support
by Damien Zammit 02 Dec '14

02 Dec '14

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7626 -gerrit commit e5b6cde6be960deb26c1b3e426bfad32b8634fa6 Author: Damien Zammit <damien(a)zamaudio.com> Date: Tue Dec 2 20:24:31 2014 +1100 superio/smsc/sch311x: New superio support Add support for the SCH3112, SCH3114 and SCH3116 super I/Os. Includes a command to share all 2-6 serial ports among a single IRQ. Change-Id: I759d458bb03e145a68fe04617521ce079cc2be2f Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/superio/smsc/Kconfig | 2 + src/superio/smsc/Makefile.inc | 1 + src/superio/smsc/sch311x/Makefile.inc | 21 ++++++++ src/superio/smsc/sch311x/sch311x.h | 36 +++++++++++++ src/superio/smsc/sch311x/sch311x_early_init.c | 73 +++++++++++++++++++++++++++ src/superio/smsc/sch311x/superio.c | 66 ++++++++++++++++++++++++ 6 files changed, 199 insertions(+) diff --git a/src/superio/smsc/Kconfig b/src/superio/smsc/Kconfig index 6aaa112..a47d127 100644 --- a/src/superio/smsc/Kconfig +++ b/src/superio/smsc/Kconfig @@ -47,5 +47,7 @@ config SUPERIO_SMSC_SMSCSUPERIO select SUPERIO_WANTS_14MHZ_CLOCK config SUPERIO_SMSC_SIO1036 bool +config SUPERIO_SMSC_SCH311X + bool config SUPERIO_SMSC_SCH4037 bool diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index a89b6ac..2397d6c 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -32,4 +32,5 @@ subdirs-y += kbc1100 subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 +subdirs-y += sch311x subdirs-y += sch4037 diff --git a/src/superio/smsc/sch311x/Makefile.inc b/src/superio/smsc/sch311x/Makefile.inc new file mode 100644 index 0000000..de0e724 --- /dev/null +++ b/src/superio/smsc/sch311x/Makefile.inc @@ -0,0 +1,21 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +# + +romstage-$(CONFIG_SUPERIO_SMSC_SCH311X) += sch311x_early_init.c +ramstage-$(CONFIG_SUPERIO_SMSC_SCH311X) += superio.c diff --git a/src/superio/smsc/sch311x/sch311x.h b/src/superio/smsc/sch311x/sch311x.h new file mode 100644 index 0000000..987e2dd --- /dev/null +++ b/src/superio/smsc/sch311x/sch311x.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef SUPERIO_SCH_311X_H +#define SUPERIO_SCH_311X_H + +#define SCH311X_FDD 0 /* FDD */ +#define SCH311X_LPT 3 /* LPT */ +#define SMSCSUPERIO_SP1 4 /* Com1 */ +#define SMSCSUPERIO_SP2 5 /* Com2 */ +#define SCH311X_KBC 7 /* KBC */ +#define SCH311X_RUNTIME 0x0A /* Runtime */ +#define SMSCSUPERIO_SP3 0x0B /* Com3 */ +#define SMSCSUPERIO_SP4 0x0C /* Com4 */ +#define SMSCSUPERIO_SP5 0x0D /* Com5 */ +#define SMSCSUPERIO_SP6 0x0E /* Com6 */ + +void sch311x_early_init(unsigned port); + +#endif /* SUPERIO_SCH_311X_H */ diff --git a/src/superio/smsc/sch311x/sch311x_early_init.c b/src/superio/smsc/sch311x/sch311x_early_init.c new file mode 100644 index 0000000..c1b41ba --- /dev/null +++ b/src/superio/smsc/sch311x/sch311x_early_init.c @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <arch/io.h> +#include <device/pnp.h> +#include <stdint.h> + +#include "sch311x.h" + +static void pnp_enter_conf_state(pnp_devfn_t dev) +{ + unsigned port = dev >> 8; + outb(0x55, port); +} + +static void pnp_exit_conf_state(pnp_devfn_t dev) +{ + unsigned port = dev >> 8; + outb(0xaa, port); +} + +void sch311x_early_init(unsigned port) +{ + pnp_devfn_t dev; + + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_enter_conf_state(dev); + + /* Auto power management */ + pnp_write_config(dev, 0x22, 0x38); /* BIT3+BIT4+BIT5 */ + pnp_write_config(dev, 0x23, 0 ); + + /* Enable SMSC UART 0 */ + dev = PNP_DEV(port, SMSCSUPERIO_SP1); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + + pnp_set_iobase(dev, PNP_IDX_IO0, CONFIG_TTYS0_BASE); + pnp_set_irq(dev, PNP_IDX_IRQ0, 0x4); + + /* Enable High speed, disable MIDI support, + * Share 1x IRQ among all serial ports */ + pnp_write_config(dev, 0xF0, 0xC2); + pnp_set_enable(dev, 1); + + /* Enable keyboard */ + dev = PNP_DEV(port, SCH311X_KBC); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_irq(dev, 0x70, 1); /* IRQ 1 */ + pnp_set_irq(dev, 0x72, 12); /* IRQ 12 */ + pnp_set_enable(dev, 1); + + pnp_exit_conf_state(dev); +} diff --git a/src/superio/smsc/sch311x/superio.c b/src/superio/smsc/sch311x/superio.c new file mode 100644 index 0000000..8f17a12 --- /dev/null +++ b/src/superio/smsc/sch311x/superio.c @@ -0,0 +1,66 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* RAM driver for the SMSC SCH311X Super I/O chip */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <pc80/keyboard.h> +#include <stdlib.h> + +#include "sch311x.h" + +static void sch311x_init(struct device *dev) +{ + if (!dev->enabled) { + return; + } + + switch(dev->path.pnp.device) { + case SCH311X_KBC: + pc_keyboard_init(); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = sch311x_init, + .ops_pnp_mode = &pnp_conf_mode_55_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + { &ops, SCH311X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_smsc_sch311x_ops = { + CHIP_NAME("SMSC SCH311x Super I/O") + .enable_dev = enable_dev, +};

1 0

Patch merged into coreboot/master: 24cca75 build system: remove ROMSTAGE_ELF variable
by gerrit＠coreboot.org 02 Dec '14

02 Dec '14

the following patch was just integrated into master: commit 24cca75b47f516e2ad226c37da1e71aef5036fce Author: Patrick Georgi <pgeorgi(a)google.com> Date: Sat Nov 29 11:51:25 2014 +0100 build system: remove ROMSTAGE_ELF variable No need to keep that just because x86 has one extra linking step. Change-Id: Iffdbf64e0613f89070ed0dfb009379f5ca0bd3c1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-on: http://review.coreboot.org/7611 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7611 for details. -gerrit

1 0

Patch set updated for coreboot: 4c92e32 nvramtool: make sure that strings are 0-terminated
by Patrick Georgi 02 Dec '14

02 Dec '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7621 -gerrit commit 4c92e32519e979b7ed8a407cc311a7985480c4f0 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Dec 1 22:09:33 2014 +0100 nvramtool: make sure that strings are 0-terminated The call site expects them to be. Change-Id: Ic05fc5831f5743d94fe617dfb3b9e329f01866d1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/nvramtool/cmos_lowlevel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/nvramtool/cmos_lowlevel.c b/util/nvramtool/cmos_lowlevel.c index c46e480..32f0e0a 100644 --- a/util/nvramtool/cmos_lowlevel.c +++ b/util/nvramtool/cmos_lowlevel.c @@ -128,7 +128,7 @@ unsigned long long cmos_read(const cmos_entry_t * e) result = 0; if (e->config == CMOS_ENTRY_STRING) { - int strsz = (length + 7) / 8; + int strsz = (length + 7) / 8 + 1; char *newstring = malloc(strsz); unsigned usize = (8 * sizeof(unsigned long long));

1 0

Patch set updated for coreboot: 35b7eae Drop tianocoreboot ("Project PIANO")
by Patrick Georgi 02 Dec '14

02 Dec '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7622 -gerrit commit 35b7eaec6b97af88d23f45d329828df93a7d772c Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Dec 1 22:18:26 2014 +0100 Drop tianocoreboot ("Project PIANO") There are four other approaches to provide UEFI on top of coreboot that actually get to a UEFI shell. No need to keep this experiment and confuse users. Change-Id: I81c52e24099852f6daf0d5725aec707bdfd75ae1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- payloads/tianocoreboot/Makefile | 80 ---- payloads/tianocoreboot/README | 27 -- payloads/tianocoreboot/include/BootMode.h | 38 -- .../include/EfiFirmwareVolumeHeader.h | 213 --------- payloads/tianocoreboot/include/EfiTypes.h | 297 ------------ .../tianocoreboot/include/MemoryAllocationHob.h | 34 -- payloads/tianocoreboot/include/PeiHob.h | 257 ---------- payloads/tianocoreboot/include/PiFirmwareFile.h | 494 ------------------- payloads/tianocoreboot/include/coff.h | 106 ----- payloads/tianocoreboot/include/efi.h | 36 -- payloads/tianocoreboot/libpayload.config | 81 ---- payloads/tianocoreboot/tianocoreboot.c | 529 --------------------- 12 files changed, 2192 deletions(-) diff --git a/payloads/tianocoreboot/Makefile b/payloads/tianocoreboot/Makefile deleted file mode 100644 index 3ac541f..0000000 --- a/payloads/tianocoreboot/Makefile +++ /dev/null @@ -1,80 +0,0 @@ -## -## This file is part of the TianoCoreBoot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -src := $(shell pwd) -srctree := $(src) -obj ?= $(src)/build - -export V := $(V) - -CONFIG_SHELL := sh -UNAME_RELEASE := $(shell uname -r) -HAVE_DOTCONFIG := $(wildcard .config) -MAKEFLAGS += -rR --no-print-directory - -# Make is silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -LIBCONFIG_PATH := ../libpayload -LIBPAYLOAD_DIR := $(obj)/libpayload -LPCC := $(LIBPAYLOAD_DIR)/libpayload/bin/lpgcc -LPAS := $(LIBPAYLOAD_DIR)/libpayload/bin/lpas -HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/libpayload/lib/libpayload.a) -OBJCOPY ?= objcopy - -INCLUDES = -Iinclude -CFLAGS := -Wall -Werror -Os $(INCLUDES) -OBJECTS = tianocoreboot.o -OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) -TARGET = $(obj)/tianocoreboot.elf - -all: $(TARGET) - -$(TARGET): prepare $(OBJS) libpayload - $(Q)printf " LINK $(subst $(shell pwd)/,,$(@))\n" - $(Q)CC="$(CC)" $(LPCC) -o $@ $(OBJS) - $(Q)$(OBJCOPY) --only-keep-debug $@ $(TARGET).debug - $(Q)$(OBJCOPY) --strip-debug $@ - $(Q)$(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ - -$(obj)/%.o: $(src)/%.c libpayload - $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)CC="$(CC)" $(LPCC) $(CFLAGS) -c -o $@ $< - -ifneq ($(strip $(HAVE_LIBPAYLOAD)),) -libpayload: - $(Q)printf "Found Libpayload $(LIBPAYLOAD_DIR).\n" -else -libpayload: - $(Q)printf "Building libpayload @ $(LIBCONFIG_PATH).\n" - $(Q)cp libpayload.config .config - $(Q)make -C $(LIBCONFIG_PATH) distclean - $(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(LIBPAYLOAD_DIR) install DOTCONFIG=$(shell pwd)/.config -endif - -prepare: - $(Q)mkdir -p $(obj) - -clean: - $(Q)rm -rf $(obj) $(LIBPAYLOAD_DIR) .xcompile .config .config.old - -.PHONY: $(PHONY) clean - diff --git a/payloads/tianocoreboot/README b/payloads/tianocoreboot/README deleted file mode 100644 index 0dce08b..0000000 --- a/payloads/tianocoreboot/README +++ /dev/null @@ -1,27 +0,0 @@ -mkdir Tiano -cd Tiano -svn co https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2 edk2 --username guest -cd edk2 -svn co https://edk2-fatdriver2.svn.sourceforge.net/svnroot/edk2-fatdriver2/trunk/F… FatPkg --username guest -cd .. - -make -C edk2/BaseTools - -export EDK_TOOLS_PATH=$(pwd)/edk2/BaseTools -cd edk2 -. ./edksetup.sh BaseTools - -vi Conf/target.txt - -ACTIVE_PLATFORM = OvmfPkg/OvmfPkgIa32.dsc -TOOL_CHAIN_TAG = GCC46 - ------- -#TODO -TARGET_ARCH = IA32 X64 ------- - -build -D DEBUG_ON_SERIAL_PORT - ---> ./Build/OvmfIa32/DEBUG_GCC46/FV/DXEFV.Fv - diff --git a/payloads/tianocoreboot/include/BootMode.h b/payloads/tianocoreboot/include/BootMode.h deleted file mode 100644 index 38b7c0c..0000000 --- a/payloads/tianocoreboot/include/BootMode.h +++ /dev/null @@ -1,38 +0,0 @@ -/*++ - -Copyright (c) 2004, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - BootMode.h - -Abstract: - - This includes for the Boot mode information. - ---*/ - -#ifndef _EFI_BOOT_MODE_H -#define _EFI_BOOT_MODE_H - -#define BOOT_WITH_FULL_CONFIGURATION 0x00 -#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01 -#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02 -#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03 -#define BOOT_WITH_DEFAULT_SETTINGS 0x04 -#define BOOT_ON_S4_RESUME 0x05 -#define BOOT_ON_S5_RESUME 0x06 -#define BOOT_ON_S2_RESUME 0x10 -#define BOOT_ON_S3_RESUME 0x11 -#define BOOT_ON_FLASH_UPDATE 0x12 -#define BOOT_IN_RECOVERY_MODE 0x20 -#define BOOT_IN_RECOVERY_MODE_MASK 0x40 -#define BOOT_SPECIAL_MASK 0x80 -#endif diff --git a/payloads/tianocoreboot/include/EfiFirmwareVolumeHeader.h b/payloads/tianocoreboot/include/EfiFirmwareVolumeHeader.h deleted file mode 100644 index 9bbab35..0000000 --- a/payloads/tianocoreboot/include/EfiFirmwareVolumeHeader.h +++ /dev/null @@ -1,213 +0,0 @@ -/*++ - -Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - EfiFirmwareVolumeHeader.h - -Abstract: - - Defines data structure that is the volume header found at the beginning of - all firmware volumes that are either memory mapped, or have an - associated FirmwareVolumeBlock protocol. - ---*/ - -#ifndef _EFI_FIRMWARE_VOLUME_HEADER_H_ -#define _EFI_FIRMWARE_VOLUME_HEADER_H_ - - -// -// Firmware Volume Block Attributes bit definitions -// They are the shared between Framework and PI1.0. -// -typedef UINT32 EFI_FVB_ATTRIBUTES; - -#define EFI_FVB_READ_DISABLED_CAP 0x00000001 -#define EFI_FVB_READ_ENABLED_CAP 0x00000002 -#define EFI_FVB_READ_STATUS 0x00000004 - -#define EFI_FVB_WRITE_DISABLED_CAP 0x00000008 -#define EFI_FVB_WRITE_ENABLED_CAP 0x00000010 -#define EFI_FVB_WRITE_STATUS 0x00000020 - -#define EFI_FVB_LOCK_CAP 0x00000040 -#define EFI_FVB_LOCK_STATUS 0x00000080 - -#define EFI_FVB_STICKY_WRITE 0x00000200 -#define EFI_FVB_MEMORY_MAPPED 0x00000400 -#define EFI_FVB_ERASE_POLARITY 0x00000800 - - -#if (PI_SPECIFICATION_VERSION < 0x00010000) - -#define EFI_FVB_ALIGNMENT_CAP 0x00008000 -#define EFI_FVB_ALIGNMENT_2 0x00010000 -#define EFI_FVB_ALIGNMENT_4 0x00020000 -#define EFI_FVB_ALIGNMENT_8 0x00040000 -#define EFI_FVB_ALIGNMENT_16 0x00080000 -#define EFI_FVB_ALIGNMENT_32 0x00100000 -#define EFI_FVB_ALIGNMENT_64 0x00200000 -#define EFI_FVB_ALIGNMENT_128 0x00400000 -#define EFI_FVB_ALIGNMENT_256 0x00800000 -#define EFI_FVB_ALIGNMENT_512 0x01000000 -#define EFI_FVB_ALIGNMENT_1K 0x02000000 -#define EFI_FVB_ALIGNMENT_2K 0x04000000 -#define EFI_FVB_ALIGNMENT_4K 0x08000000 -#define EFI_FVB_ALIGNMENT_8K 0x10000000 -#define EFI_FVB_ALIGNMENT_16K 0x20000000 -#define EFI_FVB_ALIGNMENT_32K 0x40000000 -#define EFI_FVB_ALIGNMENT_64K 0x80000000 - -#define EFI_FVB_CAPABILITIES (EFI_FVB_READ_DISABLED_CAP | \ - EFI_FVB_READ_ENABLED_CAP | \ - EFI_FVB_WRITE_DISABLED_CAP | \ - EFI_FVB_WRITE_ENABLED_CAP | \ - EFI_FVB_LOCK_CAP \ - ) - -#define EFI_FVB_STATUS (EFI_FVB_READ_STATUS | EFI_FVB_WRITE_STATUS | EFI_FVB_LOCK_STATUS) - - - -#else - -#define EFI_FVB2_READ_LOCK_CAP 0x00001000 -#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 - -#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 -#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 - -#define EFI_FVB2_ALIGNMENT 0x001F0000 -#define EFI_FVB2_ALIGNMENT_1 0x00000000 -#define EFI_FVB2_ALIGNMENT_2 0x00010000 -#define EFI_FVB2_ALIGNMENT_4 0x00020000 -#define EFI_FVB2_ALIGNMENT_8 0x00030000 -#define EFI_FVB2_ALIGNMENT_16 0x00040000 -#define EFI_FVB2_ALIGNMENT_32 0x00050000 -#define EFI_FVB2_ALIGNMENT_64 0x00060000 -#define EFI_FVB2_ALIGNMENT_128 0x00070000 -#define EFI_FVB2_ALIGNMENT_256 0x00080000 -#define EFI_FVB2_ALIGNMENT_512 0x00090000 -#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 -#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 -#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 -#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 -#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 -#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 -#define EFI_FVB2_ALIGNMENT_64K 0x00100000 -#define EFI_FVB2_ALIGNMENT_128K 0x00110000 -#define EFI_FVB2_ALIGNMENT_256K 0x00120000 -#define EFI_FVB2_ALIGNMENT_512K 0x00130000 -#define EFI_FVB2_ALIGNMENT_1M 0x00140000 -#define EFI_FVB2_ALIGNMENT_2M 0x00150000 -#define EFI_FVB2_ALIGNMENT_4M 0x00160000 -#define EFI_FVB2_ALIGNMENT_8M 0x00170000 -#define EFI_FVB2_ALIGNMENT_16M 0x00180000 -#define EFI_FVB2_ALIGNMENT_32M 0x00190000 -#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 -#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 -#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 -#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 -#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 -#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 - -#define EFI_FVB_CAPABILITIES (EFI_FVB_READ_DISABLED_CAP | \ - EFI_FVB_READ_ENABLED_CAP | \ - EFI_FVB_WRITE_DISABLED_CAP | \ - EFI_FVB_WRITE_ENABLED_CAP | \ - EFI_FVB_LOCK_CAP | \ - EFI_FVB2_READ_LOCK_CAP | \ - EFI_FVB2_WRITE_LOCK_CAP ) - -#define EFI_FVB_STATUS (EFI_FVB_READ_STATUS | EFI_FVB_WRITE_STATUS | \ - EFI_FVB_LOCK_STATUS | EFI_FVB2_READ_LOCK_STATUS | \ - EFI_FVB2_WRITE_LOCK_STATUS ) - - - -// -// Extended Header Header. Located via ExtHeaderOffset. -// The extended headers follow each other in memory and are -// terminated by ExtHeaderType EFI_FV_EXT_TYPE_END -// -#define EFI_FV_EXT_TYPE_END 0x00 -typedef struct { - UINT16 ExtEntrySize; - UINT16 ExtEntryType; -} EFI_FIRMWARE_VOLUME_EXT_ENTRY; - -// -// GUID that maps OEM file types to GUIDs -// -#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01 -typedef struct { - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - UINT32 TypeMask; - EFI_GUID Types[1]; -} EFI_FIRMWARE_VOLUME_EXT_HEADER_OEM_TYPE; - -// -// Unique name of the FV -// -typedef struct { - EFI_GUID FvName; - UINT32 ExtHeaderSize; -} EFI_FIRMWARE_VOLUME_EXT_HEADER; - - -#endif - - -// -// Firmware Volume Header Revision definition -// -#define EFI_FVH_REVISION 0x01 -// -// PI1.0 define Firmware Volume Header Revision to 2 -// -#define EFI_FVH_PI_REVISION 0x02 - -// -// Firmware Volume Header Signature definition -// -#define EFI_FVH_SIGNATURE EFI_SIGNATURE_32 ('_', 'F', 'V', 'H') - -// -// Firmware Volume Header Block Map Entry definition -// -typedef struct { - UINT32 NumBlocks; - UINT32 BlockLength; -} EFI_FV_BLOCK_MAP_ENTRY; - -// -// Firmware Volume Header definition -// -typedef struct { - UINT8 ZeroVector[16]; - EFI_GUID FileSystemGuid; - UINT64 FvLength; - UINT32 Signature; - EFI_FVB_ATTRIBUTES Attributes; - UINT16 HeaderLength; - UINT16 Checksum; -#if (PI_SPECIFICATION_VERSION < 0x00010000) - UINT8 Reserved[3]; -#else - UINT16 ExtHeaderOffset; - UINT8 Reserved[1]; -#endif - UINT8 Revision; - EFI_FV_BLOCK_MAP_ENTRY FvBlockMap[1]; -} EFI_FIRMWARE_VOLUME_HEADER; - -#endif diff --git a/payloads/tianocoreboot/include/EfiTypes.h b/payloads/tianocoreboot/include/EfiTypes.h deleted file mode 100644 index 49760d3..0000000 --- a/payloads/tianocoreboot/include/EfiTypes.h +++ /dev/null @@ -1,297 +0,0 @@ -/*++ - -Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - EfiTypes.h - -Abstract: - - EFI defined types. Use these types when ever possible! - ---*/ - -#ifndef _EFI_TYPES_H_ -#define _EFI_TYPES_H_ - -// -// EFI Data Types based on ANSI C integer types in EfiBind.h -// -typedef uint8_t BOOLEAN; -typedef intn_t INTN; -typedef uintn_t UINTN; -typedef int8_t INT8; -typedef uint8_t UINT8; -typedef int16_t INT16; -typedef uint16_t UINT16; -typedef int32_t INT32; -typedef uint32_t UINT32; -typedef int64_t INT64; -typedef uint64_t UINT64; -typedef char CHAR8; -typedef uint16_t CHAR16; -typedef UINT64 EFI_LBA; - -// -// Modifiers for EFI Data Types used to self document code. -// Please see EFI coding convention for proper usage. -// -#ifndef IN -// -// Some other envirnments use this construct, so #ifndef to prevent -// mulitple definition. -// -#define IN -#define OUT -#define OPTIONAL -#endif - -#ifndef UNALIGNED -#define UNALIGNED -#endif - -// -// Modifiers for EFI Runtime and Boot Services -// -#define EFI_RUNTIMESERVICE -#define EFI_BOOTSERVICE - -// -// Boot Service add in EFI 1.1 -// -#define EFI_BOOTSERVICE11 - -// -// Modifiers to absract standard types to aid in debug of problems -// -#define CONST const -#define STATIC static -#define VOID void -#define VOLATILE volatile - -// -// Modifier to ensure that all protocol member functions and EFI intrinsics -// use the correct C calling convention. All protocol member functions and -// EFI intrinsics are required to modify thier member functions with EFIAPI. -// -#ifndef EFIAPI - #define EFIAPI _EFIAPI -#endif - -// -// EFI Constants. They may exist in other build structures, so #ifndef them. -// -#ifndef TRUE -#define TRUE ((BOOLEAN) (1 == 1)) -#endif - -#ifndef FALSE -#define FALSE ((BOOLEAN) (0 == 1)) -#endif - -#ifndef NULL -#define NULL ((VOID *) 0) -#endif -// -// EFI Data Types derived from other EFI data types. -// -typedef UINTN EFI_STATUS; - -typedef VOID *EFI_HANDLE; -#define NULL_HANDLE ((VOID *) 0) - -typedef VOID *EFI_EVENT; -typedef UINTN EFI_TPL; - -typedef struct { - UINT32 Data1; - UINT16 Data2; - UINT16 Data3; - UINT8 Data4[8]; -} EFI_GUID; - -typedef union { - EFI_GUID Guid; - UINT8 Raw[16]; -} EFI_GUID_UNION; - -// -// EFI Time Abstraction: -// Year: 2000 - 20XX -// Month: 1 - 12 -// Day: 1 - 31 -// Hour: 0 - 23 -// Minute: 0 - 59 -// Second: 0 - 59 -// Nanosecond: 0 - 999,999,999 -// TimeZone: -1440 to 1440 or 2047 -// -typedef struct { - UINT16 Year; - UINT8 Month; - UINT8 Day; - UINT8 Hour; - UINT8 Minute; - UINT8 Second; - UINT8 Pad1; - UINT32 Nanosecond; - INT16 TimeZone; - UINT8 Daylight; - UINT8 Pad2; -} EFI_TIME; - -// -// Bit definitions for EFI_TIME.Daylight -// -#define EFI_TIME_ADJUST_DAYLIGHT 0x01 -#define EFI_TIME_IN_DAYLIGHT 0x02 - -// -// Value definition for EFI_TIME.TimeZone -// -#define EFI_UNSPECIFIED_TIMEZONE 0x07FF - -// -// Networking -// -typedef struct { - UINT8 Addr[4]; -} EFI_IPv4_ADDRESS; - -typedef struct { - UINT8 Addr[16]; -} EFI_IPv6_ADDRESS; - -typedef struct { - UINT8 Addr[32]; -} EFI_MAC_ADDRESS; - -typedef union { - UINT32 Addr[4]; - EFI_IPv4_ADDRESS v4; - EFI_IPv6_ADDRESS v6; -} EFI_IP_ADDRESS; - -typedef enum { - EfiReservedMemoryType, - EfiLoaderCode, - EfiLoaderData, - EfiBootServicesCode, - EfiBootServicesData, - EfiRuntimeServicesCode, - EfiRuntimeServicesData, - EfiConventionalMemory, - EfiUnusableMemory, - EfiACPIReclaimMemory, - EfiACPIMemoryNVS, - EfiMemoryMappedIO, - EfiMemoryMappedIOPortSpace, - EfiPalCode, - EfiMaxMemoryType -} EFI_MEMORY_TYPE; - -typedef enum { - AllocateAnyPages, - AllocateMaxAddress, - AllocateAddress, - MaxAllocateType -} EFI_ALLOCATE_TYPE; - -typedef struct { - UINT64 Signature; - UINT32 Revision; - UINT32 HeaderSize; - UINT32 CRC32; - UINT32 Reserved; -} EFI_TABLE_HEADER; - -// -// possible caching types for the memory range -// -#define EFI_MEMORY_UC 0x0000000000000001 -#define EFI_MEMORY_WC 0x0000000000000002 -#define EFI_MEMORY_WT 0x0000000000000004 -#define EFI_MEMORY_WB 0x0000000000000008 -#define EFI_MEMORY_UCE 0x0000000000000010 - -// -// physical memory protection on range -// -#define EFI_MEMORY_WP 0x0000000000001000 -#define EFI_MEMORY_RP 0x0000000000002000 -#define EFI_MEMORY_XP 0x0000000000004000 - -// -// range requires a runtime mapping -// -#define EFI_MEMORY_RUNTIME 0x8000000000000000ULL - -typedef UINT64 EFI_PHYSICAL_ADDRESS; -typedef UINT64 EFI_VIRTUAL_ADDRESS; - -#define EFI_MEMORY_DESCRIPTOR_VERSION 1 -typedef struct { - UINT32 Type; - UINT32 Pad; - EFI_PHYSICAL_ADDRESS PhysicalStart; - EFI_VIRTUAL_ADDRESS VirtualStart; - UINT64 NumberOfPages; - UINT64 Attribute; -} EFI_MEMORY_DESCRIPTOR; - -// -// The EFI memory allocation functions work in units of EFI_PAGEs that are -// 4K. This should in no way be confused with the page size of the processor. -// An EFI_PAGE is just the quanta of memory in EFI. -// -#define EFI_PAGE_SIZE 4096 -#define EFI_PAGE_MASK 0xFFF -#define EFI_PAGE_SHIFT 12 - -#define EFI_SIZE_TO_PAGES(a) (((a) >> EFI_PAGE_SHIFT) + (((a) & EFI_PAGE_MASK) ? 1 : 0)) - -#define EFI_PAGES_TO_SIZE(a) ( (a) << EFI_PAGE_SHIFT) - -// -// ALIGN_POINTER - aligns a pointer to the lowest boundry -// -#define ALIGN_POINTER(p, s) ((VOID *) (p + ((s - ((UINTN) p)) & (s - 1)))) - -// -// ALIGN_VARIABLE - aligns a variable up to the next natural boundry for int size of a processor -// -#define ALIGN_VARIABLE(Value, Adjustment) \ - (UINTN) Adjustment = 0; \ - if ((UINTN) Value % sizeof (UINTN)) { \ - (UINTN) Adjustment = sizeof (UINTN) - ((UINTN) Value % sizeof (UINTN)); \ - } \ - Value = (UINTN) Value + (UINTN) Adjustment - -// -// EFI_FIELD_OFFSET - returns the byte offset to a field within a structure -// -#define EFI_FIELD_OFFSET(TYPE,Field) ((UINTN)(&(((TYPE *) 0)->Field))) - -// -// CONTAINING_RECORD - returns a pointer to the structure -// from one of it's elements. -// -#define _CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - (CHAR8 *) &(((TYPE *) 0)->Field))) - -// -// Define macros to build data structure signatures from characters. -// -#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8)) -#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16)) -#define EFI_SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (EFI_SIGNATURE_32 (A, B, C, D) | ((UINT64) (EFI_SIGNATURE_32 (E, F, G, H)) << 32)) - -#endif diff --git a/payloads/tianocoreboot/include/MemoryAllocationHob.h b/payloads/tianocoreboot/include/MemoryAllocationHob.h deleted file mode 100644 index fb06757..0000000 --- a/payloads/tianocoreboot/include/MemoryAllocationHob.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @file - GUIDs for HOBs used in memory allcation - - Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved. - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - @par Revision Reference: - GUIDs introduced in PI Version 1.0. - -**/ - -#ifndef __MEMORY_ALLOCATION_GUID_H__ -#define __MEMORY_ALLOCATION_GUID_H__ - -#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \ - {0x564b33cd, 0xc92a, 0x4593, {0x90, 0xbf, 0x24, 0x73, 0xe4, 0x3c, 0x63, 0x22} }; - -#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \ - {0x4ed4bf27, 0x4092, 0x42e9, {0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x0, 0xc9, 0xbd} } - -#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \ - {0xf8e21975, 0x899, 0x4f58, {0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a} } - -extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid; -extern EFI_GUID gEfiHobMemoryAllocStackGuid; -extern EFI_GUID gEfiHobMemoryAllocModuleGuid; - -#endif diff --git a/payloads/tianocoreboot/include/PeiHob.h b/payloads/tianocoreboot/include/PeiHob.h deleted file mode 100644 index 407ea76..0000000 --- a/payloads/tianocoreboot/include/PeiHob.h +++ /dev/null @@ -1,257 +0,0 @@ -/*++ - -Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - PeiHob.h - -Abstract: - - PEI Hand Off Block (HOB) definition. - - The HOB is a memory data structure used to hand-off system information from - PEI to DXE (the next phase). - ---*/ - -#ifndef _PEI_HOB_H_ -#define _PEI_HOB_H_ - -#include "BootMode.h" - -// -// Every Hob must start with this data structure. -// -typedef struct { - UINT16 HobType; - UINT16 HobLength; - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -// -// End of HOB List HOB -// -#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff - -// -// Handoff Information Table HOB -// -#define EFI_HOB_TYPE_HANDOFF 0x0001 - -#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009 - -typedef UINT32 EFI_BOOT_MODE; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - UINT32 Version; - EFI_BOOT_MODE BootMode; - EFI_PHYSICAL_ADDRESS EfiMemoryTop; - EFI_PHYSICAL_ADDRESS EfiMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiEndOfHobList; -} EFI_HOB_HANDOFF_INFO_TABLE; - -// -// Memory Descriptor HOB -// -#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 - -typedef struct { - EFI_GUID Name; - EFI_PHYSICAL_ADDRESS MemoryBaseAddress; - UINT64 MemoryLength; - EFI_MEMORY_TYPE MemoryType; - UINT8 Reserved[4]; -} EFI_HOB_MEMORY_ALLOCATION_HEADER; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; - // - // Additional data pertaining to the "Name" Guid memory - // may go here. - // -} EFI_HOB_MEMORY_ALLOCATION; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; -} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; -} EFI_HOB_MEMORY_ALLOCATION_STACK; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader; - EFI_GUID ModuleName; - EFI_PHYSICAL_ADDRESS EntryPoint; -} EFI_HOB_MEMORY_ALLOCATION_MODULE; - -#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 - -typedef UINT32 EFI_RESOURCE_TYPE; - -#define EFI_RESOURCE_SYSTEM_MEMORY 0 -#define EFI_RESOURCE_MEMORY_MAPPED_IO 1 -#define EFI_RESOURCE_IO 2 -#define EFI_RESOURCE_FIRMWARE_DEVICE 3 -#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 4 -#define EFI_RESOURCE_MEMORY_RESERVED 5 -#define EFI_RESOURCE_IO_RESERVED 6 -#define EFI_RESOURCE_MAX_MEMORY_TYPE 7 - -typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; - -#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 -#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 -#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 -#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008 -#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040 -#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100 -#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000 -#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000 -#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000 -#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000 -// -// The following values are defined in PI 1.2 errata B. -// -#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000 -#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_GUID Owner; - EFI_RESOURCE_TYPE ResourceType; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - EFI_PHYSICAL_ADDRESS PhysicalStart; - UINT64 ResourceLength; -} EFI_HOB_RESOURCE_DESCRIPTOR; - -// -// GUID Extension HOB -// The HobLength is variable as it includes the GUID specific data. -// -#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_GUID Name; - - // - // Guid specific data goes here - // -} EFI_HOB_GUID_TYPE; - -// -// Firmware Volume HOB -// -#define EFI_HOB_TYPE_FV 0x0005 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 Length; -} EFI_HOB_FIRMWARE_VOLUME; - -// -// CPU HOB -// -#define EFI_HOB_TYPE_CPU 0x0006 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - UINT8 SizeOfMemorySpace; - UINT8 SizeOfIoSpace; - UINT8 Reserved[6]; -} EFI_HOB_CPU; - -// -// PEI Core Memory Pool HOB -// The HobLength is variable as the HOB contains pool allocations by -// the PeiServices AllocatePool function -// -#define EFI_HOB_TYPE_PEI_MEMORY_POOL 0x0007 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; -} EFI_HOB_MEMORY_POOL; - -// -// Capsule volume HOB -- identical to a firmware volume -// -#define EFI_HOB_TYPE_CV 0x0008 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 Length; -} EFI_HOB_CAPSULE_VOLUME; - -#if (PI_SPECIFICATION_VERSION >= 0x00010000) - -#define EFI_HOB_TYPE_FV2 0x0009 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 Length; - EFI_GUID FvName; - EFI_GUID FileName; -} EFI_HOB_FIRMWARE_VOLUME2; - -#define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A - -#endif - -#define EFI_HOB_TYPE_UNUSED 0xFFFE - -// -// Union of all the possible HOB Types -// -typedef union { - EFI_HOB_GENERIC_HEADER *Header; - EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable; - EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation; - EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore; - EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack; - EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule; - EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor; - EFI_HOB_GUID_TYPE *Guid; - EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume; -#if (PI_SPECIFICATION_VERSION >= 0x00010000) - EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2; -#endif - EFI_HOB_CPU *Cpu; - EFI_HOB_MEMORY_POOL *Pool; - EFI_HOB_CAPSULE_VOLUME *CapsuleVolume; - UINT8 *Raw; -} EFI_PEI_HOB_POINTERS; - -#define GET_HOB_TYPE(Hob) ((Hob).Header->HobType) -#define GET_HOB_LENGTH(Hob) ((Hob).Header->HobLength) -#define GET_NEXT_HOB(Hob) ((Hob).Raw + GET_HOB_LENGTH (Hob)) -#define END_OF_HOB_LIST(Hob) (GET_HOB_TYPE (Hob) == EFI_HOB_TYPE_END_OF_HOB_LIST) - -#endif diff --git a/payloads/tianocoreboot/include/PiFirmwareFile.h b/payloads/tianocoreboot/include/PiFirmwareFile.h deleted file mode 100644 index 750ba70..0000000 --- a/payloads/tianocoreboot/include/PiFirmwareFile.h +++ /dev/null @@ -1,494 +0,0 @@ -/** @file - The firmware file related definitions in PI. - -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved. -This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - @par Revision Reference: - PI Version 1.2. - -**/ - - -#ifndef __PI_FIRMWARE_FILE_H__ -#define __PI_FIRMWARE_FILE_H__ - -#pragma pack(1) -/// -/// Used to verify the integrity of the file. -/// -typedef union { - struct { - /// - /// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file - /// header. The State and IntegrityCheck.Checksum.File fields are assumed - /// to be zero and the checksum is calculated such that the entire header sums to zero. - /// - UINT8 Header; - /// - /// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes - /// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit - /// checksum of the file data. - /// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero, - /// the IntegrityCheck.Checksum.File field must be initialized with a value of - /// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the - /// EFI_FILE_DATA_VALID bit is set in the State field. - /// - UINT8 File; - } Checksum; - /// - /// This is the full 16 bits of the IntegrityCheck field. - /// - UINT16 Checksum16; -} EFI_FFS_INTEGRITY_CHECK; - -/// -/// FFS_FIXED_CHECKSUM is the checksum value used when the -/// FFS_ATTRIB_CHECKSUM attribute bit is clear. -/// -#define FFS_FIXED_CHECKSUM 0xAA - -typedef UINT8 EFI_FV_FILETYPE; -typedef UINT8 EFI_FFS_FILE_ATTRIBUTES; -typedef UINT8 EFI_FFS_FILE_STATE; - -/// -/// File Types Definitions -/// -#define EFI_FV_FILETYPE_ALL 0x00 -#define EFI_FV_FILETYPE_RAW 0x01 -#define EFI_FV_FILETYPE_FREEFORM 0x02 -#define EFI_FV_FILETYPE_SECURITY_CORE 0x03 -#define EFI_FV_FILETYPE_PEI_CORE 0x04 -#define EFI_FV_FILETYPE_DXE_CORE 0x05 -#define EFI_FV_FILETYPE_PEIM 0x06 -#define EFI_FV_FILETYPE_DRIVER 0x07 -#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 -#define EFI_FV_FILETYPE_APPLICATION 0x09 -#define EFI_FV_FILETYPE_SMM 0x0A -#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B -#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C -#define EFI_FV_FILETYPE_SMM_CORE 0x0D -#define EFI_FV_FILETYPE_OEM_MIN 0xc0 -#define EFI_FV_FILETYPE_OEM_MAX 0xdf -#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0 -#define EFI_FV_FILETYPE_DEBUG_MAX 0xef -#define EFI_FV_FILETYPE_FFS_MIN 0xf0 -#define EFI_FV_FILETYPE_FFS_MAX 0xff -#define EFI_FV_FILETYPE_FFS_PAD 0xf0 -/// -/// FFS File Attributes. -/// -#define FFS_ATTRIB_LARGE_FILE 0x01 -#define FFS_ATTRIB_FIXED 0x04 -#define FFS_ATTRIB_DATA_ALIGNMENT 0x38 -#define FFS_ATTRIB_CHECKSUM 0x40 - -/// -/// FFS File State Bits. -/// -#define EFI_FILE_HEADER_CONSTRUCTION 0x01 -#define EFI_FILE_HEADER_VALID 0x02 -#define EFI_FILE_DATA_VALID 0x04 -#define EFI_FILE_MARKED_FOR_UPDATE 0x08 -#define EFI_FILE_DELETED 0x10 -#define EFI_FILE_HEADER_INVALID 0x20 - - -/// -/// Each file begins with the header that describe the -/// contents and state of the files. -/// -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. - /// - EFI_GUID Name; - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - /// - /// The length of the file in bytes, including the FFS header. - /// - UINT8 Size[3]; - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; -} EFI_FFS_FILE_HEADER; - -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. There may be only - /// one instance of a file with the file name GUID of Name in any given firmware - /// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD. - /// - EFI_GUID Name; - - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - - /// - /// The length of the file in bytes, including the FFS header. - /// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a - /// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER). - /// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is - /// located at the next 8-byte aligned firmware volume offset following the last byte of the file F. - /// - UINT8 Size[3]; - - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; - - /// - /// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero. - /// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used. - /// - UINT32 ExtendedSize; -} EFI_FFS_FILE_HEADER2; - -#define IS_FFS_FILE2(FfsFileHeaderPtr) \ - (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE) - -#define FFS_FILE_SIZE(FfsFileHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff)) - -#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \ - (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize) - -typedef UINT8 EFI_SECTION_TYPE; - -/// -/// Pseudo type. It is used as a wild card when retrieving sections. -/// The section type EFI_SECTION_ALL matches all section types. -/// -#define EFI_SECTION_ALL 0x00 - -/// -/// Encapsulation section Type values. -/// -#define EFI_SECTION_COMPRESSION 0x01 - -#define EFI_SECTION_GUID_DEFINED 0x02 - -#define EFI_SECTION_DISPOSABLE 0x03 - -/// -/// Leaf section Type values. -/// -#define EFI_SECTION_PE32 0x10 -#define EFI_SECTION_PIC 0x11 -#define EFI_SECTION_TE 0x12 -#define EFI_SECTION_DXE_DEPEX 0x13 -#define EFI_SECTION_VERSION 0x14 -#define EFI_SECTION_USER_INTERFACE 0x15 -#define EFI_SECTION_COMPATIBILITY16 0x16 -#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 -#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 -#define EFI_SECTION_RAW 0x19 -#define EFI_SECTION_PEI_DEPEX 0x1B -#define EFI_SECTION_SMM_DEPEX 0x1C - -/// -/// Common section header. -/// -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - EFI_SECTION_TYPE Type; - /// - /// Declares the section type. - /// -} EFI_COMMON_SECTION_HEADER; - -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - - EFI_SECTION_TYPE Type; - - /// - /// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If - /// Size is not equal to 0xFFFFFF, then this field does not exist. - /// - UINT32 ExtendedSize; -} EFI_COMMON_SECTION_HEADER2; - -/// -/// Leaf section type that contains an -/// IA-32 16-bit executable image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2; - -/// -/// CompressionType of EFI_COMPRESSION_SECTION. -/// -#define EFI_NOT_COMPRESSED 0x00 -#define EFI_STANDARD_COMPRESSION 0x01 -/// -/// An encapsulation section type in which the -/// section data is compressed. -/// -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION; - -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION2; - -/// -/// An encapsulation section type in which the section data is disposable. -/// A disposable section is an encapsulation section in which the section data may be disposed of during -/// the process of creating or updating a firmware image without significant impact on the usefulness of -/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This -/// allows optional or descriptive data to be included with the firmware file which can be removed in -/// order to conserve space. The contents of this section are implementation specific, but might contain -/// debug data or detailed integration instructions. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2; - -/// -/// The leaf section which could be used to determine the dispatch order of DXEs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2; - -/// -/// The leaf section which contains a PI FV. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2; - -/// -/// The leaf section which contains a single GUID. -/// -typedef struct { - /// - /// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION2; - -/// -/// Attributes of EFI_GUID_DEFINED_SECTION. -/// -#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01 -#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02 -/// -/// The leaf section which is encapsulation defined by specific GUID. -/// -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION2; - -/// -/// The leaf section which contains PE32+ image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2; - -/// -/// The leaf section used to determine the dispatch order of PEIMs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2; - -/// -/// A leaf section type that contains a position-independent-code (PIC) image. -/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image. -/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be -/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all -/// relocation information has been stripped from the image and the image can be moved and will -/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must -/// be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2; - -/// -/// The leaf section which constains the position-independent-code image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2; - -/// -/// The leaf section which contains an array of zero or more bytes. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2; - -/// -/// The SMM dependency expression section is a leaf section that contains a dependency expression that -/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the -/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform -/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression. -/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol -/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2; - -/// -/// The leaf section which contains a unicode string that -/// is human readable file name. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - - /// - /// Array of unicode string. - /// - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION2; - -/// -/// The leaf section which contains a numeric build number and -/// an optional unicode string that represents the file revision. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - UINT16 BuildNumber; - - /// - /// Array of unicode string. - /// - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// A UINT16 that represents a particular build. Subsequent builds have monotonically - /// increasing build numbers relative to earlier builds. - /// - UINT16 BuildNumber; - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION2; - -#define IS_SECTION2(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff) - -#define SECTION_SIZE(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff)) - -#define SECTION2_SIZE(SectionHeaderPtr) \ - (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize) - -#pragma pack() - -#endif - diff --git a/payloads/tianocoreboot/include/coff.h b/payloads/tianocoreboot/include/coff.h deleted file mode 100644 index b6569a1..0000000 --- a/payloads/tianocoreboot/include/coff.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the TianoCoreBoot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -typedef struct { - uint8_t signature[2]; - uint16_t lastsize; - uint16_t nblocks; - uint16_t nreloc; - uint16_t hdrsize; - uint16_t minalloc; - uint16_t maxalloc; - uint16_t ss; - uint16_t sp; - uint16_t checksum; - uint16_t ip; - uint16_t cs; - uint16_t relocpos; - uint16_t noverlay; - uint16_t reserved1[4]; - uint16_t oem_id; - uint16_t oem_info; - uint16_t reserved2[10]; - uint32_t e_lfanew; -} dos_header_t; - -typedef struct { - uint8_t signature[4]; - uint16_t Machine; - uint16_t NumberOfSections; - uint32_t TimeDateStamp; - uint32_t PointerToSymbolTable; - uint32_t NumberOfSymbols; - uint16_t SizeOfOptionalHeader; - uint16_t Characteristics; -} coff_header_t; - -typedef struct { - uint32_t VirtualAddress; - uint32_t Size; -} data_directory; - -typedef struct { - uint16_t signature; - uint8_t MajorLinkerVersion; - uint8_t MinorLinkerVersion; - uint32_t SizeOfCode; - uint32_t SizeOfInitializedData; - uint32_t SizeOfUninitializedData; - uint32_t AddressOfEntryPoint; - uint32_t BaseOfCode; - uint32_t BaseOfData; - uint32_t ImageBase; - uint32_t SectionAlignment; - uint32_t FileAlignment; - uint16_t MajorOSVersion; - uint16_t MinorOSVersion; - uint16_t MajorImageVersion; - uint16_t MinorImageVersion; - uint16_t MajorSubsystemVersion; - uint16_t MinorSubsystemVersion; - uint32_t Reserved; - uint32_t SizeOfImage; - uint32_t SizeOfHeaders; - uint32_t Checksum; - uint16_t Subsystem; - uint16_t DLLCharacteristics; - uint32_t SizeOfStackReserve; - uint32_t SizeOfStackCommit; - uint32_t SizeOfHeapReserve; - uint32_t SizeOfHeapCommit; - uint32_t LoaderFlags; - uint32_t NumberOfRvaAndSizes; - data_directory DataDirectory[16]; -} pe_opt_header_t; - -typedef struct { - uint8_t SectionName[8]; - uint32_t Size; - uint32_t RVA; - uint32_t PhysicalSizeOnDisk; - uint32_t PhysicalLocationOnDisk; - uint8_t Reserved[12]; - uint32_t SectionFlags; -} pe_section_t; - -typedef struct { - uint32_t VirtualAddress; - uint32_t SizeOfBlock; -} relocation_t; - diff --git a/payloads/tianocoreboot/include/efi.h b/payloads/tianocoreboot/include/efi.h deleted file mode 100644 index 8deef53..0000000 --- a/payloads/tianocoreboot/include/efi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the TianoCoreBoot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> - -#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) - -typedef long intn_t; -typedef unsigned long uintn_t; - -#include <EfiTypes.h> -#include <EfiFirmwareVolumeHeader.h> -#include <PiFirmwareFile.h> -#include <PeiHob.h> -#include <MemoryAllocationHob.h> - -#define EFI_DXE_FILE_GUID \ - { 0xb1644c1a, 0xc16a, 0x4c5b, { 0x88, 0xde, 0xea, 0xfb, 0xa9, 0x7e, 0x74, 0xd8 } } - diff --git a/payloads/tianocoreboot/libpayload.config b/payloads/tianocoreboot/libpayload.config deleted file mode 100644 index 310f7e8..0000000 --- a/payloads/tianocoreboot/libpayload.config +++ /dev/null @@ -1,81 +0,0 @@ -# -# Automatically generated make config: don't edit -# libpayload version: 0.2.0 -# Wed Nov 19 15:45:30 2014 -# - -# -# Generic Options -# -# CONFIG_LP_EXPERIMENTAL is not set -# CONFIG_LP_OBSOLETE is not set -# CONFIG_LP_DEVELOPER is not set -# CONFIG_LP_CHROMEOS is not set - -# -# Architecture Options -# -# CONFIG_LP_ARCH_ARM is not set -CONFIG_LP_ARCH_X86=y -# CONFIG_LP_MEMMAP_RAM_ONLY is not set -CONFIG_LP_MULTIBOOT=y - -# -# Standard Libraries -# -CONFIG_LP_LIBC=y -CONFIG_LP_CURSES=y -# CONFIG_LP_TINYCURSES is not set -CONFIG_LP_PDCURSES=y -CONFIG_LP_CBFS=y -CONFIG_LP_LZMA=y - -# -# Console Options -# -# CONFIG_LP_SKIP_CONSOLE_INIT is not set -CONFIG_LP_CBMEM_CONSOLE=y -CONFIG_LP_SERIAL_CONSOLE=y -CONFIG_LP_8250_SERIAL_CONSOLE=y -# CONFIG_LP_S5P_SERIAL_CONSOLE is not set -# CONFIG_LP_TEGRA_SERIAL_CONSOLE is not set -# CONFIG_LP_PL011_SERIAL_CONSOLE is not set -CONFIG_LP_SERIAL_IOBASE=0x3f8 -# CONFIG_LP_SERIAL_SET_SPEED is not set -# CONFIG_LP_SERIAL_ACS_FALLBACK is not set -CONFIG_LP_VIDEO_CONSOLE=y -CONFIG_LP_VGA_VIDEO_CONSOLE=y -# CONFIG_LP_GEODELX_VIDEO_CONSOLE is not set -# CONFIG_LP_COREBOOT_VIDEO_CONSOLE is not set -CONFIG_LP_PC_KEYBOARD=y -CONFIG_LP_PC_KEYBOARD_LAYOUT_US=y -# CONFIG_LP_PC_KEYBOARD_LAYOUT_DE is not set - -# -# Drivers -# -CONFIG_LP_PCI=y -CONFIG_LP_NVRAM=y -# CONFIG_LP_RTC_PORT_EXTENDED_VIA is not set -CONFIG_LP_SPEAKER=y -CONFIG_LP_STORAGE=y -# CONFIG_LP_STORAGE_64BIT_LBA is not set -CONFIG_LP_STORAGE_ATA=y -CONFIG_LP_STORAGE_ATAPI=y -CONFIG_LP_STORAGE_AHCI=y -CONFIG_LP_STORAGE_AHCI_ONLY_TESTED=y -CONFIG_LP_TIMER_RDTSC=y -CONFIG_LP_USB=y -# CONFIG_LP_USB_UHCI is not set -# CONFIG_LP_USB_OHCI is not set -# CONFIG_LP_USB_EHCI is not set -# CONFIG_LP_USB_XHCI is not set -CONFIG_LP_USB_HID=y -CONFIG_LP_USB_HUB=y -CONFIG_LP_USB_MSC=y -CONFIG_LP_USB_GEN_HUB=y -CONFIG_LP_USB_PCI=y -# CONFIG_LP_BIG_ENDIAN is not set -CONFIG_LP_LITTLE_ENDIAN=y -CONFIG_LP_IO_ADDRESS_SPACE=y -CONFIG_LP_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/tianocoreboot/tianocoreboot.c b/payloads/tianocoreboot/tianocoreboot.c deleted file mode 100644 index bbdcfaf..0000000 --- a/payloads/tianocoreboot/tianocoreboot.c +++ /dev/null @@ -1,529 +0,0 @@ -/* - * This file is part of the TianoCoreBoot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <libpayload.h> -#include <endian.h> -#include <cbfs.h> -#include <efi.h> -#include <coff.h> - -#define DXE_CORE_SIZE (256*1024) -#define UEFI_STACK_SIZE (128*1024) -#define HOB_LIST_SIZE (16*1024) - -#undef VERBOSE -#undef INVENTORY - -static void print_guid(EFI_GUID *guid) -{ - printf("%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", - guid->Data1, guid->Data2, guid->Data3, - guid->Data4[0], guid->Data4[1], guid->Data4[2], guid->Data4[3], - guid->Data4[4], guid->Data4[5], guid->Data4[6], guid->Data4[7]); -} - -static void dump_uefi_firmware_volume_header(EFI_FIRMWARE_VOLUME_HEADER *fvh) -{ - printf("Found UEFI firmware volume.\n"); - printf(" GUID: "); - print_guid(&(fvh->FileSystemGuid)); - printf("\n"); - printf(" length: 0x%016llx\n", fvh->FvLength); -#ifdef VERBOSE - printf(" signature: 0x%08x\n", fvh->Signature); - printf(" attributes: 0x%08x\n", fvh->Attributes); - printf(" header length: 0x%04x\n", fvh->HeaderLength); - printf(" checksum: 0x%04x\n", fvh->Checksum); - printf(" revision: 0x%02x\n", fvh->Revision); - printf(" block map:\n"); - int i = 0; - EFI_FV_BLOCK_MAP_ENTRY *fbm = &(fvh->FvBlockMap[0]); - while (fbm[i].NumBlocks || fbm[i].BlockLength) { - printf(" %2d. numblocks = 0x%08x length = 0x%08x\n", - i+1, fbm[i].NumBlocks, fbm[i].BlockLength); - i++; - } -#endif - printf("\n"); -} - -#ifdef INVENTORY -static void dump_uefi_ffs_file_header(EFI_FFS_FILE_HEADER *file) -{ - int size; - -#ifdef VERBOSE - printf("Found FFS file:\n GUID: "); -#endif - print_guid(&(file->Name)); -#ifdef VERBOSE - printf("\n integrity check: %02x %02x\n", - file->IntegrityCheck.Checksum.Header, - file->IntegrityCheck.Checksum.File); - printf(" file type: "); -#else - printf(" "); -#endif - switch (file->Type) { - case EFI_FV_FILETYPE_RAW: printf("raw"); break; - case EFI_FV_FILETYPE_FREEFORM: printf("free form"); break; - case EFI_FV_FILETYPE_SECURITY_CORE: printf("security core"); break; - case EFI_FV_FILETYPE_PEI_CORE: printf("PEIM core"); break; - case EFI_FV_FILETYPE_DXE_CORE: printf("DXE core"); break; - case EFI_FV_FILETYPE_PEIM: printf("PEIM"); break; - case EFI_FV_FILETYPE_DRIVER: printf("driver"); break; - case EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER: printf("combined PEIM driver"); break; - case EFI_FV_FILETYPE_APPLICATION: printf("application"); break; - case EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE: printf("firmware volume image"); break; - case EFI_FV_FILETYPE_FFS_PAD: printf("FFS pad"); break; - default: printf("unknown"); - } -#ifdef VERBOSE - printf("\n"); - printf(" attributes: 0x%02x\n", file->Attributes); -#endif - size = file->Size[0] | (file->Size[1] << 8) | (file->Size[2] << 16); -#ifdef VERBOSE - printf(" size: 0x%06x\n", size); - printf(" state: 0x%02x\n", file->State); -#else - printf(" (%d bytes)\n", size); -#endif -} -#endif - -void *load_dxe_core(void *pe, void *target) -{ - dos_header_t *dos_hdr = (dos_header_t *)pe; - -#if VERBOSE - printf("Loading DXE core at %p\n", pe); -#endif - - if (*(uint16_t *)pe != 0x5a4d) { - printf("DXE core not a PE binary.\n"); - return NULL; - } - -#ifdef VERBOSE - printf("e_lfanew = 0x%08x\n", dos_hdr->e_lfanew); -#endif - - coff_header_t *coff_hdr = (coff_header_t *)(pe + dos_hdr->e_lfanew); -#ifdef VERBOSE - printf("Machine: %x\n", coff_hdr->Machine); - printf("NumberOfSections: %x\n", coff_hdr->NumberOfSections); - printf("TimeDateStamp: %x\n", coff_hdr->TimeDateStamp); - printf("PointerToSymbolTable: %x\n", coff_hdr->PointerToSymbolTable); - printf("NumberOfSymbols: %x\n", coff_hdr->NumberOfSymbols); - printf("SizeOfOptionalHeader: %x\n", coff_hdr->SizeOfOptionalHeader); - printf("Characteristics: %x\n", coff_hdr->Characteristics); -#endif - if (coff_hdr->Machine != 0x14c) { - printf("Only x86 supported right now.\n"); - return NULL; - } - - /* Right after the coff header */ - pe_opt_header_t *pe_hdr = (pe_opt_header_t *)(&coff_hdr[1]); - if (pe_hdr->signature != 267) { - printf("No valid PE opt header\n"); - return NULL; - } - -#ifdef VERBOSE - printf("\n"); - printf("MajorLinkerVersion: %x\n", pe_hdr->MajorLinkerVersion); - printf("MinorLinkerVersion: %x\n", pe_hdr->MinorLinkerVersion); - printf("SizeOfCode: %x\n", pe_hdr->SizeOfCode); - printf("SizeOfInitializedData: %x\n", pe_hdr->SizeOfInitializedData); - printf("SizeOfUninitializedData: %x\n", pe_hdr->SizeOfUninitializedData); - printf("AddressOfEntryPoint: %x\n", pe_hdr->AddressOfEntryPoint); - printf("BaseOfCode: %x\n", pe_hdr->BaseOfCode); - printf("BaseOfData: %x\n", pe_hdr->BaseOfData); - printf("ImageBase: %x\n", pe_hdr->ImageBase); - printf("SectionAlignment: %x\n", pe_hdr->SectionAlignment); - printf("FileAlignment: %x\n", pe_hdr->FileAlignment); - printf("MajorOSVersion: %x\n", pe_hdr->MajorOSVersion); - printf("MinorOSVersion: %x\n", pe_hdr->MinorOSVersion); - printf("MajorImageVersion: %x\n", pe_hdr->MajorImageVersion); - printf("MinorImageVersion: %x\n", pe_hdr->MinorImageVersion); - printf("MajorSubsystemVersion: %x\n", pe_hdr->MajorSubsystemVersion); - printf("MinorSubsystemVersion: %x\n", pe_hdr->MinorSubsystemVersion); - printf("Reserved: %x\n", pe_hdr->Reserved); - printf("SizeOfImage: %x\n", pe_hdr->SizeOfImage); - printf("SizeOfHeaders: %x\n", pe_hdr->SizeOfHeaders); - printf("Checksum: %x\n", pe_hdr->Checksum); - printf("Subsystem: %x\n", pe_hdr->Subsystem); - printf("DLLCharacteristics: %x\n", pe_hdr->DLLCharacteristics); - printf("SizeOfStackReserve: %x\n", pe_hdr->SizeOfStackReserve); - printf("SizeOfStackCommit: %x\n", pe_hdr->SizeOfStackCommit); - printf("SizeOfHeapReserve: %x\n", pe_hdr->SizeOfHeapReserve); - printf("SizeOfHeapCommit: %x\n", pe_hdr->SizeOfHeapCommit); - printf("LoaderFlags: %x\n", pe_hdr->LoaderFlags); - printf("NumberOfRvaAndSizes: %x\n", pe_hdr->NumberOfRvaAndSizes); -#endif - - if(pe_hdr->Subsystem != 0xb) { - printf("Not an EFI binary.\n"); - return NULL; - } - - int i; -#ifdef VERBOSE - for (i = 0; i < pe_hdr->NumberOfRvaAndSizes; i++) { - if (!pe_hdr->DataDirectory[i].Size) - continue; - printf("Data Directory %d\n", i+1); - printf(" VirtualAddress %x\n", pe_hdr->DataDirectory[i].VirtualAddress); - printf(" Size %x\n", pe_hdr->DataDirectory[i].Size); - } -#endif - - pe_section_t *sections = (pe_section_t *)(&pe_hdr[1]); - - int offset = 0; - - for (i = 0; i < coff_hdr->NumberOfSections; i++) { - int j; - printf(" Section %d: ", i); - for (j = 0; j < 8; j++) - printf("%c", sections[i].SectionName[j] ? sections[i].SectionName[j] : ' '); - - printf(" size=%08x rva=%08x in file=%08x/%08x flags=%08x\n", - sections[i].Size, sections[i].RVA, sections[i].PhysicalSizeOnDisk, - sections[i].PhysicalLocationOnDisk, sections[i].SectionFlags); - - if (!strncmp((char *)sections[i].SectionName, ".text", 6)) { - // .text section - // size=157a0 rva=240 size on disk=157a0 location on disk=240 flags=60000020 - memcpy(target, pe + sections[i].PhysicalLocationOnDisk, - sections[i].PhysicalSizeOnDisk); - offset = sections[i].RVA; - } else - if (!strncmp((char *)sections[i].SectionName, ".data", 6)) { - // .data section - // size=6820 rva=159e0 size on disk=6820 location on disk=159e0 flags=c0000040 - memcpy(target + sections[i].RVA - offset, pe + sections[i].PhysicalLocationOnDisk, - sections[i].PhysicalSizeOnDisk); - } else - if (!strncmp((char *)sections[i].SectionName, ".reloc", 7)) { - // .reloc section - // section 2: .reloc - // size=1080 rva=1c200 size on disk=1080 location on disk=1c200 flags=42000040 - relocation_t *reloc = (relocation_t *) - (pe + sections[i].PhysicalLocationOnDisk); - while (reloc && reloc->SizeOfBlock) { -#ifdef VERBOSE - printf("Relocation Block Virtual %08x Size %08x\n", - reloc->VirtualAddress, reloc->SizeOfBlock); -#endif - for (i = sizeof(relocation_t); i < reloc->SizeOfBlock; i+= 2) { - uint16_t r = *(uint16_t *)((void *)reloc + i); - switch (r>>12) { - case 3: -#ifdef VERBOSE - printf(" HIGHLOW %08x\n", - reloc->VirtualAddress + (r & 0xfff)); -#endif - *(uint32_t *)(target - offset + reloc->VirtualAddress + (r & 0xfff)) - += (unsigned long)target - offset; - break; - case 0: -#ifdef VERBOSE - printf(" ABSOLUTE %08x\n", r & 0xfff); -#endif - break; - default: - printf("Unknown relocation type %x\n", r); - return NULL; - } - } - - reloc = (relocation_t *)(((void *)reloc) + reloc->SizeOfBlock); - } - } else - if (!strncmp((char *)sections[i].SectionName, ".debug", 7)) { - // debug section, silently ignored. - } else { - printf("section type "); - for (j = 0; j < 8; j++) - if (sections[i].SectionName[j]) - printf("%c", sections[i].SectionName[j]); - printf(" unknown. ignored.\n"); - } - } - - return (target + pe_hdr->AddressOfEntryPoint - offset); -} - -void start_dxe_core(void *entry, void *stack, void *hoblist) -{ - printf("\nJumping to DXE core at %p\n", entry); - asm volatile( - "movl %1, %%esp\n" - "pushl %2\n" - "call *%0\n" - : : "r"(entry), "r"(stack), "r"(hoblist) : "esp" - ); -} - -static const EFI_HOB_HANDOFF_INFO_TABLE HandoffInformationTable = { - { EFI_HOB_TYPE_HANDOFF, sizeof(EFI_HOB_HANDOFF_INFO_TABLE), 0 }, - EFI_HOB_HANDOFF_TABLE_VERSION, - BOOT_WITH_FULL_CONFIGURATION, - 0 /* EfiMemoryTop */, - 0 /* EfiMemoryBottom */, - 0 /* EfiFreeMemoryTop */, - 0 /* EfiFreeMemoryBottom */, - 0 /* EfiEndOfHobList */ -}; - -static const EFI_HOB_FIRMWARE_VOLUME FirmwareVolume = { - { EFI_HOB_TYPE_FV, sizeof(EFI_HOB_FIRMWARE_VOLUME), 0 }, - 0 /* BaseAddress */, - 0 /* Length */ -}; - -/* 1..n */ -static const EFI_HOB_RESOURCE_DESCRIPTOR ResourceDescriptor = { - { EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, sizeof(EFI_HOB_RESOURCE_DESCRIPTOR), 0 }, - { 0 }, // owner EFI_GUID - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_TESTED, - 0, /* PhysicalStart */ - 0 /* ResourceLength */ -}; - -static const EFI_HOB_MEMORY_ALLOCATION_MODULE MemoryAllocationModule = { - { EFI_HOB_TYPE_MEMORY_ALLOCATION, sizeof(EFI_HOB_MEMORY_ALLOCATION_MODULE), 0 }, - { EFI_HOB_MEMORY_ALLOC_MODULE_GUID, 0 /* MemoryBaseAddress */, 0 /* MemoryLength */, EfiBootServicesCode, {0,0,0,0} }, - EFI_DXE_FILE_GUID, - 0x0 // ADDR EntryPoint -}; - -static const EFI_HOB_CPU Cpu = { - { EFI_HOB_TYPE_CPU, sizeof(EFI_HOB_CPU), 0 }, - 32, /* SizeOfMemorySpace, u8 */ - 16, /* SizeOfIoSpace */ - { 0,0,0,0,0,0 } -}; - -static const EFI_HOB_GENERIC_HEADER End = - { EFI_HOB_TYPE_END_OF_HOB_LIST, sizeof(EFI_HOB_GENERIC_HEADER), 0 }; - - -static void prepare_handoff_blocks(void *hoblist, EFI_FIRMWARE_VOLUME_HEADER *fvh, - unsigned long EfiMemoryTop, unsigned long EfiMemoryBottom, - unsigned long EfiFreeMemoryTop, unsigned long EfiFreeMemoryBottom, - unsigned long dxecore_base) -{ - void *ptr = hoblist; - int i; - - EFI_HOB_HANDOFF_INFO_TABLE *hit = (EFI_HOB_HANDOFF_INFO_TABLE *)ptr; - memcpy(ptr, &HandoffInformationTable, sizeof(HandoffInformationTable)); - ptr += sizeof(HandoffInformationTable); - - EFI_HOB_FIRMWARE_VOLUME *fv = (EFI_HOB_FIRMWARE_VOLUME *)ptr; - memcpy(ptr, &FirmwareVolume, sizeof(FirmwareVolume)); - ptr += sizeof(FirmwareVolume); - - for (i = 0; i < lib_sysinfo.n_memranges; i++) { - EFI_HOB_RESOURCE_DESCRIPTOR *resource; - if (lib_sysinfo.memrange[i].type != CB_MEM_RAM) - continue; - resource = (EFI_HOB_RESOURCE_DESCRIPTOR *)ptr; - memcpy(ptr, &ResourceDescriptor, sizeof(ResourceDescriptor)); - ptr += sizeof(ResourceDescriptor); - resource->PhysicalStart = lib_sysinfo.memrange[i].base; - resource->ResourceLength = lib_sysinfo.memrange[i].size; - } - - EFI_HOB_MEMORY_ALLOCATION_MODULE *allocation = (EFI_HOB_MEMORY_ALLOCATION_MODULE *)ptr; - memcpy(ptr, &MemoryAllocationModule, sizeof(MemoryAllocationModule)); - ptr += sizeof(MemoryAllocationModule); - - memcpy(ptr, &Cpu, sizeof(Cpu)); - ptr += sizeof(Cpu); - - memcpy(ptr, &End, sizeof(End)); - ptr += sizeof(Cpu); - - /* Handoff Information Table HOB */ - hit->EfiMemoryTop = EfiMemoryTop; - hit->EfiMemoryBottom = EfiMemoryBottom; - hit->EfiFreeMemoryTop = EfiFreeMemoryTop; - hit->EfiFreeMemoryBottom = EfiFreeMemoryBottom; - hit->EfiEndOfHobList = (unsigned long)ptr; - - /* Firmware Volume HOB */ - fv->BaseAddress = (unsigned long)fvh; - fv->Length = fvh->FvLength; - - allocation->MemoryAllocationHeader.MemoryBaseAddress = dxecore_base; - allocation->MemoryAllocationHeader.MemoryLength = DXE_CORE_SIZE; -} - -int main(void) -{ - int i; - struct cbfs_file *file; - void *tiano; - unsigned long long ram_seg_base = 0, ram_seg_size = 0; - EFI_FIRMWARE_VOLUME_HEADER *fvh = NULL; - EFI_PEI_HOB_POINTERS hoblist; - EFI_COMMON_SECTION_HEADER *dxecore = NULL; - - printf("\nTiano Core Loader v1.0\n"); - printf("Copyright (C) 2013 Google Inc. All rights reserved.\n\n"); - - printf("Memory Map (%d entries):\n", lib_sysinfo.n_memranges); - for (i = 0; i < lib_sysinfo.n_memranges; i++) { - printf(" %d. %016llx - %016llx [%02x]\n", i + 1, - lib_sysinfo.memrange[i].base, - lib_sysinfo.memrange[i].base + - lib_sysinfo.memrange[i].size - 1, - lib_sysinfo.memrange[i].type); - - /* Look for the last chunk of memory below 4G */ - if (lib_sysinfo.memrange[i].type == CB_MEM_RAM && - lib_sysinfo.memrange[i].base < 0xffffffff) { - ram_seg_base = lib_sysinfo.memrange[i].base; - ram_seg_size = lib_sysinfo.memrange[i].size; - } - } - printf("\n"); - - if (!ram_seg_base || ram_seg_size < (1024*1024)) { - printf("No usable RAM found.\n"); - halt(); - } - - /* Find the end of our memory block, align to 4K */ - unsigned long memory = (ram_seg_base + ram_seg_size) & 0xfffff000; - - /* 256K for DXE core. It's 116K on my system but you never know. */ - memory -= DXE_CORE_SIZE; - unsigned long dxecore_base = memory; - memory -= UEFI_STACK_SIZE; - unsigned long uefi_stack = memory; - - memory -= 1024*1024; // FIXME this should go away - unsigned long free_memory = memory; // FIXME this should go away - - memory -= HOB_LIST_SIZE; - unsigned long hoblist_base = memory; - - printf("DXE code: %08lx\n", dxecore_base); - printf("DXE stack: %08lx\n", uefi_stack); - printf("HOB list: %08lx\n\n", hoblist_base); - - /* Find UEFI firmware volume in CBFS */ - file = cbfs_find("fallback/tianocore.fd"); - if (!file) { - printf("Could not find fallback/tianocore.fd in CBFS.\n"); - halt(); - } - - tiano = CBFS_SUBHEADER(file); - while (tiano < (void *)CBFS_SUBHEADER(file) + ntohl(file->len)) { - /* Verify UEFI firmware volume consistency */ - fvh = (EFI_FIRMWARE_VOLUME_HEADER *)tiano; - if (fvh->Signature != 0x4856465f) { - printf("Not an UEFI firmware volume.\n"); - halt(); - } - - /* Dump UEFI firmware volume header */ - dump_uefi_firmware_volume_header(fvh); - - /* Dump UEFI firmware file headers */ - for (i = fvh->HeaderLength; i < fvh->FvLength;) { - int size; - EFI_FFS_FILE_HEADER *ffs; - - ffs = (EFI_FFS_FILE_HEADER *)(tiano + i); - - size = ffs->Size[0] | (ffs->Size[1] << 8) | (ffs->Size[2] << 16); - if (size == 0xffffff) - break; -#ifdef INVENTORY - printf("%08x - ", i); - dump_uefi_ffs_file_header(ffs); -#endif - - if (ffs->Type == EFI_FV_FILETYPE_DXE_CORE) { - dxecore = (EFI_COMMON_SECTION_HEADER *)&ffs[1]; -#ifndef INVENTORY - break; -#endif - } - - i = ALIGN(i + size, 8); - } - - tiano += fvh->FvLength; -#ifdef INVENTORY - printf("\n"); -#endif - } - - /* Prepare Hand Off Blocks */ - prepare_handoff_blocks((void *)hoblist_base, fvh, - // FIXME memory top, memory bottom - (ram_seg_base + ram_seg_size) & 0xfffff000, ram_seg_base, - // FIXME free memory top, free memory bottom - uefi_stack, free_memory, - dxecore_base); - hoblist.Raw = (void *)hoblist_base; - - if (!dxecore) { - printf("No DXE core found.\n"); - halt(); - } - - printf("Found DXE core at %p\n", &dxecore[1]); -#ifdef VERBOSE - int size = dxecore->Size[0] | (dxecore->Size[1] << 8) | (dxecore->Size[2] << 16); - printf(" size = %d, type = %x\n", size, dxecore->Type); -#endif - - void *pe = (void *)&dxecore[1]; - - void *entry; - entry = load_dxe_core(pe, (void *)dxecore_base); - - if (!entry) { - printf("Could not load DXE code.\n"); - halt(); - } - - start_dxe_core(entry, (void *)(uefi_stack + UEFI_STACK_SIZE - 4), hoblist.Raw); - - printf("The end.\n"); - halt(); - - return 0; -} - -PAYLOAD_INFO(name, "TianoCoreBoot"); -PAYLOAD_INFO(listname, "Tiano Core"); -PAYLOAD_INFO(desc, "Tiano Core Loader");

1 0

Patch merged into coreboot/master: fffd772 tianocoreboot: Update config to make it compile
by gerrit＠coreboot.org 02 Dec '14

02 Dec '14

the following patch was just integrated into master: commit fffd772e35f1efb528fa485ebfbbbe3f405d7ec9 Author: Marcel Meißner <mm-meissner(a)gmx.de> Date: Thu Nov 20 21:25:36 2014 +0100 tianocoreboot: Update config to make it compile Change-Id: Ie584460529dcd342702dc00787df9c20e2ef10e7 Signed-off-by: Marcel Meißner <mm-meissner(a)gmx.de> Reviewed-on: http://review.coreboot.org/7541 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7541 for details. -gerrit

1 0

Patch merged into coreboot/master: e890531 nvramtool: cmos_read(): Use malloc() instead of alloca()
by gerrit＠coreboot.org 02 Dec '14

02 Dec '14

the following patch was just integrated into master: commit e8905312f066fc899089edebe803873819f2b920 Author: Andrew Engelbrecht <sudoman(a)ninthfloor.org> Date: Mon Dec 1 12:22:48 2014 -0500 nvramtool: cmos_read(): Use malloc() instead of alloca() Fixes crash occurring when 'nvramtool -a' tried to free a prematurely freed pointer. (Tested on x60) malloc() is correct because the pointer is accessed outside the calling function. The pointer is freed in the parent function list_cmos_entry(). Change-Id: I1723f09740657f0f0d9e6954bd6d11c0a3820a42 Signed-off-by: Andrew Engelbrecht <sudoman(a)ninthfloor.org> Reviewed-on: http://review.coreboot.org/7620 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/7620 for details. -gerrit

1 0

New patch to review for coreboot: 956aede mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREE
by Edward O'Callaghan 02 Dec '14

02 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7625 -gerrit commit 956aede3ccc1de672b304805bc9f686d41f7ec19 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 19:35:28 2014 +1100 mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREE The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: I0b4e99cc0d6f89f0261f26ee61b8c175a373c730 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/Kconfig | 4 ---- src/mainboard/lenovo/g505s/agesawrapper.c | 7 ------- 2 files changed, 11 deletions(-) diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index fb753dc..fc3a6ac 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -68,8 +68,4 @@ config VGA_BIOS_ID string default "1002,990b" -config HUDSON_LEGACY_FREE - bool - default y - endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c index 4cbaeaa..4417681 100644 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ b/src/mainboard/lenovo/g505s/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);

1 0

Patch set updated for coreboot: 0106dbd AGESA: Remove duplicate OemCustomizeInitEarly declarations
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7158 -gerrit commit 0106dbd936ed3a52cb71dbcda9d3e1c0961c1b52 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 13:43:46 2014 +0300 AGESA: Remove duplicate OemCustomizeInitEarly declarations Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 1 + src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 2 -- src/mainboard/amd/olivehill/PlatformGnbPcie.c | 3 +- .../amd/olivehill/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/amd/parmer/PlatformGnbPcie.c | 3 +- src/mainboard/amd/parmer/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 1 + .../amd/persimmon/PlatformGnbPcieComplex.h | 4 --- src/mainboard/amd/south_station/PlatformGnbPcie.c | 1 + .../amd/south_station/PlatformGnbPcieComplex.h | 4 --- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 3 +- .../amd/thatcher/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 1 + src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 4 --- src/mainboard/amd/union_station/PlatformGnbPcie.c | 1 + .../amd/union_station/PlatformGnbPcieComplex.h | 4 --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 1 + .../asrock/e350m1/PlatformGnbPcieComplex.h | 4 --- src/mainboard/asrock/imb-a180/PlatformGnbPcie.c | 3 +- .../asrock/imb-a180/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 5 +++- .../asus/f2a85-m/PlatformGnbPcieComplex.h | 31 --------------------- src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c | 1 + .../gizmosphere/gizmo/PlatformGnbPcieComplex.h | 4 --- .../hp/pavilion_m6_1035dx/PlatformGnbPcie.c | 5 +++- .../hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h | 31 --------------------- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 1 + .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 2 -- src/mainboard/lenovo/g505s/PlatformGnbPcie.c | 5 +++- .../lenovo/g505s/PlatformGnbPcieComplex.h | 31 --------------------- .../lippert/frontrunner-af/PlatformGnbPcie.c | 1 + .../frontrunner-af/PlatformGnbPcieComplex.h | 4 --- src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 1 + .../lippert/toucan-af/PlatformGnbPcieComplex.h | 4 --- src/northbridge/amd/agesa/agesawrapper.h | 3 ++ src/northbridge/amd/agesa/family12/agesawrapper.c | 2 -- src/northbridge/amd/agesa/family14/agesawrapper.c | 2 -- src/northbridge/amd/agesa/family15/agesawrapper.c | 4 +-- .../amd/agesa/family15rl/agesawrapper.c | 2 -- .../amd/agesa/family15tn/agesawrapper.c | 2 -- .../amd/agesa/family16kb/agesawrapper.c | 2 -- 41 files changed, 35 insertions(+), 276 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 08cd998..4e8e15f 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 111ad6f..0b93d9c 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -64,6 +64,4 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c index 0775ad3..903d1bb 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h b/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h deleted file mode 100644 index b3c69cf..0000000 --- a/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index 784f6d9..50f8be5 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* diff --git a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h deleted file mode 100644 index b3c69cf..0000000 --- a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index de797c0..0ecc4f1 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index ec8a6e3..4a01875 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -65,9 +65,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index 3798251..884d813 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 4072112..58cc105 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h deleted file mode 100644 index b3c69cf..0000000 --- a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index a17a7ed..f8ad709 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index aa0eedb..12ded1e 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index eefd27f..9f6af52 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c index 24d8381..75fb0c2 100644 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c +++ b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h b/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h deleted file mode 100644 index 1db8b2d..0000000 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 3a8be41..91b5028 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -17,8 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "PlatformGnbPcieComplex.h" +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h deleted file mode 100644 index add9008..0000000 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> -#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c index cc4bbfb..00bd809 100755 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c @@ -26,6 +26,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h index 5cd4b41..88dc25b 100755 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h @@ -66,9 +66,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c index de046ac..378b48f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c @@ -17,8 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "PlatformGnbPcieComplex.h" +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h deleted file mode 100644 index add9008..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> -#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index ad4934e..cdeca0b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -21,6 +21,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index dd6f7d7..0d1738e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -79,6 +79,4 @@ #define GNB_GPP_PORT8_CHANNEL_TYPE 4 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 -void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); - #endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c index de046ac..378b48f 100644 --- a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c +++ b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c @@ -17,8 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "PlatformGnbPcieComplex.h" +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h b/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h deleted file mode 100644 index add9008..0000000 --- a/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> -#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index c06296f..331e27d 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h index 02c7f4e..0b57605 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h @@ -65,9 +65,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index f8ba912..5677aa8 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h index 69e2615..301938c 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h @@ -65,9 +65,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index b94ddf7..49f6666 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -65,4 +65,7 @@ void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_fchs3earlyrestore(void); AGESA_STATUS agesawrapper_fchs3laterestore(void); +void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly); +void OemCustomizeInitPost(AMD_POST_PARAMS *InitPost); + #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 8a5f03f..7309262 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -47,8 +47,6 @@ VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - UINT32 ReadAmdSbPmr(IN UINT8 IndexValue, OUT UINT8 * DataValue); UINT32 WriteAmdSbPmr(IN UINT8 IndexValue, IN UINT8 DataValue); diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index ee6caaf..1f580ef 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -46,8 +46,6 @@ VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(VOID) { UINT64 MsrReg; diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 74f9cb9..5c99551 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -47,11 +47,11 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; /* TODO: Function body should be in mainboard directory. */ -static VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS * InitEarly) +void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly) { } -static VOID OemCustomizeInitPost(AMD_POST_PARAMS *InitPost) +void OemCustomizeInitPost(AMD_POST_PARAMS *InitPost) { #if IS_ENABLED(CONFIG_BOARD_AMD_DINAR) InitPost->MemConfig.UmaMode = UMA_AUTO; diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 66a351c..2099a49 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; VOID *AcpiIvrs = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(void) { UINT64 MsrReg; diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 66a351c..2099a49 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; VOID *AcpiIvrs = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(void) { UINT64 MsrReg; diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 66a351c..2099a49 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; VOID *AcpiIvrs = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(void) { UINT64 MsrReg;

1 0

Patch set updated for coreboot: 1f59790 AGESA fam15tn / fam15rl / fam16kb: Common agesawrapper
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7159 -gerrit commit 1f59790c03a84e7fcdef06303c36e895043e3e84 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 20 08:49:16 2014 +0300 AGESA fam15tn / fam15rl / fam16kb: Common agesawrapper Split FCH parts to southbridge/hudson. Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/Makefile.inc | 2 - src/mainboard/amd/olivehill/agesawrapper.c | 609 -------------------- src/mainboard/amd/parmer/Makefile.inc | 2 - src/mainboard/amd/parmer/agesawrapper.c | 612 -------------------- src/mainboard/amd/thatcher/Makefile.inc | 2 - src/mainboard/amd/thatcher/agesawrapper.c | 616 -------------------- src/mainboard/asrock/imb-a180/Makefile.inc | 2 - src/mainboard/asrock/imb-a180/agesawrapper.c | 638 --------------------- src/mainboard/asus/f2a85-m/Makefile.inc | 2 - src/mainboard/asus/f2a85-m/agesawrapper.c | 636 -------------------- src/mainboard/asus/f2a85-m_le/Makefile.inc | 2 - src/mainboard/asus/f2a85-m_le/agesawrapper.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 2 - src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 625 -------------------- src/mainboard/lenovo/g505s/Makefile.inc | 2 - src/mainboard/lenovo/g505s/agesawrapper.c | 625 -------------------- src/northbridge/amd/agesa/family15rl/Makefile.inc | 2 + .../amd/agesa/family15rl/agesawrapper.c | 499 ++++++++++++++++ src/northbridge/amd/agesa/family15tn/Makefile.inc | 2 + .../amd/agesa/family15tn/agesawrapper.c | 499 ++++++++++++++++ src/northbridge/amd/agesa/family16kb/Makefile.inc | 2 + .../amd/agesa/family16kb/agesawrapper.c | 499 ++++++++++++++++ src/southbridge/amd/agesa/hudson/Makefile.inc | 2 + src/southbridge/amd/agesa/hudson/agesawrapper.c | 92 +++ 24 files changed, 1597 insertions(+), 4378 deletions(-) diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c deleted file mode 100644 index 242aa27..0000000 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c deleted file mode 100644 index b4b39d0..0000000 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c deleted file mode 100644 index 7425eac..0000000 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ /dev/null @@ -1,616 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; -#if 1 /* TODO: Get the param from Nv storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); -#endif - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO:Get params from Volatile storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); -#endif - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#if 1 /* TODO: Save the params to NvStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#endif - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO: Save the params to VolatileStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage - ); -#endif - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/asrock/imb-a180/Makefile.inc b/src/mainboard/asrock/imb-a180/Makefile.inc index a83297a..0e63e9b 100644 --- a/src/mainboard/asrock/imb-a180/Makefile.inc +++ b/src/mainboard/asrock/imb-a180/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c deleted file mode 100644 index 1412392..0000000 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ /dev/null @@ -1,638 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/asus/f2a85-m/Makefile.inc +++ b/src/mainboard/asus/f2a85-m/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c deleted file mode 100644 index 2a5f5c8..0000000 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "PlatformGnbPcieComplex.h" - -#include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/mtrr.h> -#include <device/device.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <stdint.h> -#include <string.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; -#if 1 /* TODO: Get the param from Nv storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); -#endif - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO:Get params from Volatile storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); -#endif - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#if 1 /* TODO: Save the params to NvStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#endif - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO: Save the params to VolatileStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage - ); -#endif - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/asus/f2a85-m_le/Makefile.inc b/src/mainboard/asus/f2a85-m_le/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/asus/f2a85-m_le/Makefile.inc +++ b/src/mainboard/asus/f2a85-m_le/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asus/f2a85-m_le/agesawrapper.c b/src/mainboard/asus/f2a85-m_le/agesawrapper.c deleted file mode 100644 index d38e91c..0000000 --- a/src/mainboard/asus/f2a85-m_le/agesawrapper.c +++ /dev/null @@ -1 +0,0 @@ -#include "../f2a85-m/agesawrapper.c" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 7039c72..fae7fcc 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -18,12 +18,10 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c ramstage-y += ec.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c deleted file mode 100644 index 1ceffa0..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "PlatformGnbPcieComplex.h" - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <device/device.h> -#include <string.h> -#include <stdint.h> - -#include <cpu/amd/agesa/s3_resume.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -uint32_t agesawrapper_amdinitcpuio(void) -{ - pci_devfn_t dev; - msr_t msr; - uint32_t reg32; - - dev = PCI_DEV(0, 0x18, 1); - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - pci_io_write_config32(dev, 0xf4, 1); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - * Last address before processor local APIC at FEE00000 - */ - pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7)); - - - /* Lowest NP address is HPET at FED00000 */ - pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3); - - /* Map the remaining PCI hole as posted MMIO */ - pci_io_write_config32(dev, 0x8C, 0x00fecf00); - - msr = rdmsr(0xc001001a); - reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */ - pci_io_write_config32(dev, 0x88, reg32); - - /* Send all IO (0000-FFFF) to southbridge. */ - pci_io_write_config32(dev, 0xc4, 0x0000f000); - pci_io_write_config32(dev, 0xc0, 0x00000003); - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index 7039c72..fae7fcc 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -18,12 +18,10 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c ramstage-y += ec.c diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c deleted file mode 100644 index 1ceffa0..0000000 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "PlatformGnbPcieComplex.h" - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <device/device.h> -#include <string.h> -#include <stdint.h> - -#include <cpu/amd/agesa/s3_resume.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -uint32_t agesawrapper_amdinitcpuio(void) -{ - pci_devfn_t dev; - msr_t msr; - uint32_t reg32; - - dev = PCI_DEV(0, 0x18, 1); - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - pci_io_write_config32(dev, 0xf4, 1); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - * Last address before processor local APIC at FEE00000 - */ - pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7)); - - - /* Lowest NP address is HPET at FED00000 */ - pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3); - - /* Map the remaining PCI hole as posted MMIO */ - pci_io_write_config32(dev, 0x8C, 0x00fecf00); - - msr = rdmsr(0xc001001a); - reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */ - pci_io_write_config32(dev, 0x88, reg32); - - /* Send all IO (0000-FFFF) to southbridge. */ - pci_io_write_config32(dev, 0xc4, 0x0000f000); - pci_io_write_config32(dev, 0xc0, 0x00000003); - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family15rl/Makefile.inc b/src/northbridge/amd/agesa/family15rl/Makefile.inc index 5013364..831aab1 100644 --- a/src/northbridge/amd/agesa/family15rl/Makefile.inc +++ b/src/northbridge/amd/agesa/family15rl/Makefile.inc @@ -18,6 +18,8 @@ # romstage-y += dimmSpd.c +romstage-y += agesawrapper.c ramstage-y += iommu.c ramstage-y += northbridge.c +ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c new file mode 100644 index 0000000..66a351c --- /dev/null +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -0,0 +1,499 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32) MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + + status = AmdInitEnv(EnvParam); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +VOID *agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + + ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitLate(AmdLateParams); + AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return status; +} + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct(&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog(&AmdEventParams); + } + + return Status; +} diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index 5013364..831aab1 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -18,6 +18,8 @@ # romstage-y += dimmSpd.c +romstage-y += agesawrapper.c ramstage-y += iommu.c ramstage-y += northbridge.c +ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c new file mode 100644 index 0000000..66a351c --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -0,0 +1,499 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32) MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + + status = AmdInitEnv(EnvParam); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +VOID *agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + + ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitLate(AmdLateParams); + AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return status; +} + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct(&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog(&AmdEventParams); + } + + return Status; +} diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index 4a75499..f821940 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -18,5 +18,7 @@ # romstage-y += dimmSpd.c +romstage-y += agesawrapper.c ramstage-y += northbridge.c +ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c new file mode 100644 index 0000000..66a351c --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -0,0 +1,499 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32) MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + + status = AmdInitEnv(EnvParam); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +VOID *agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + + ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitLate(AmdLateParams); + AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return status; +} + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct(&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog(&AmdEventParams); + } + + return Status; +} diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 98cac93..84f0d3e 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -10,6 +10,8 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += agesawrapper.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c new file mode 100644 index 0000000..4de59b9 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/agesawrapper.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +extern UINT8 picr_data[0x54], intr_data[0x54]; + +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) +{ + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3EarlyRestore(&FchParams); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_fchs3laterestore (void) +{ + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + UINT8 byte; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + return AGESA_SUCCESS; +}

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2014