coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

1 participants
1346 discussions

Patch set updated for coreboot: c50cda4 AGESA: Trace execution with AGESA_EVENTLOG()
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7604 -gerrit commit c50cda4d600c3440076a10e59f5488e1639394d8 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 14:19:04 2014 +0300 AGESA: Trace execution with AGESA_EVENTLOG() Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/agesawrapper_s3.c | 6 +- src/cpu/amd/agesa/amd_late_init.c | 5 +- src/mainboard/amd/dinar/romstage.c | 11 ++-- src/mainboard/amd/inagua/romstage.c | 11 ++-- src/mainboard/amd/olivehill/romstage.c | 15 +++-- src/mainboard/amd/parmer/romstage.c | 15 +++-- src/mainboard/amd/persimmon/romstage.c | 15 +++-- src/mainboard/amd/south_station/romstage.c | 11 ++-- src/mainboard/amd/thatcher/romstage.c | 15 +++-- src/mainboard/amd/torpedo/romstage.c | 11 ++-- src/mainboard/amd/union_station/romstage.c | 11 ++-- src/mainboard/asrock/e350m1/romstage.c | 11 ++-- src/mainboard/asrock/imb-a180/romstage.c | 15 +++-- src/mainboard/asus/f2a85-m/romstage.c | 15 +++-- src/mainboard/gizmosphere/gizmo/romstage.c | 15 +++-- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 15 +++-- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 15 +++-- src/mainboard/lenovo/g505s/romstage.c | 15 +++-- src/mainboard/lippert/frontrunner-af/romstage.c | 15 +++-- src/mainboard/lippert/toucan-af/romstage.c | 15 +++-- src/mainboard/supermicro/h8qgi/romstage.c | 11 ++-- src/mainboard/supermicro/h8scm/romstage.c | 11 ++-- src/mainboard/tyan/s8226/romstage.c | 11 ++-- src/northbridge/amd/agesa/agesawrapper.h | 5 +- src/northbridge/amd/agesa/agesawrapper_call.h | 73 ---------------------- src/northbridge/amd/agesa/eventlog.c | 71 +++++++++++++++++---- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/agesawrapper.c | 14 ++--- src/northbridge/amd/agesa/family12/northbridge.c | 3 +- src/northbridge/amd/agesa/family14/agesawrapper.c | 16 ++--- src/northbridge/amd/agesa/family14/northbridge.c | 3 +- src/northbridge/amd/agesa/family15/agesawrapper.c | 14 ++--- src/northbridge/amd/agesa/family15/northbridge.c | 3 +- .../amd/agesa/family15rl/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family15rl/northbridge.c | 5 +- .../amd/agesa/family15tn/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 5 +- .../amd/agesa/family16kb/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 5 +- 39 files changed, 246 insertions(+), 299 deletions(-) diff --git a/src/cpu/amd/agesa/agesawrapper_s3.c b/src/cpu/amd/agesa/agesawrapper_s3.c index b9f5051..72bcf42 100644 --- a/src/cpu/amd/agesa/agesawrapper_s3.c +++ b/src/cpu/amd/agesa/agesawrapper_s3.c @@ -59,7 +59,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG_(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -93,7 +93,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; @@ -122,7 +122,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); ASSERT(status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 26442f4..53c2759 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -21,7 +21,6 @@ #include <bootstate.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> @@ -32,7 +31,7 @@ static void agesawrapper_post_device(void *unused) if (acpi_is_wakeup_s3()) return; - AGESAWRAPPER(amdinitlate); + agesawrapper_amdinitlate(); #if CONFIG_AMD_SB_CIMX sb_Late_Post(); @@ -40,7 +39,7 @@ static void agesawrapper_post_device(void *unused) if (!acpi_s3_resume_allowed()) return; - AGESAWRAPPER(amdS3Save); + agesawrapper_amdS3Save(); } BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 3b13ee6..b1e9a61 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -30,7 +30,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> @@ -64,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x32); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); /* Halt if there was a built in self test failure */ post_code(0x33); @@ -81,10 +80,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x35); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x36); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x37); nb_Poweron_Init(); @@ -93,10 +92,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x40); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x43); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index e0cf1d3..3a5c761 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index b1dcb58..abab688 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -51,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -81,29 +80,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = inb(0xcd6); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index fe84a90..9a55e80 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -68,25 +67,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index fbe60fc..5434ed3 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> @@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index a64ba60..7dcd9b2 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 6a300d6..1934545 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -48,7 +47,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); @@ -82,25 +81,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 682a76e..f2bcccc 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -29,7 +29,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" @@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x35); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -72,13 +71,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x36); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x37); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x38); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x39); printk(BIOS_DEBUG, "sb_before_pci_init "); @@ -86,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x43); copy_and_run(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 7745338..ac583dd 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include <sb_cimx.h> @@ -69,19 +68,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index f297da6..c7c71a1 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,7 +31,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 24fa194..3d1458b 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -105,29 +104,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = inb(0xcd6); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 57450ee..fbc89a7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -19,7 +19,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -76,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { @@ -128,24 +127,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 95c7041..92b5292 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,7 +33,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <cpu/x86/cache.h> #include <sb_cimx.h> @@ -88,29 +87,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 449a8c1..9411ac8 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -18,7 +18,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -39,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 30215ce..534bdc4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -19,7 +19,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -96,29 +95,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 449a8c1..9411ac8 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -18,7 +18,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -39,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); /* Set LPC decode enables. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); @@ -64,25 +63,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 02f4bc7..c4bf978 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/smscsuperio/smscsuperio.h> #include "cpu/x86/lapic.h" @@ -79,33 +78,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = AGESAWRAPPER(amdinitpost); + val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 2714d7f..9d99894 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -80,33 +79,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = AGESAWRAPPER(amdinitpost); + val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index d584a4c..9c48601 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -46,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ @@ -66,7 +65,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -81,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. @@ -101,10 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index c67a926..2f4c828 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ @@ -65,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -80,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); nb_Ht_Init(); @@ -95,10 +94,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a0e8bfd..8587ed1 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -44,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* For serial port. */ @@ -69,7 +68,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -84,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. @@ -104,10 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index e1eb69b..7b61b4c 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -23,7 +23,6 @@ #include <stdint.h> #include "Porting.h" #include "AGESA.h" -#include <northbridge/amd/agesa/agesawrapper_call.h> /* Define AMD Ontario APPU SSID/SVID */ #define AMD_APU_SVID 0x1022 @@ -48,7 +47,9 @@ AGESA_STATUS agesawrapper_amdinitlate(void); AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); +#define AGESA_EVENTLOG(status, stdheader) \ + agesawrapper_trace(status, stdheader, __func__) AGESA_STATUS agesawrapper_amdinitcpuio(void); AGESA_STATUS agesawrapper_amdinitmmio(void); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h deleted file mode 100644 index 55742d4..0000000 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_CALL_H_ -#define _AGESAWRAPPER_CALL_H_ - -#include <stdint.h> -#include <console/console.h> -#include "AGESA.h" - -/* - * Possible AGESA_STATUS values: - * - * 0x0 = AGESA_SUCCESS - * 0x1 = AGESA_UNSUPPORTED - * 0x2 = AGESA_BOUNDS_CHK - * 0x3 = AGESA_ALERT - * 0x4 = AGESA_WARNING - * 0x5 = AGESA_ERROR - * 0x6 = AGESA_CRITICAL - * 0x7 = AGESA_FATAL - */ -static const char * decodeAGESA_STATUS(AGESA_STATUS sret) -{ - const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", - "AGESA_BOUNDS_CHK", "AGESA_ALERT", - "AGESA_WARNING", "AGESA_ERROR", - "AGESA_CRITICAL", "AGESA_FATAL" - }; - if (sret > 7) return "unknown"; /* Non-AGESA error code */ - return statusStrings[sret]; -} - -static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) -{ - AGESA_STATUS ret; - printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); - ret = func(); - printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", - name, decodeAGESA_STATUS(ret)); - return (u32)ret; -} - -#define AGESAWRAPPER(func) do_agesawrapper(agesawrapper_ ## func, #func) - -#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() - -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 - /* TODO: These families do not pass valid HeapStatus. */ -#define AGESA_EVENTLOG(status) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0) -#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x) -#else -#define AGESA_EVENTLOG(status, heapstatus) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) -#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x,y) -#endif - -#endif diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 1deb343..90640d9 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -1,9 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <console/console.h> +#include <stdint.h> +#include <string.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" +#include "AGESA.h" +#include "AMD.h" + + +/* + * Possible AGESA_STATUS values: + * + * 0x0 = AGESA_SUCCESS + * 0x1 = AGESA_UNSUPPORTED + * 0x2 = AGESA_BOUNDS_CHK + * 0x3 = AGESA_ALERT + * 0x4 = AGESA_WARNING + * 0x5 = AGESA_ERROR + * 0x6 = AGESA_CRITICAL + * 0x7 = AGESA_FATAL + */ +static const char * decodeAGESA_STATUS(AGESA_STATUS sret) +{ + const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", + "AGESA_BOUNDS_CHK", "AGESA_ALERT", + "AGESA_WARNING", "AGESA_ERROR", + "AGESA_CRITICAL", "AGESA_FATAL" + }; + if (sret > 7) return "unknown"; /* Non-AGESA error code */ + return statusStrings[sret]; +} #if 0 @@ -42,6 +86,7 @@ static void agesa_alert(EVENT_PARAMS *event) switch (event->EventInfo) { case MEM_ALERT_USER_TMG_MODE_OVERRULED: printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " + "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", (unsigned int)event->DataParam1, (unsigned int)event->DataParam2, @@ -664,25 +709,19 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) } #endif -/** - * @param HeapStatus -the current HeapStatus - */ -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) { - AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill(&AmdEventParams, - 0, - sizeof(EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); + AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus; + + AmdReadEventLog(&AmdEventParams); while (AmdEventParams.EventClass != 0) { printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass, @@ -693,8 +732,14 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); + AmdReadEventLog(&AmdEventParams); } +} - return Status; + +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func) +{ + printk(BIOS_DEBUG, "%s() returned %s\n", func, decodeAGESA_STATUS(ret)); + if (ret != AGESA_SUCCESS) + amd_readeventlog(StdHeader); } diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1f615e5..2c46129 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -832,7 +832,7 @@ static void amdfam10_domain_enable_resources(device_t dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 9a39c0e..8d0fe90 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -247,7 +247,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -296,7 +296,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -321,7 +321,7 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -370,7 +370,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -389,7 +389,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) AmdLateParams.StdHeader.ImageBasePtr = 0; status = AmdInitLate(&AmdLateParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdLateParams.StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams.DmiTable; @@ -417,7 +417,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf ApExeParams.StdHeader.ImageBasePtr = 0; status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index bcebcd9..8d82925 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -37,7 +37,6 @@ #include "sb_cimx.h" #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 @@ -777,7 +776,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index e182830..8d80ef1 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -157,7 +157,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -182,7 +182,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -204,7 +204,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -229,8 +229,10 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); + status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); + /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -347,7 +349,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -375,7 +377,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) (u32) AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; @@ -414,7 +416,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf ApExeParams.RelatedDataBlock = ConfigPtr; status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index aec7157..8d95dc4 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -36,7 +36,6 @@ #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -775,7 +774,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 4641881..0552a02 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -210,7 +210,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); #endif - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -243,7 +243,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices, &AmdParamStruct.StdHeader); @@ -281,7 +281,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) OemCustomizeInitPost(PostParams); status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); @@ -317,7 +317,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) } EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParams); - AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -369,7 +369,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -396,7 +396,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(status, AmdLateParamsPtr->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParamsPtr->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; @@ -438,7 +438,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data); status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr); - AGESA_EVENTLOG(status, AmdLateParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams.StdHeader); ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED)); return status; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index de7d026..0700a5d 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "sb_cimx.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -710,7 +709,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index c5924d2..9d2fa9f 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -43,7 +43,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -697,14 +696,14 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 54a5c69..ac8d72a 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -695,14 +694,14 @@ static void domain_read_resources(device_t dev) static void domain_enable_resources(device_t dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 849f40c..db12fc3 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam16.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -737,14 +736,14 @@ static void domain_read_resources(device_t dev) static void domain_enable_resources(device_t dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); }

1 0

Patch set updated for coreboot: f730603 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7602 -gerrit commit f730603d582c740ab87d823b7866120ea6c52989 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 21 17:40:37 2014 +0200 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/agesawrapper.c | 7 ------- src/mainboard/amd/olivehill/romstage.c | 4 ++++ src/mainboard/amd/parmer/agesawrapper.c | 7 ------- src/mainboard/amd/parmer/romstage.c | 4 ++++ src/mainboard/amd/thatcher/agesawrapper.c | 7 ------- src/mainboard/amd/thatcher/romstage.c | 10 ++++++---- src/mainboard/asrock/imb-a180/agesawrapper.c | 7 ------- src/mainboard/asrock/imb-a180/romstage.c | 4 ++++ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 7 ------- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 4 ++++ src/mainboard/lenovo/g505s/agesawrapper.c | 7 ------- src/mainboard/lenovo/g505s/romstage.c | 4 ++++ 12 files changed, 26 insertions(+), 46 deletions(-) diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 22522db..242aa27 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 0a982b6..1ff7a0b 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -53,6 +53,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index c457fa3..b4b39d0 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 886ca57..17daa64 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -45,6 +45,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index cc3c069..7425eac 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 0dee909..f7a21ed 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -46,13 +46,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; u8 byte; - device_t dev; + pci_devfn_t dev; + AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + /* Set LPC decode enables. */ + dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + hudson_lpc_port80(); - //__asm__ volatile ("1: jmp 1b"); - /* TODO: */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ pci_write_config8(dev, 0x48, byte); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 62fc053..1412392 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -133,8 +133,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -151,11 +149,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 877d458..8315501 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -58,6 +58,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + hudson_lpc_port80(); /* Enable the AcpiMmio space */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 5ae2c68..086032d 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -41,6 +41,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ b/src/mainboard/lenovo/g505s/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 5ae2c68..086032d 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -41,6 +41,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + /* Set LPC decode enables. */ + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + pci_write_config32(dev, 0x44, 0xff03ffd5); + hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) {

1 0

Patch set updated for coreboot: 9290dab AGESA: Common agesawrapper for S3 resume
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7162 -gerrit commit 9290dabbc79bbcc275a8e57250487b6ec9105e5b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 20 07:41:20 2014 +0300 AGESA: Common agesawrapper for S3 resume Change-Id: I27cd073331659e47d241a0ce249b2d080b4bab5c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 4 +- src/cpu/amd/agesa/agesawrapper_s3.c | 147 +++++++++++++++++++++ src/mainboard/amd/olivehill/romstage.c | 1 + src/mainboard/amd/parmer/romstage.c | 1 + src/mainboard/amd/thatcher/romstage.c | 1 + src/mainboard/asrock/imb-a180/romstage.c | 1 + src/mainboard/asus/f2a85-m/romstage.c | 1 + src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 1 + src/mainboard/lenovo/g505s/romstage.c | 1 + src/northbridge/amd/agesa/agesawrapper_call.h | 2 + src/northbridge/amd/agesa/family12/agesawrapper.c | 3 - src/northbridge/amd/agesa/family12/northbridge.c | 3 + src/northbridge/amd/agesa/family14/agesawrapper.c | 119 ----------------- src/northbridge/amd/agesa/family14/northbridge.c | 6 +- src/northbridge/amd/agesa/family15/agesawrapper.c | 3 - src/northbridge/amd/agesa/family15/northbridge.c | 3 + .../amd/agesa/family15rl/agesawrapper.c | 127 ------------------ src/northbridge/amd/agesa/family15rl/northbridge.c | 7 +- .../amd/agesa/family15tn/agesawrapper.c | 127 ------------------ src/northbridge/amd/agesa/family15tn/northbridge.c | 7 +- .../amd/agesa/family16kb/agesawrapper.c | 127 ------------------ src/northbridge/amd/agesa/family16kb/northbridge.c | 7 +- 22 files changed, 184 insertions(+), 515 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 668efbe..1b7ff3c 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,8 +24,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += s3_resume.c -ramstage-y += s3_resume.c +romstage-y += s3_resume.c agesawrapper_s3.c +ramstage-y += s3_resume.c agesawrapper_s3.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/agesawrapper_s3.c b/src/cpu/amd/agesa/agesawrapper_s3.c new file mode 100644 index 0000000..b9f5051 --- /dev/null +++ b/src/cpu/amd/agesa/agesawrapper_s3.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> + +#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG_(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +#ifndef __PRE_RAM__ +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + + status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct(&AmdInterfaceParams); + + return status; +} +#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 1ff7a0b..b1dcb58 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -102,6 +102,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 17daa64..fe84a90 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -85,6 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index f7a21ed..6a300d6 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -99,6 +99,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 8315501..24fa194 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -126,6 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 385dad4..57450ee 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -144,6 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 086032d..449a8c1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -81,6 +81,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 086032d..449a8c1 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -81,6 +81,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h index 3720dd3..55742d4 100644 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ b/src/northbridge/amd/agesa/agesawrapper_call.h @@ -63,9 +63,11 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) /* TODO: These families do not pass valid HeapStatus. */ #define AGESA_EVENTLOG(status) \ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0) +#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x) #else #define AGESA_EVENTLOG(status, heapstatus) \ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) +#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x,y) #endif #endif diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 39b4f75..9a39c0e 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -357,9 +357,6 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 1e22025..bcebcd9 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -774,6 +774,9 @@ static void domain_enable_resources(device_t dev) sb_Mid_Post_Init(); #endif + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index 84a01b0..e182830 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -335,9 +335,6 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -402,122 +399,6 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitresume(VOID) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(VOID) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - - OemAgesaSaveMtrr(); - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} -#endif /* #ifndef __PRE_RAM__ */ - AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) { AGESA_STATUS status; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a604718..aec7157 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -771,8 +771,12 @@ static void domain_enable_resources(device_t dev) /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - if (!acpi_is_wakeup_s3()) + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 5c99551..4641881 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -355,9 +355,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5a53371..de7d026 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -707,6 +707,9 @@ static void domain_enable_resources(device_t dev) #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init(); #endif + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 4f2e535..7685411 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -260,9 +260,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -345,127 +342,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index a0f299b..c5924d2 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -700,9 +700,12 @@ static void domain_enable_resources(struct device *dev) AGESAWRAPPER(fchs3laterestore); /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 4f2e535..7685411 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -260,9 +260,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -345,127 +342,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index a98d1e9..54a5c69 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -698,9 +698,12 @@ static void domain_enable_resources(device_t dev) AGESAWRAPPER(fchs3laterestore); /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 4f2e535..7685411 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -260,9 +260,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -345,127 +342,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index def29d1..849f40c 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -740,9 +740,12 @@ static void domain_enable_resources(device_t dev) AGESAWRAPPER(fchs3laterestore); /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); }

1 0

Patch set updated for coreboot: eae1abf AGESA fam16kb: Move clearing of NoSnoopEnable bit
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7603 -gerrit commit eae1abfab4b5fe7bd75bd47adc800c0e6a0ea546 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 16:03:12 2014 +0200 AGESA fam16kb: Move clearing of NoSnoopEnable bit Originally from commit 4ca72139 move this code now from cpu/ to northbridge/. Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 18 ------------------ src/northbridge/amd/agesa/family16kb/northbridge.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index a0a3516..26442f4 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -19,10 +19,6 @@ #include <arch/acpi.h> #include <bootstate.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> @@ -38,20 +34,6 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB) - device_t dev; - u32 value; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); -#endif - #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 72967c1..def29d1 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -653,9 +653,25 @@ static const struct pci_driver family10_northbridge __pci_driver = { .device = PCI_DEVICE_ID_AMD_10H_NB_HT, }; +static void fam16_finalize(void *chip_info) +{ + device_t dev; + u32 value; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); +} + struct chip_operations northbridge_amd_agesa_family16kb_ops = { CHIP_NAME("AMD FAM16 Northbridge") .enable_dev = 0, + .final = fam16_finalize, }; static void domain_read_resources(device_t dev)

1 0

Patch set updated for coreboot: 8a30d6a AGESA fam14: Move agesawrapper_amdinitmmio()
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7163 -gerrit commit 8a30d6a1e0d05cd31b3eef6ebccaf543918fc1b1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 14:03:29 2014 +0200 AGESA fam14: Move agesawrapper_amdinitmmio() Enabling MMCONF PCI-e configuration access should be done before console_init(). This will likely move further to bootblock one day. Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/romstage.c | 5 ++--- src/mainboard/amd/inagua/romstage.c | 5 ++--- src/mainboard/amd/persimmon/romstage.c | 5 ++--- src/mainboard/amd/south_station/romstage.c | 5 ++--- src/mainboard/amd/union_station/romstage.c | 5 ++--- src/mainboard/asrock/e350m1/romstage.c | 5 ++--- src/mainboard/gizmosphere/gizmo/romstage.c | 5 ++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 5 ++--- src/mainboard/lippert/frontrunner-af/romstage.c | 5 ++--- src/mainboard/lippert/toucan-af/romstage.c | 5 ++--- 10 files changed, 20 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index b1e9a61..c011038 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -43,6 +43,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -62,9 +64,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - post_code(0x32); - agesawrapper_amdinitmmio(); - /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3a5c761..68822e0 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -54,6 +54,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5434ed3..b0c1624 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -60,6 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -78,9 +80,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 7dcd9b2..727b92d 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -55,6 +55,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index ac583dd..4d31d2b 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -50,6 +50,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -67,9 +69,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index c7c71a1..ea59a8d 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,6 +55,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 92b5292..5132eef 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -68,6 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr.hi = 0; wrmsr (MSR_PSTATE_CONTROL, msr); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -86,9 +88,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 534bdc4..d7fa6bc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -76,6 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -94,9 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index c4bf978..52da850 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -59,6 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -77,9 +79,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 9d99894..13d6f66 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -60,6 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -78,9 +80,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset();

1 0

Patch set updated for coreboot: 4113d03 AGESA: Add common eventlog
by Kyösti Mälkki 02 Dec '14

02 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7161 -gerrit commit 4113d030bf45e1a1f067a18c51afdffe44890960 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 16:18:00 2014 +0300 AGESA: Add common eventlog Change-Id: Ibbf10a53ea671990d336340fdc96dfb37b5defd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/Makefile.inc | 7 ++---- src/northbridge/amd/agesa/agesawrapper.h | 4 ---- src/northbridge/amd/agesa/agesawrapper_call.h | 2 +- src/northbridge/amd/agesa/family12/agesawrapper.c | 26 ---------------------- src/northbridge/amd/agesa/family14/agesawrapper.c | 26 ---------------------- .../amd/agesa/family15rl/agesawrapper.c | 26 ---------------------- .../amd/agesa/family15tn/agesawrapper.c | 26 ---------------------- .../amd/agesa/family16kb/agesawrapper.c | 26 ---------------------- 8 files changed, 3 insertions(+), 140 deletions(-) diff --git a/src/northbridge/amd/agesa/Makefile.inc b/src/northbridge/amd/agesa/Makefile.inc index 6eb4941..1eed658 100644 --- a/src/northbridge/amd/agesa/Makefile.inc +++ b/src/northbridge/amd/agesa/Makefile.inc @@ -24,8 +24,5 @@ subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += def_callouts.c -ramstage-y += def_callouts.c - -romstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c -ramstage-$(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY15) += eventlog.c +romstage-y += def_callouts.c eventlog.c +ramstage-y += def_callouts.c eventlog.c diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index 49f6666..e1eb69b 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -48,11 +48,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void); AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 -AGESA_STATUS agesawrapper_amdreadeventlog(void); -#else AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); -#endif AGESA_STATUS agesawrapper_amdinitcpuio(void); AGESA_STATUS agesawrapper_amdinitmmio(void); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h index 71997a8..3720dd3 100644 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ b/src/northbridge/amd/agesa/agesawrapper_call.h @@ -62,7 +62,7 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) #if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 /* TODO: These families do not pass valid HeapStatus. */ #define AGESA_EVENTLOG(status) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog() + if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0) #else #define AGESA_EVENTLOG(status, heapstatus) \ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 7309262..39b4f75 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -425,29 +425,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdreadeventlog(VOID) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, - "\nEventLog: EventClass = %lx, EventInfo = %lx.\n", - AmdEventParams.EventClass, AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %lx, Param2 = %lx.\n", - AmdEventParams.DataParam1, AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %lx, Param4 = %lx.\n", - AmdEventParams.DataParam3, AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index 1f580ef..84a01b0 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -538,29 +538,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdreadeventlog(VOID) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = NULL; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, - "\nEventLog: EventClass = %lx, EventInfo = %lx.\n", - AmdEventParams.EventClass, AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %lx, Param2 = %lx.\n", - AmdEventParams.DataParam1, AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %lx, Param4 = %lx.\n", - AmdEventParams.DataParam3, AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 2099a49..4f2e535 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -469,29 +469,3 @@ AGESA_STATUS agesawrapper_amdS3Save(void) } #endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 2099a49..4f2e535 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -469,29 +469,3 @@ AGESA_STATUS agesawrapper_amdS3Save(void) } #endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 2099a49..4f2e535 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -469,29 +469,3 @@ AGESA_STATUS agesawrapper_amdS3Save(void) } #endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", - (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", - (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", - (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); - } - - return Status; -}

1 0

New patch to review for coreboot: 2f68863 southbridge/amd/agesa/hudson/early_setup.c: Use IS_ENABLED macro
by Edward O'Callaghan 02 Dec '14

02 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7624 -gerrit commit 2f688636275fad0a73f0c75b7ef505e2e0674b16 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 17:44:47 2014 +1100 southbridge/amd/agesa/hudson/early_setup.c: Use IS_ENABLED macro Change-Id: I2adb5a8fe2cede988cc6fdef5ff81da86d267175 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/early_setup.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 039df20..1b9b689 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -123,7 +123,7 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) return nvram_pos; } -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) int acpi_get_sleep_type(void) { u16 tmp = inw(ACPI_PM1_CNT_BLK); @@ -131,14 +131,12 @@ int acpi_get_sleep_type(void) /* printk(BIOS_DEBUG, "SLP_TYP type was %x\n", tmp); */ return (int)tmp; } -#endif -#if CONFIG_HAVE_ACPI_RESUME int acpi_is_wakeup_early(void) { return (acpi_get_sleep_type() == 3); } -#endif +#endif /* CONFIG_HAVE_ACPI_RESUME */ unsigned long get_top_of_ram(void) { @@ -153,4 +151,4 @@ unsigned long get_top_of_ram(void) return (unsigned long) xdata; } -#endif +#endif /* _HUDSON_EARLY_SETUP_C_ */

1 0

New patch to review for coreboot: 5d0753e RISCV: get RISCV to build again
by Ronald G. Minnich 02 Dec '14

02 Dec '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7623 -gerrit commit 5d0753e194dd58389b9a6e3a89f243e07314c240 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Tue Dec 2 04:07:02 2014 +0000 RISCV: get RISCV to build again This makes lzmadecode 64-bit clean (I hope). It also cleans up a few other nits. Change-Id: I24492e9f357e8d3a6de6abc351267f900eb4a19a Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 4 +--- src/arch/riscv/rom_media.c | 8 -------- src/lib/lzmadecode.c | 3 ++- src/mainboard/emulation/qemu-riscv/uart.c | 1 - 4 files changed, 3 insertions(+), 13 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 394220c..1020fc7 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -41,7 +41,7 @@ bootblock-y += \ $(objcbfs)/bootblock.debug: $(src)/arch/riscv/bootblock.ld $(obj)/ldoptions $$(bootblock-objs) @printf " LINK $(subst $(obj)/,,$(@))\n" - $(LD_bootblock) -m elf64-littleriscv --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/riscv/bootblock.ld + $(LD_bootblock) -m elf64lriscv --gc-sections -static -o $@ -L$(obj) $< -T $(src)/arch/riscv/bootblock.ld endif @@ -58,7 +58,6 @@ romstage-y += \ $(top)/src/lib/memcpy.c \ $(top)/src/lib/memmove.c \ $(top)/src/lib/memset.c -romstage-y += cbmem.c romstage-$(CONFIG_COLLECT_TIMESTAMPS) += timestamp.c @@ -86,7 +85,6 @@ ramstage-y += rom_media.c ramstage-y += stages.c ramstage-y += misc.c ramstage-y += boot.c -ramstage-y += cbmem.c ramstage-y += tables.c ramstage-y += \ $(top)/src/lib/memchr.c \ diff --git a/src/arch/riscv/rom_media.c b/src/arch/riscv/rom_media.c index 712b7c4..8e858cb 100644 --- a/src/arch/riscv/rom_media.c +++ b/src/arch/riscv/rom_media.c @@ -90,11 +90,3 @@ static int init_rom_media_cbfs(struct cbfs_media *media) { int init_default_cbfs_media(struct cbfs_media *media) { return init_rom_media_cbfs(media); } -// bug in coreboot. Fix me. -// even if you have no use for lzma cbfs demands it. -// and the ulzma code is terrible -- full of bad 32/64 bad things. -unsigned long ulzma(unsigned char *src, unsigned char *dst); -unsigned long ulzma(unsigned char *src, unsigned char *dst) -{ - return 0; -} diff --git a/src/lib/lzmadecode.c b/src/lib/lzmadecode.c index fb57f4f..ada7226 100644 --- a/src/lib/lzmadecode.c +++ b/src/lib/lzmadecode.c @@ -20,6 +20,7 @@ */ #include "lzmadecode.h" +#include <stdint.h> #define kNumTopBits 24 #define kTopValue ((UInt32)1 << kNumTopBits) @@ -30,7 +31,7 @@ /* Use 32-bit reads whenever possible to avoid bad flash performance. */ #define RC_READ_BYTE (look_ahead_ptr < 4 ? look_ahead.raw[look_ahead_ptr++] \ - : ((((UInt32) Buffer & 3) || ((SizeT) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ + : ((((uintptr_t) Buffer & 3) || ((SizeT) (BufferLim - Buffer) < 4)) ? (*Buffer++) \ : ((look_ahead.dw = *(UInt32 *)Buffer), (Buffer += 4), (look_ahead_ptr = 1), look_ahead.raw[0]))) #define RC_INIT2 Code = 0; Range = 0xFFFFFFFF; \ diff --git a/src/mainboard/emulation/qemu-riscv/uart.c b/src/mainboard/emulation/qemu-riscv/uart.c index 40192c9..6647cde 100644 --- a/src/mainboard/emulation/qemu-riscv/uart.c +++ b/src/mainboard/emulation/qemu-riscv/uart.c @@ -21,7 +21,6 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> -#include "frontend.h" static uint8_t *buf = (void *)0x3f8; uintptr_t uart_platform_base(int idx)

1 0

New patch to review for coreboot: bfbc0a7 Drop tianocoreboot ("Project PIANO")
by Patrick Georgi 01 Dec '14

01 Dec '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7622 -gerrit commit bfbc0a7518186db168f8441479703cf6e3c369b2 Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Dec 1 22:18:26 2014 +0100 Drop tianocoreboot ("Project PIANO") There are four other approaches to provide UEFI on top of coreboot that actually get to a UEFI shell. No need to keep this experiment and confuse users. Change-Id: I81c52e24099852f6daf0d5725aec707bdfd75ae1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- payloads/tianocoreboot/Makefile | 80 ---- payloads/tianocoreboot/README | 27 -- payloads/tianocoreboot/include/BootMode.h | 38 -- .../include/EfiFirmwareVolumeHeader.h | 213 --------- payloads/tianocoreboot/include/EfiTypes.h | 297 ------------ .../tianocoreboot/include/MemoryAllocationHob.h | 34 -- payloads/tianocoreboot/include/PeiHob.h | 257 ---------- payloads/tianocoreboot/include/PiFirmwareFile.h | 494 ------------------- payloads/tianocoreboot/include/coff.h | 106 ----- payloads/tianocoreboot/include/efi.h | 36 -- payloads/tianocoreboot/libpayload.config | 58 --- payloads/tianocoreboot/tianocoreboot.c | 529 --------------------- 12 files changed, 2169 deletions(-) diff --git a/payloads/tianocoreboot/Makefile b/payloads/tianocoreboot/Makefile deleted file mode 100644 index 3ac541f..0000000 --- a/payloads/tianocoreboot/Makefile +++ /dev/null @@ -1,80 +0,0 @@ -## -## This file is part of the TianoCoreBoot project. -## -## Copyright (C) 2013 Google Inc. -## -## This program is free software; you can redistribute it and/or modify -## it under the terms of the GNU General Public License as published by -## the Free Software Foundation; version 2 of the License. -## -## This program is distributed in the hope that it will be useful, -## but WITHOUT ANY WARRANTY; without even the implied warranty of -## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -## GNU General Public License for more details. -## -## You should have received a copy of the GNU General Public License -## along with this program; if not, write to the Free Software -## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -## - -src := $(shell pwd) -srctree := $(src) -obj ?= $(src)/build - -export V := $(V) - -CONFIG_SHELL := sh -UNAME_RELEASE := $(shell uname -r) -HAVE_DOTCONFIG := $(wildcard .config) -MAKEFLAGS += -rR --no-print-directory - -# Make is silent per default, but 'make V=1' will show all compiler calls. -ifneq ($(V),1) -Q := @ -endif - -LIBCONFIG_PATH := ../libpayload -LIBPAYLOAD_DIR := $(obj)/libpayload -LPCC := $(LIBPAYLOAD_DIR)/libpayload/bin/lpgcc -LPAS := $(LIBPAYLOAD_DIR)/libpayload/bin/lpas -HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/libpayload/lib/libpayload.a) -OBJCOPY ?= objcopy - -INCLUDES = -Iinclude -CFLAGS := -Wall -Werror -Os $(INCLUDES) -OBJECTS = tianocoreboot.o -OBJS = $(patsubst %,$(obj)/%,$(OBJECTS)) -TARGET = $(obj)/tianocoreboot.elf - -all: $(TARGET) - -$(TARGET): prepare $(OBJS) libpayload - $(Q)printf " LINK $(subst $(shell pwd)/,,$(@))\n" - $(Q)CC="$(CC)" $(LPCC) -o $@ $(OBJS) - $(Q)$(OBJCOPY) --only-keep-debug $@ $(TARGET).debug - $(Q)$(OBJCOPY) --strip-debug $@ - $(Q)$(OBJCOPY) --add-gnu-debuglink=$(TARGET).debug $@ - -$(obj)/%.o: $(src)/%.c libpayload - $(Q)printf " CC $(subst $(shell pwd)/,,$(@))\n" - $(Q)CC="$(CC)" $(LPCC) $(CFLAGS) -c -o $@ $< - -ifneq ($(strip $(HAVE_LIBPAYLOAD)),) -libpayload: - $(Q)printf "Found Libpayload $(LIBPAYLOAD_DIR).\n" -else -libpayload: - $(Q)printf "Building libpayload @ $(LIBCONFIG_PATH).\n" - $(Q)cp libpayload.config .config - $(Q)make -C $(LIBCONFIG_PATH) distclean - $(Q)make -C $(LIBCONFIG_PATH) DESTDIR=$(LIBPAYLOAD_DIR) install DOTCONFIG=$(shell pwd)/.config -endif - -prepare: - $(Q)mkdir -p $(obj) - -clean: - $(Q)rm -rf $(obj) $(LIBPAYLOAD_DIR) .xcompile .config .config.old - -.PHONY: $(PHONY) clean - diff --git a/payloads/tianocoreboot/README b/payloads/tianocoreboot/README deleted file mode 100644 index 0dce08b..0000000 --- a/payloads/tianocoreboot/README +++ /dev/null @@ -1,27 +0,0 @@ -mkdir Tiano -cd Tiano -svn co https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2 edk2 --username guest -cd edk2 -svn co https://edk2-fatdriver2.svn.sourceforge.net/svnroot/edk2-fatdriver2/trunk/F… FatPkg --username guest -cd .. - -make -C edk2/BaseTools - -export EDK_TOOLS_PATH=$(pwd)/edk2/BaseTools -cd edk2 -. ./edksetup.sh BaseTools - -vi Conf/target.txt - -ACTIVE_PLATFORM = OvmfPkg/OvmfPkgIa32.dsc -TOOL_CHAIN_TAG = GCC46 - ------- -#TODO -TARGET_ARCH = IA32 X64 ------- - -build -D DEBUG_ON_SERIAL_PORT - ---> ./Build/OvmfIa32/DEBUG_GCC46/FV/DXEFV.Fv - diff --git a/payloads/tianocoreboot/include/BootMode.h b/payloads/tianocoreboot/include/BootMode.h deleted file mode 100644 index 38b7c0c..0000000 --- a/payloads/tianocoreboot/include/BootMode.h +++ /dev/null @@ -1,38 +0,0 @@ -/*++ - -Copyright (c) 2004, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - BootMode.h - -Abstract: - - This includes for the Boot mode information. - ---*/ - -#ifndef _EFI_BOOT_MODE_H -#define _EFI_BOOT_MODE_H - -#define BOOT_WITH_FULL_CONFIGURATION 0x00 -#define BOOT_WITH_MINIMAL_CONFIGURATION 0x01 -#define BOOT_ASSUMING_NO_CONFIGURATION_CHANGES 0x02 -#define BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS 0x03 -#define BOOT_WITH_DEFAULT_SETTINGS 0x04 -#define BOOT_ON_S4_RESUME 0x05 -#define BOOT_ON_S5_RESUME 0x06 -#define BOOT_ON_S2_RESUME 0x10 -#define BOOT_ON_S3_RESUME 0x11 -#define BOOT_ON_FLASH_UPDATE 0x12 -#define BOOT_IN_RECOVERY_MODE 0x20 -#define BOOT_IN_RECOVERY_MODE_MASK 0x40 -#define BOOT_SPECIAL_MASK 0x80 -#endif diff --git a/payloads/tianocoreboot/include/EfiFirmwareVolumeHeader.h b/payloads/tianocoreboot/include/EfiFirmwareVolumeHeader.h deleted file mode 100644 index 9bbab35..0000000 --- a/payloads/tianocoreboot/include/EfiFirmwareVolumeHeader.h +++ /dev/null @@ -1,213 +0,0 @@ -/*++ - -Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - EfiFirmwareVolumeHeader.h - -Abstract: - - Defines data structure that is the volume header found at the beginning of - all firmware volumes that are either memory mapped, or have an - associated FirmwareVolumeBlock protocol. - ---*/ - -#ifndef _EFI_FIRMWARE_VOLUME_HEADER_H_ -#define _EFI_FIRMWARE_VOLUME_HEADER_H_ - - -// -// Firmware Volume Block Attributes bit definitions -// They are the shared between Framework and PI1.0. -// -typedef UINT32 EFI_FVB_ATTRIBUTES; - -#define EFI_FVB_READ_DISABLED_CAP 0x00000001 -#define EFI_FVB_READ_ENABLED_CAP 0x00000002 -#define EFI_FVB_READ_STATUS 0x00000004 - -#define EFI_FVB_WRITE_DISABLED_CAP 0x00000008 -#define EFI_FVB_WRITE_ENABLED_CAP 0x00000010 -#define EFI_FVB_WRITE_STATUS 0x00000020 - -#define EFI_FVB_LOCK_CAP 0x00000040 -#define EFI_FVB_LOCK_STATUS 0x00000080 - -#define EFI_FVB_STICKY_WRITE 0x00000200 -#define EFI_FVB_MEMORY_MAPPED 0x00000400 -#define EFI_FVB_ERASE_POLARITY 0x00000800 - - -#if (PI_SPECIFICATION_VERSION < 0x00010000) - -#define EFI_FVB_ALIGNMENT_CAP 0x00008000 -#define EFI_FVB_ALIGNMENT_2 0x00010000 -#define EFI_FVB_ALIGNMENT_4 0x00020000 -#define EFI_FVB_ALIGNMENT_8 0x00040000 -#define EFI_FVB_ALIGNMENT_16 0x00080000 -#define EFI_FVB_ALIGNMENT_32 0x00100000 -#define EFI_FVB_ALIGNMENT_64 0x00200000 -#define EFI_FVB_ALIGNMENT_128 0x00400000 -#define EFI_FVB_ALIGNMENT_256 0x00800000 -#define EFI_FVB_ALIGNMENT_512 0x01000000 -#define EFI_FVB_ALIGNMENT_1K 0x02000000 -#define EFI_FVB_ALIGNMENT_2K 0x04000000 -#define EFI_FVB_ALIGNMENT_4K 0x08000000 -#define EFI_FVB_ALIGNMENT_8K 0x10000000 -#define EFI_FVB_ALIGNMENT_16K 0x20000000 -#define EFI_FVB_ALIGNMENT_32K 0x40000000 -#define EFI_FVB_ALIGNMENT_64K 0x80000000 - -#define EFI_FVB_CAPABILITIES (EFI_FVB_READ_DISABLED_CAP | \ - EFI_FVB_READ_ENABLED_CAP | \ - EFI_FVB_WRITE_DISABLED_CAP | \ - EFI_FVB_WRITE_ENABLED_CAP | \ - EFI_FVB_LOCK_CAP \ - ) - -#define EFI_FVB_STATUS (EFI_FVB_READ_STATUS | EFI_FVB_WRITE_STATUS | EFI_FVB_LOCK_STATUS) - - - -#else - -#define EFI_FVB2_READ_LOCK_CAP 0x00001000 -#define EFI_FVB2_READ_LOCK_STATUS 0x00002000 - -#define EFI_FVB2_WRITE_LOCK_CAP 0x00004000 -#define EFI_FVB2_WRITE_LOCK_STATUS 0x00008000 - -#define EFI_FVB2_ALIGNMENT 0x001F0000 -#define EFI_FVB2_ALIGNMENT_1 0x00000000 -#define EFI_FVB2_ALIGNMENT_2 0x00010000 -#define EFI_FVB2_ALIGNMENT_4 0x00020000 -#define EFI_FVB2_ALIGNMENT_8 0x00030000 -#define EFI_FVB2_ALIGNMENT_16 0x00040000 -#define EFI_FVB2_ALIGNMENT_32 0x00050000 -#define EFI_FVB2_ALIGNMENT_64 0x00060000 -#define EFI_FVB2_ALIGNMENT_128 0x00070000 -#define EFI_FVB2_ALIGNMENT_256 0x00080000 -#define EFI_FVB2_ALIGNMENT_512 0x00090000 -#define EFI_FVB2_ALIGNMENT_1K 0x000A0000 -#define EFI_FVB2_ALIGNMENT_2K 0x000B0000 -#define EFI_FVB2_ALIGNMENT_4K 0x000C0000 -#define EFI_FVB2_ALIGNMENT_8K 0x000D0000 -#define EFI_FVB2_ALIGNMENT_16K 0x000E0000 -#define EFI_FVB2_ALIGNMENT_32K 0x000F0000 -#define EFI_FVB2_ALIGNMENT_64K 0x00100000 -#define EFI_FVB2_ALIGNMENT_128K 0x00110000 -#define EFI_FVB2_ALIGNMENT_256K 0x00120000 -#define EFI_FVB2_ALIGNMENT_512K 0x00130000 -#define EFI_FVB2_ALIGNMENT_1M 0x00140000 -#define EFI_FVB2_ALIGNMENT_2M 0x00150000 -#define EFI_FVB2_ALIGNMENT_4M 0x00160000 -#define EFI_FVB2_ALIGNMENT_8M 0x00170000 -#define EFI_FVB2_ALIGNMENT_16M 0x00180000 -#define EFI_FVB2_ALIGNMENT_32M 0x00190000 -#define EFI_FVB2_ALIGNMENT_64M 0x001A0000 -#define EFI_FVB2_ALIGNMENT_128M 0x001B0000 -#define EFI_FVB2_ALIGNMENT_256M 0x001C0000 -#define EFI_FVB2_ALIGNMENT_512M 0x001D0000 -#define EFI_FVB2_ALIGNMENT_1G 0x001E0000 -#define EFI_FVB2_ALIGNMENT_2G 0x001F0000 - -#define EFI_FVB_CAPABILITIES (EFI_FVB_READ_DISABLED_CAP | \ - EFI_FVB_READ_ENABLED_CAP | \ - EFI_FVB_WRITE_DISABLED_CAP | \ - EFI_FVB_WRITE_ENABLED_CAP | \ - EFI_FVB_LOCK_CAP | \ - EFI_FVB2_READ_LOCK_CAP | \ - EFI_FVB2_WRITE_LOCK_CAP ) - -#define EFI_FVB_STATUS (EFI_FVB_READ_STATUS | EFI_FVB_WRITE_STATUS | \ - EFI_FVB_LOCK_STATUS | EFI_FVB2_READ_LOCK_STATUS | \ - EFI_FVB2_WRITE_LOCK_STATUS ) - - - -// -// Extended Header Header. Located via ExtHeaderOffset. -// The extended headers follow each other in memory and are -// terminated by ExtHeaderType EFI_FV_EXT_TYPE_END -// -#define EFI_FV_EXT_TYPE_END 0x00 -typedef struct { - UINT16 ExtEntrySize; - UINT16 ExtEntryType; -} EFI_FIRMWARE_VOLUME_EXT_ENTRY; - -// -// GUID that maps OEM file types to GUIDs -// -#define EFI_FV_EXT_TYPE_OEM_TYPE 0x01 -typedef struct { - EFI_FIRMWARE_VOLUME_EXT_ENTRY Hdr; - UINT32 TypeMask; - EFI_GUID Types[1]; -} EFI_FIRMWARE_VOLUME_EXT_HEADER_OEM_TYPE; - -// -// Unique name of the FV -// -typedef struct { - EFI_GUID FvName; - UINT32 ExtHeaderSize; -} EFI_FIRMWARE_VOLUME_EXT_HEADER; - - -#endif - - -// -// Firmware Volume Header Revision definition -// -#define EFI_FVH_REVISION 0x01 -// -// PI1.0 define Firmware Volume Header Revision to 2 -// -#define EFI_FVH_PI_REVISION 0x02 - -// -// Firmware Volume Header Signature definition -// -#define EFI_FVH_SIGNATURE EFI_SIGNATURE_32 ('_', 'F', 'V', 'H') - -// -// Firmware Volume Header Block Map Entry definition -// -typedef struct { - UINT32 NumBlocks; - UINT32 BlockLength; -} EFI_FV_BLOCK_MAP_ENTRY; - -// -// Firmware Volume Header definition -// -typedef struct { - UINT8 ZeroVector[16]; - EFI_GUID FileSystemGuid; - UINT64 FvLength; - UINT32 Signature; - EFI_FVB_ATTRIBUTES Attributes; - UINT16 HeaderLength; - UINT16 Checksum; -#if (PI_SPECIFICATION_VERSION < 0x00010000) - UINT8 Reserved[3]; -#else - UINT16 ExtHeaderOffset; - UINT8 Reserved[1]; -#endif - UINT8 Revision; - EFI_FV_BLOCK_MAP_ENTRY FvBlockMap[1]; -} EFI_FIRMWARE_VOLUME_HEADER; - -#endif diff --git a/payloads/tianocoreboot/include/EfiTypes.h b/payloads/tianocoreboot/include/EfiTypes.h deleted file mode 100644 index 49760d3..0000000 --- a/payloads/tianocoreboot/include/EfiTypes.h +++ /dev/null @@ -1,297 +0,0 @@ -/*++ - -Copyright (c) 2004 - 2010, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - EfiTypes.h - -Abstract: - - EFI defined types. Use these types when ever possible! - ---*/ - -#ifndef _EFI_TYPES_H_ -#define _EFI_TYPES_H_ - -// -// EFI Data Types based on ANSI C integer types in EfiBind.h -// -typedef uint8_t BOOLEAN; -typedef intn_t INTN; -typedef uintn_t UINTN; -typedef int8_t INT8; -typedef uint8_t UINT8; -typedef int16_t INT16; -typedef uint16_t UINT16; -typedef int32_t INT32; -typedef uint32_t UINT32; -typedef int64_t INT64; -typedef uint64_t UINT64; -typedef char CHAR8; -typedef uint16_t CHAR16; -typedef UINT64 EFI_LBA; - -// -// Modifiers for EFI Data Types used to self document code. -// Please see EFI coding convention for proper usage. -// -#ifndef IN -// -// Some other envirnments use this construct, so #ifndef to prevent -// mulitple definition. -// -#define IN -#define OUT -#define OPTIONAL -#endif - -#ifndef UNALIGNED -#define UNALIGNED -#endif - -// -// Modifiers for EFI Runtime and Boot Services -// -#define EFI_RUNTIMESERVICE -#define EFI_BOOTSERVICE - -// -// Boot Service add in EFI 1.1 -// -#define EFI_BOOTSERVICE11 - -// -// Modifiers to absract standard types to aid in debug of problems -// -#define CONST const -#define STATIC static -#define VOID void -#define VOLATILE volatile - -// -// Modifier to ensure that all protocol member functions and EFI intrinsics -// use the correct C calling convention. All protocol member functions and -// EFI intrinsics are required to modify thier member functions with EFIAPI. -// -#ifndef EFIAPI - #define EFIAPI _EFIAPI -#endif - -// -// EFI Constants. They may exist in other build structures, so #ifndef them. -// -#ifndef TRUE -#define TRUE ((BOOLEAN) (1 == 1)) -#endif - -#ifndef FALSE -#define FALSE ((BOOLEAN) (0 == 1)) -#endif - -#ifndef NULL -#define NULL ((VOID *) 0) -#endif -// -// EFI Data Types derived from other EFI data types. -// -typedef UINTN EFI_STATUS; - -typedef VOID *EFI_HANDLE; -#define NULL_HANDLE ((VOID *) 0) - -typedef VOID *EFI_EVENT; -typedef UINTN EFI_TPL; - -typedef struct { - UINT32 Data1; - UINT16 Data2; - UINT16 Data3; - UINT8 Data4[8]; -} EFI_GUID; - -typedef union { - EFI_GUID Guid; - UINT8 Raw[16]; -} EFI_GUID_UNION; - -// -// EFI Time Abstraction: -// Year: 2000 - 20XX -// Month: 1 - 12 -// Day: 1 - 31 -// Hour: 0 - 23 -// Minute: 0 - 59 -// Second: 0 - 59 -// Nanosecond: 0 - 999,999,999 -// TimeZone: -1440 to 1440 or 2047 -// -typedef struct { - UINT16 Year; - UINT8 Month; - UINT8 Day; - UINT8 Hour; - UINT8 Minute; - UINT8 Second; - UINT8 Pad1; - UINT32 Nanosecond; - INT16 TimeZone; - UINT8 Daylight; - UINT8 Pad2; -} EFI_TIME; - -// -// Bit definitions for EFI_TIME.Daylight -// -#define EFI_TIME_ADJUST_DAYLIGHT 0x01 -#define EFI_TIME_IN_DAYLIGHT 0x02 - -// -// Value definition for EFI_TIME.TimeZone -// -#define EFI_UNSPECIFIED_TIMEZONE 0x07FF - -// -// Networking -// -typedef struct { - UINT8 Addr[4]; -} EFI_IPv4_ADDRESS; - -typedef struct { - UINT8 Addr[16]; -} EFI_IPv6_ADDRESS; - -typedef struct { - UINT8 Addr[32]; -} EFI_MAC_ADDRESS; - -typedef union { - UINT32 Addr[4]; - EFI_IPv4_ADDRESS v4; - EFI_IPv6_ADDRESS v6; -} EFI_IP_ADDRESS; - -typedef enum { - EfiReservedMemoryType, - EfiLoaderCode, - EfiLoaderData, - EfiBootServicesCode, - EfiBootServicesData, - EfiRuntimeServicesCode, - EfiRuntimeServicesData, - EfiConventionalMemory, - EfiUnusableMemory, - EfiACPIReclaimMemory, - EfiACPIMemoryNVS, - EfiMemoryMappedIO, - EfiMemoryMappedIOPortSpace, - EfiPalCode, - EfiMaxMemoryType -} EFI_MEMORY_TYPE; - -typedef enum { - AllocateAnyPages, - AllocateMaxAddress, - AllocateAddress, - MaxAllocateType -} EFI_ALLOCATE_TYPE; - -typedef struct { - UINT64 Signature; - UINT32 Revision; - UINT32 HeaderSize; - UINT32 CRC32; - UINT32 Reserved; -} EFI_TABLE_HEADER; - -// -// possible caching types for the memory range -// -#define EFI_MEMORY_UC 0x0000000000000001 -#define EFI_MEMORY_WC 0x0000000000000002 -#define EFI_MEMORY_WT 0x0000000000000004 -#define EFI_MEMORY_WB 0x0000000000000008 -#define EFI_MEMORY_UCE 0x0000000000000010 - -// -// physical memory protection on range -// -#define EFI_MEMORY_WP 0x0000000000001000 -#define EFI_MEMORY_RP 0x0000000000002000 -#define EFI_MEMORY_XP 0x0000000000004000 - -// -// range requires a runtime mapping -// -#define EFI_MEMORY_RUNTIME 0x8000000000000000ULL - -typedef UINT64 EFI_PHYSICAL_ADDRESS; -typedef UINT64 EFI_VIRTUAL_ADDRESS; - -#define EFI_MEMORY_DESCRIPTOR_VERSION 1 -typedef struct { - UINT32 Type; - UINT32 Pad; - EFI_PHYSICAL_ADDRESS PhysicalStart; - EFI_VIRTUAL_ADDRESS VirtualStart; - UINT64 NumberOfPages; - UINT64 Attribute; -} EFI_MEMORY_DESCRIPTOR; - -// -// The EFI memory allocation functions work in units of EFI_PAGEs that are -// 4K. This should in no way be confused with the page size of the processor. -// An EFI_PAGE is just the quanta of memory in EFI. -// -#define EFI_PAGE_SIZE 4096 -#define EFI_PAGE_MASK 0xFFF -#define EFI_PAGE_SHIFT 12 - -#define EFI_SIZE_TO_PAGES(a) (((a) >> EFI_PAGE_SHIFT) + (((a) & EFI_PAGE_MASK) ? 1 : 0)) - -#define EFI_PAGES_TO_SIZE(a) ( (a) << EFI_PAGE_SHIFT) - -// -// ALIGN_POINTER - aligns a pointer to the lowest boundry -// -#define ALIGN_POINTER(p, s) ((VOID *) (p + ((s - ((UINTN) p)) & (s - 1)))) - -// -// ALIGN_VARIABLE - aligns a variable up to the next natural boundry for int size of a processor -// -#define ALIGN_VARIABLE(Value, Adjustment) \ - (UINTN) Adjustment = 0; \ - if ((UINTN) Value % sizeof (UINTN)) { \ - (UINTN) Adjustment = sizeof (UINTN) - ((UINTN) Value % sizeof (UINTN)); \ - } \ - Value = (UINTN) Value + (UINTN) Adjustment - -// -// EFI_FIELD_OFFSET - returns the byte offset to a field within a structure -// -#define EFI_FIELD_OFFSET(TYPE,Field) ((UINTN)(&(((TYPE *) 0)->Field))) - -// -// CONTAINING_RECORD - returns a pointer to the structure -// from one of it's elements. -// -#define _CR(Record, TYPE, Field) ((TYPE *) ((CHAR8 *) (Record) - (CHAR8 *) &(((TYPE *) 0)->Field))) - -// -// Define macros to build data structure signatures from characters. -// -#define EFI_SIGNATURE_16(A, B) ((A) | (B << 8)) -#define EFI_SIGNATURE_32(A, B, C, D) (EFI_SIGNATURE_16 (A, B) | (EFI_SIGNATURE_16 (C, D) << 16)) -#define EFI_SIGNATURE_64(A, B, C, D, E, F, G, H) \ - (EFI_SIGNATURE_32 (A, B, C, D) | ((UINT64) (EFI_SIGNATURE_32 (E, F, G, H)) << 32)) - -#endif diff --git a/payloads/tianocoreboot/include/MemoryAllocationHob.h b/payloads/tianocoreboot/include/MemoryAllocationHob.h deleted file mode 100644 index fb06757..0000000 --- a/payloads/tianocoreboot/include/MemoryAllocationHob.h +++ /dev/null @@ -1,34 +0,0 @@ -/** @file - GUIDs for HOBs used in memory allcation - - Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved. - This program and the accompanying materials - are licensed and made available under the terms and conditions of the BSD License - which accompanies this distribution. The full text of the license may be found at - http://opensource.org/licenses/bsd-license.php - - THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, - WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - @par Revision Reference: - GUIDs introduced in PI Version 1.0. - -**/ - -#ifndef __MEMORY_ALLOCATION_GUID_H__ -#define __MEMORY_ALLOCATION_GUID_H__ - -#define EFI_HOB_MEMORY_ALLOC_BSP_STORE_GUID \ - {0x564b33cd, 0xc92a, 0x4593, {0x90, 0xbf, 0x24, 0x73, 0xe4, 0x3c, 0x63, 0x22} }; - -#define EFI_HOB_MEMORY_ALLOC_STACK_GUID \ - {0x4ed4bf27, 0x4092, 0x42e9, {0x80, 0x7d, 0x52, 0x7b, 0x1d, 0x0, 0xc9, 0xbd} } - -#define EFI_HOB_MEMORY_ALLOC_MODULE_GUID \ - {0xf8e21975, 0x899, 0x4f58, {0xa4, 0xbe, 0x55, 0x25, 0xa9, 0xc6, 0xd7, 0x7a} } - -extern EFI_GUID gEfiHobMemoryAllocBspStoreGuid; -extern EFI_GUID gEfiHobMemoryAllocStackGuid; -extern EFI_GUID gEfiHobMemoryAllocModuleGuid; - -#endif diff --git a/payloads/tianocoreboot/include/PeiHob.h b/payloads/tianocoreboot/include/PeiHob.h deleted file mode 100644 index 407ea76..0000000 --- a/payloads/tianocoreboot/include/PeiHob.h +++ /dev/null @@ -1,257 +0,0 @@ -/*++ - -Copyright (c) 2004 - 2011, Intel Corporation. All rights reserved. -This program and the accompanying materials -are licensed and made available under the terms and conditions of the BSD License -which accompanies this distribution. The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - -Module Name: - - PeiHob.h - -Abstract: - - PEI Hand Off Block (HOB) definition. - - The HOB is a memory data structure used to hand-off system information from - PEI to DXE (the next phase). - ---*/ - -#ifndef _PEI_HOB_H_ -#define _PEI_HOB_H_ - -#include "BootMode.h" - -// -// Every Hob must start with this data structure. -// -typedef struct { - UINT16 HobType; - UINT16 HobLength; - UINT32 Reserved; -} EFI_HOB_GENERIC_HEADER; - -// -// End of HOB List HOB -// -#define EFI_HOB_TYPE_END_OF_HOB_LIST 0xffff - -// -// Handoff Information Table HOB -// -#define EFI_HOB_TYPE_HANDOFF 0x0001 - -#define EFI_HOB_HANDOFF_TABLE_VERSION 0x0009 - -typedef UINT32 EFI_BOOT_MODE; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - UINT32 Version; - EFI_BOOT_MODE BootMode; - EFI_PHYSICAL_ADDRESS EfiMemoryTop; - EFI_PHYSICAL_ADDRESS EfiMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryTop; - EFI_PHYSICAL_ADDRESS EfiFreeMemoryBottom; - EFI_PHYSICAL_ADDRESS EfiEndOfHobList; -} EFI_HOB_HANDOFF_INFO_TABLE; - -// -// Memory Descriptor HOB -// -#define EFI_HOB_TYPE_MEMORY_ALLOCATION 0x0002 - -typedef struct { - EFI_GUID Name; - EFI_PHYSICAL_ADDRESS MemoryBaseAddress; - UINT64 MemoryLength; - EFI_MEMORY_TYPE MemoryType; - UINT8 Reserved[4]; -} EFI_HOB_MEMORY_ALLOCATION_HEADER; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; - // - // Additional data pertaining to the "Name" Guid memory - // may go here. - // -} EFI_HOB_MEMORY_ALLOCATION; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; -} EFI_HOB_MEMORY_ALLOCATION_BSP_STORE; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER AllocDescriptor; -} EFI_HOB_MEMORY_ALLOCATION_STACK; - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_HOB_MEMORY_ALLOCATION_HEADER MemoryAllocationHeader; - EFI_GUID ModuleName; - EFI_PHYSICAL_ADDRESS EntryPoint; -} EFI_HOB_MEMORY_ALLOCATION_MODULE; - -#define EFI_HOB_TYPE_RESOURCE_DESCRIPTOR 0x0003 - -typedef UINT32 EFI_RESOURCE_TYPE; - -#define EFI_RESOURCE_SYSTEM_MEMORY 0 -#define EFI_RESOURCE_MEMORY_MAPPED_IO 1 -#define EFI_RESOURCE_IO 2 -#define EFI_RESOURCE_FIRMWARE_DEVICE 3 -#define EFI_RESOURCE_MEMORY_MAPPED_IO_PORT 4 -#define EFI_RESOURCE_MEMORY_RESERVED 5 -#define EFI_RESOURCE_IO_RESERVED 6 -#define EFI_RESOURCE_MAX_MEMORY_TYPE 7 - -typedef UINT32 EFI_RESOURCE_ATTRIBUTE_TYPE; - -#define EFI_RESOURCE_ATTRIBUTE_PRESENT 0x00000001 -#define EFI_RESOURCE_ATTRIBUTE_INITIALIZED 0x00000002 -#define EFI_RESOURCE_ATTRIBUTE_TESTED 0x00000004 -#define EFI_RESOURCE_ATTRIBUTE_SINGLE_BIT_ECC 0x00000008 -#define EFI_RESOURCE_ATTRIBUTE_MULTIPLE_BIT_ECC 0x00000010 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_1 0x00000020 -#define EFI_RESOURCE_ATTRIBUTE_ECC_RESERVED_2 0x00000040 -#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED 0x00000080 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED 0x00000100 -#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED 0x00000200 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE 0x00000400 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE 0x00000800 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE 0x00001000 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE 0x00002000 -#define EFI_RESOURCE_ATTRIBUTE_16_BIT_IO 0x00004000 -#define EFI_RESOURCE_ATTRIBUTE_32_BIT_IO 0x00008000 -#define EFI_RESOURCE_ATTRIBUTE_64_BIT_IO 0x00010000 -#define EFI_RESOURCE_ATTRIBUTE_UNCACHED_EXPORTED 0x00020000 -// -// The following values are defined in PI 1.2 errata B. -// -#define EFI_RESOURCE_ATTRIBUTE_READ_PROTECTABLE 0x00100000 -#define EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTABLE 0x00200000 -#define EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTABLE 0x00400000 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_GUID Owner; - EFI_RESOURCE_TYPE ResourceType; - EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute; - EFI_PHYSICAL_ADDRESS PhysicalStart; - UINT64 ResourceLength; -} EFI_HOB_RESOURCE_DESCRIPTOR; - -// -// GUID Extension HOB -// The HobLength is variable as it includes the GUID specific data. -// -#define EFI_HOB_TYPE_GUID_EXTENSION 0x0004 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_GUID Name; - - // - // Guid specific data goes here - // -} EFI_HOB_GUID_TYPE; - -// -// Firmware Volume HOB -// -#define EFI_HOB_TYPE_FV 0x0005 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 Length; -} EFI_HOB_FIRMWARE_VOLUME; - -// -// CPU HOB -// -#define EFI_HOB_TYPE_CPU 0x0006 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - UINT8 SizeOfMemorySpace; - UINT8 SizeOfIoSpace; - UINT8 Reserved[6]; -} EFI_HOB_CPU; - -// -// PEI Core Memory Pool HOB -// The HobLength is variable as the HOB contains pool allocations by -// the PeiServices AllocatePool function -// -#define EFI_HOB_TYPE_PEI_MEMORY_POOL 0x0007 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; -} EFI_HOB_MEMORY_POOL; - -// -// Capsule volume HOB -- identical to a firmware volume -// -#define EFI_HOB_TYPE_CV 0x0008 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 Length; -} EFI_HOB_CAPSULE_VOLUME; - -#if (PI_SPECIFICATION_VERSION >= 0x00010000) - -#define EFI_HOB_TYPE_FV2 0x0009 - -typedef struct { - EFI_HOB_GENERIC_HEADER Header; - EFI_PHYSICAL_ADDRESS BaseAddress; - UINT64 Length; - EFI_GUID FvName; - EFI_GUID FileName; -} EFI_HOB_FIRMWARE_VOLUME2; - -#define EFI_HOB_TYPE_LOAD_PEIM_UNUSED 0x000A - -#endif - -#define EFI_HOB_TYPE_UNUSED 0xFFFE - -// -// Union of all the possible HOB Types -// -typedef union { - EFI_HOB_GENERIC_HEADER *Header; - EFI_HOB_HANDOFF_INFO_TABLE *HandoffInformationTable; - EFI_HOB_MEMORY_ALLOCATION *MemoryAllocation; - EFI_HOB_MEMORY_ALLOCATION_BSP_STORE *MemoryAllocationBspStore; - EFI_HOB_MEMORY_ALLOCATION_STACK *MemoryAllocationStack; - EFI_HOB_MEMORY_ALLOCATION_MODULE *MemoryAllocationModule; - EFI_HOB_RESOURCE_DESCRIPTOR *ResourceDescriptor; - EFI_HOB_GUID_TYPE *Guid; - EFI_HOB_FIRMWARE_VOLUME *FirmwareVolume; -#if (PI_SPECIFICATION_VERSION >= 0x00010000) - EFI_HOB_FIRMWARE_VOLUME2 *FirmwareVolume2; -#endif - EFI_HOB_CPU *Cpu; - EFI_HOB_MEMORY_POOL *Pool; - EFI_HOB_CAPSULE_VOLUME *CapsuleVolume; - UINT8 *Raw; -} EFI_PEI_HOB_POINTERS; - -#define GET_HOB_TYPE(Hob) ((Hob).Header->HobType) -#define GET_HOB_LENGTH(Hob) ((Hob).Header->HobLength) -#define GET_NEXT_HOB(Hob) ((Hob).Raw + GET_HOB_LENGTH (Hob)) -#define END_OF_HOB_LIST(Hob) (GET_HOB_TYPE (Hob) == EFI_HOB_TYPE_END_OF_HOB_LIST) - -#endif diff --git a/payloads/tianocoreboot/include/PiFirmwareFile.h b/payloads/tianocoreboot/include/PiFirmwareFile.h deleted file mode 100644 index 750ba70..0000000 --- a/payloads/tianocoreboot/include/PiFirmwareFile.h +++ /dev/null @@ -1,494 +0,0 @@ -/** @file - The firmware file related definitions in PI. - -Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved. -This program and the accompanying materials are licensed and made available under -the terms and conditions of the BSD License that accompanies this distribution. -The full text of the license may be found at -http://opensource.org/licenses/bsd-license.php. - -THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, -WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. - - @par Revision Reference: - PI Version 1.2. - -**/ - - -#ifndef __PI_FIRMWARE_FILE_H__ -#define __PI_FIRMWARE_FILE_H__ - -#pragma pack(1) -/// -/// Used to verify the integrity of the file. -/// -typedef union { - struct { - /// - /// The IntegrityCheck.Checksum.Header field is an 8-bit checksum of the file - /// header. The State and IntegrityCheck.Checksum.File fields are assumed - /// to be zero and the checksum is calculated such that the entire header sums to zero. - /// - UINT8 Header; - /// - /// If the FFS_ATTRIB_CHECKSUM (see definition below) bit of the Attributes - /// field is set to one, the IntegrityCheck.Checksum.File field is an 8-bit - /// checksum of the file data. - /// If the FFS_ATTRIB_CHECKSUM bit of the Attributes field is cleared to zero, - /// the IntegrityCheck.Checksum.File field must be initialized with a value of - /// 0xAA. The IntegrityCheck.Checksum.File field is valid any time the - /// EFI_FILE_DATA_VALID bit is set in the State field. - /// - UINT8 File; - } Checksum; - /// - /// This is the full 16 bits of the IntegrityCheck field. - /// - UINT16 Checksum16; -} EFI_FFS_INTEGRITY_CHECK; - -/// -/// FFS_FIXED_CHECKSUM is the checksum value used when the -/// FFS_ATTRIB_CHECKSUM attribute bit is clear. -/// -#define FFS_FIXED_CHECKSUM 0xAA - -typedef UINT8 EFI_FV_FILETYPE; -typedef UINT8 EFI_FFS_FILE_ATTRIBUTES; -typedef UINT8 EFI_FFS_FILE_STATE; - -/// -/// File Types Definitions -/// -#define EFI_FV_FILETYPE_ALL 0x00 -#define EFI_FV_FILETYPE_RAW 0x01 -#define EFI_FV_FILETYPE_FREEFORM 0x02 -#define EFI_FV_FILETYPE_SECURITY_CORE 0x03 -#define EFI_FV_FILETYPE_PEI_CORE 0x04 -#define EFI_FV_FILETYPE_DXE_CORE 0x05 -#define EFI_FV_FILETYPE_PEIM 0x06 -#define EFI_FV_FILETYPE_DRIVER 0x07 -#define EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER 0x08 -#define EFI_FV_FILETYPE_APPLICATION 0x09 -#define EFI_FV_FILETYPE_SMM 0x0A -#define EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE 0x0B -#define EFI_FV_FILETYPE_COMBINED_SMM_DXE 0x0C -#define EFI_FV_FILETYPE_SMM_CORE 0x0D -#define EFI_FV_FILETYPE_OEM_MIN 0xc0 -#define EFI_FV_FILETYPE_OEM_MAX 0xdf -#define EFI_FV_FILETYPE_DEBUG_MIN 0xe0 -#define EFI_FV_FILETYPE_DEBUG_MAX 0xef -#define EFI_FV_FILETYPE_FFS_MIN 0xf0 -#define EFI_FV_FILETYPE_FFS_MAX 0xff -#define EFI_FV_FILETYPE_FFS_PAD 0xf0 -/// -/// FFS File Attributes. -/// -#define FFS_ATTRIB_LARGE_FILE 0x01 -#define FFS_ATTRIB_FIXED 0x04 -#define FFS_ATTRIB_DATA_ALIGNMENT 0x38 -#define FFS_ATTRIB_CHECKSUM 0x40 - -/// -/// FFS File State Bits. -/// -#define EFI_FILE_HEADER_CONSTRUCTION 0x01 -#define EFI_FILE_HEADER_VALID 0x02 -#define EFI_FILE_DATA_VALID 0x04 -#define EFI_FILE_MARKED_FOR_UPDATE 0x08 -#define EFI_FILE_DELETED 0x10 -#define EFI_FILE_HEADER_INVALID 0x20 - - -/// -/// Each file begins with the header that describe the -/// contents and state of the files. -/// -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. - /// - EFI_GUID Name; - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - /// - /// The length of the file in bytes, including the FFS header. - /// - UINT8 Size[3]; - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; -} EFI_FFS_FILE_HEADER; - -typedef struct { - /// - /// This GUID is the file name. It is used to uniquely identify the file. There may be only - /// one instance of a file with the file name GUID of Name in any given firmware - /// volume, except if the file type is EFI_FV_FILETYPE_FFS_PAD. - /// - EFI_GUID Name; - - /// - /// Used to verify the integrity of the file. - /// - EFI_FFS_INTEGRITY_CHECK IntegrityCheck; - - /// - /// Identifies the type of file. - /// - EFI_FV_FILETYPE Type; - - /// - /// Declares various file attribute bits. - /// - EFI_FFS_FILE_ATTRIBUTES Attributes; - - /// - /// The length of the file in bytes, including the FFS header. - /// The length of the file data is either (Size - sizeof(EFI_FFS_FILE_HEADER)). This calculation means a - /// zero-length file has a Size of 24 bytes, which is sizeof(EFI_FFS_FILE_HEADER). - /// Size is not required to be a multiple of 8 bytes. Given a file F, the next file header is - /// located at the next 8-byte aligned firmware volume offset following the last byte of the file F. - /// - UINT8 Size[3]; - - /// - /// Used to track the state of the file throughout the life of the file from creation to deletion. - /// - EFI_FFS_FILE_STATE State; - - /// - /// If FFS_ATTRIB_LARGE_FILE is set in Attributes, then ExtendedSize exists and Size must be set to zero. - /// If FFS_ATTRIB_LARGE_FILE is not set then EFI_FFS_FILE_HEADER is used. - /// - UINT32 ExtendedSize; -} EFI_FFS_FILE_HEADER2; - -#define IS_FFS_FILE2(FfsFileHeaderPtr) \ - (((((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Attributes) & FFS_ATTRIB_LARGE_FILE) == FFS_ATTRIB_LARGE_FILE) - -#define FFS_FILE_SIZE(FfsFileHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_FFS_FILE_HEADER *) (UINTN) FfsFileHeaderPtr)->Size) & 0x00ffffff)) - -#define FFS_FILE2_SIZE(FfsFileHeaderPtr) \ - (((EFI_FFS_FILE_HEADER2 *) (UINTN) FfsFileHeaderPtr)->ExtendedSize) - -typedef UINT8 EFI_SECTION_TYPE; - -/// -/// Pseudo type. It is used as a wild card when retrieving sections. -/// The section type EFI_SECTION_ALL matches all section types. -/// -#define EFI_SECTION_ALL 0x00 - -/// -/// Encapsulation section Type values. -/// -#define EFI_SECTION_COMPRESSION 0x01 - -#define EFI_SECTION_GUID_DEFINED 0x02 - -#define EFI_SECTION_DISPOSABLE 0x03 - -/// -/// Leaf section Type values. -/// -#define EFI_SECTION_PE32 0x10 -#define EFI_SECTION_PIC 0x11 -#define EFI_SECTION_TE 0x12 -#define EFI_SECTION_DXE_DEPEX 0x13 -#define EFI_SECTION_VERSION 0x14 -#define EFI_SECTION_USER_INTERFACE 0x15 -#define EFI_SECTION_COMPATIBILITY16 0x16 -#define EFI_SECTION_FIRMWARE_VOLUME_IMAGE 0x17 -#define EFI_SECTION_FREEFORM_SUBTYPE_GUID 0x18 -#define EFI_SECTION_RAW 0x19 -#define EFI_SECTION_PEI_DEPEX 0x1B -#define EFI_SECTION_SMM_DEPEX 0x1C - -/// -/// Common section header. -/// -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - EFI_SECTION_TYPE Type; - /// - /// Declares the section type. - /// -} EFI_COMMON_SECTION_HEADER; - -typedef struct { - /// - /// A 24-bit unsigned integer that contains the total size of the section in bytes, - /// including the EFI_COMMON_SECTION_HEADER. - /// - UINT8 Size[3]; - - EFI_SECTION_TYPE Type; - - /// - /// If Size is 0xFFFFFF, then ExtendedSize contains the size of the section. If - /// Size is not equal to 0xFFFFFF, then this field does not exist. - /// - UINT32 ExtendedSize; -} EFI_COMMON_SECTION_HEADER2; - -/// -/// Leaf section type that contains an -/// IA-32 16-bit executable image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_COMPATIBILITY16_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_COMPATIBILITY16_SECTION2; - -/// -/// CompressionType of EFI_COMPRESSION_SECTION. -/// -#define EFI_NOT_COMPRESSED 0x00 -#define EFI_STANDARD_COMPRESSION 0x01 -/// -/// An encapsulation section type in which the -/// section data is compressed. -/// -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION; - -typedef struct { - /// - /// Usual common section header. CommonHeader.Type = EFI_SECTION_COMPRESSION. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// UINT32 that indicates the size of the section data after decompression. - /// - UINT32 UncompressedLength; - /// - /// Indicates which compression algorithm is used. - /// - UINT8 CompressionType; -} EFI_COMPRESSION_SECTION2; - -/// -/// An encapsulation section type in which the section data is disposable. -/// A disposable section is an encapsulation section in which the section data may be disposed of during -/// the process of creating or updating a firmware image without significant impact on the usefulness of -/// the file. The Type field in the section header is set to EFI_SECTION_DISPOSABLE. This -/// allows optional or descriptive data to be included with the firmware file which can be removed in -/// order to conserve space. The contents of this section are implementation specific, but might contain -/// debug data or detailed integration instructions. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DISPOSABLE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DISPOSABLE_SECTION2; - -/// -/// The leaf section which could be used to determine the dispatch order of DXEs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_DXE_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_DXE_DEPEX_SECTION2; - -/// -/// The leaf section which contains a PI FV. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_FIRMWARE_VOLUME_IMAGE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_FIRMWARE_VOLUME_IMAGE_SECTION2; - -/// -/// The leaf section which contains a single GUID. -/// -typedef struct { - /// - /// Common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_FREEFORM_SUBTYPE_GUID. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// This GUID is defined by the creator of the file. It is a vendor-defined file type. - /// - EFI_GUID SubTypeGuid; -} EFI_FREEFORM_SUBTYPE_GUID_SECTION2; - -/// -/// Attributes of EFI_GUID_DEFINED_SECTION. -/// -#define EFI_GUIDED_SECTION_PROCESSING_REQUIRED 0x01 -#define EFI_GUIDED_SECTION_AUTH_STATUS_VALID 0x02 -/// -/// The leaf section which is encapsulation defined by specific GUID. -/// -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION; - -typedef struct { - /// - /// The common section header. CommonHeader.Type = EFI_SECTION_GUID_DEFINED. - /// - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// The GUID that defines the format of the data that follows. It is a vendor-defined section type. - /// - EFI_GUID SectionDefinitionGuid; - /// - /// Contains the offset in bytes from the beginning of the common header to the first byte of the data. - /// - UINT16 DataOffset; - /// - /// The bit field that declares some specific characteristics of the section contents. - /// - UINT16 Attributes; -} EFI_GUID_DEFINED_SECTION2; - -/// -/// The leaf section which contains PE32+ image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PE32_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PE32_SECTION2; - -/// -/// The leaf section used to determine the dispatch order of PEIMs. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PEI_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PEI_DEPEX_SECTION2; - -/// -/// A leaf section type that contains a position-independent-code (PIC) image. -/// A PIC image section is a leaf section that contains a position-independent-code (PIC) image. -/// In addition to normal PE32+ images that contain relocation information, PEIM executables may be -/// PIC and are referred to as PIC images. A PIC image is the same as a PE32+ image except that all -/// relocation information has been stripped from the image and the image can be moved and will -/// execute correctly without performing any relocation or other fix-ups. EFI_PIC_SECTION2 must -/// be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_PIC_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_PIC_SECTION2; - -/// -/// The leaf section which constains the position-independent-code image. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_TE_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_TE_SECTION2; - -/// -/// The leaf section which contains an array of zero or more bytes. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_RAW_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_RAW_SECTION2; - -/// -/// The SMM dependency expression section is a leaf section that contains a dependency expression that -/// is used to determine the dispatch order for SMM drivers. Before the SMRAM invocation of the -/// SMM driver's entry point, this dependency expression must evaluate to TRUE. See the Platform -/// Initialization Specification, Volume 2, for details regarding the format of the dependency expression. -/// The dependency expression may refer to protocols installed in either the UEFI or the SMM protocol -/// database. EFI_SMM_DEPEX_SECTION2 must be used if the section is 16MB or larger. -/// -typedef EFI_COMMON_SECTION_HEADER EFI_SMM_DEPEX_SECTION; -typedef EFI_COMMON_SECTION_HEADER2 EFI_SMM_DEPEX_SECTION2; - -/// -/// The leaf section which contains a unicode string that -/// is human readable file name. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - - /// - /// Array of unicode string. - /// - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - CHAR16 FileNameString[1]; -} EFI_USER_INTERFACE_SECTION2; - -/// -/// The leaf section which contains a numeric build number and -/// an optional unicode string that represents the file revision. -/// -typedef struct { - EFI_COMMON_SECTION_HEADER CommonHeader; - UINT16 BuildNumber; - - /// - /// Array of unicode string. - /// - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION; - -typedef struct { - EFI_COMMON_SECTION_HEADER2 CommonHeader; - /// - /// A UINT16 that represents a particular build. Subsequent builds have monotonically - /// increasing build numbers relative to earlier builds. - /// - UINT16 BuildNumber; - CHAR16 VersionString[1]; -} EFI_VERSION_SECTION2; - -#define IS_SECTION2(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff) == 0x00ffffff) - -#define SECTION_SIZE(SectionHeaderPtr) \ - ((UINT32) (*((UINT32 *) ((EFI_COMMON_SECTION_HEADER *) (UINTN) SectionHeaderPtr)->Size) & 0x00ffffff)) - -#define SECTION2_SIZE(SectionHeaderPtr) \ - (((EFI_COMMON_SECTION_HEADER2 *) (UINTN) SectionHeaderPtr)->ExtendedSize) - -#pragma pack() - -#endif - diff --git a/payloads/tianocoreboot/include/coff.h b/payloads/tianocoreboot/include/coff.h deleted file mode 100644 index b6569a1..0000000 --- a/payloads/tianocoreboot/include/coff.h +++ /dev/null @@ -1,106 +0,0 @@ -/* - * This file is part of the TianoCoreBoot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -typedef struct { - uint8_t signature[2]; - uint16_t lastsize; - uint16_t nblocks; - uint16_t nreloc; - uint16_t hdrsize; - uint16_t minalloc; - uint16_t maxalloc; - uint16_t ss; - uint16_t sp; - uint16_t checksum; - uint16_t ip; - uint16_t cs; - uint16_t relocpos; - uint16_t noverlay; - uint16_t reserved1[4]; - uint16_t oem_id; - uint16_t oem_info; - uint16_t reserved2[10]; - uint32_t e_lfanew; -} dos_header_t; - -typedef struct { - uint8_t signature[4]; - uint16_t Machine; - uint16_t NumberOfSections; - uint32_t TimeDateStamp; - uint32_t PointerToSymbolTable; - uint32_t NumberOfSymbols; - uint16_t SizeOfOptionalHeader; - uint16_t Characteristics; -} coff_header_t; - -typedef struct { - uint32_t VirtualAddress; - uint32_t Size; -} data_directory; - -typedef struct { - uint16_t signature; - uint8_t MajorLinkerVersion; - uint8_t MinorLinkerVersion; - uint32_t SizeOfCode; - uint32_t SizeOfInitializedData; - uint32_t SizeOfUninitializedData; - uint32_t AddressOfEntryPoint; - uint32_t BaseOfCode; - uint32_t BaseOfData; - uint32_t ImageBase; - uint32_t SectionAlignment; - uint32_t FileAlignment; - uint16_t MajorOSVersion; - uint16_t MinorOSVersion; - uint16_t MajorImageVersion; - uint16_t MinorImageVersion; - uint16_t MajorSubsystemVersion; - uint16_t MinorSubsystemVersion; - uint32_t Reserved; - uint32_t SizeOfImage; - uint32_t SizeOfHeaders; - uint32_t Checksum; - uint16_t Subsystem; - uint16_t DLLCharacteristics; - uint32_t SizeOfStackReserve; - uint32_t SizeOfStackCommit; - uint32_t SizeOfHeapReserve; - uint32_t SizeOfHeapCommit; - uint32_t LoaderFlags; - uint32_t NumberOfRvaAndSizes; - data_directory DataDirectory[16]; -} pe_opt_header_t; - -typedef struct { - uint8_t SectionName[8]; - uint32_t Size; - uint32_t RVA; - uint32_t PhysicalSizeOnDisk; - uint32_t PhysicalLocationOnDisk; - uint8_t Reserved[12]; - uint32_t SectionFlags; -} pe_section_t; - -typedef struct { - uint32_t VirtualAddress; - uint32_t SizeOfBlock; -} relocation_t; - diff --git a/payloads/tianocoreboot/include/efi.h b/payloads/tianocoreboot/include/efi.h deleted file mode 100644 index 8deef53..0000000 --- a/payloads/tianocoreboot/include/efi.h +++ /dev/null @@ -1,36 +0,0 @@ -/* - * This file is part of the TianoCoreBoot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> - -#define ALIGN(x,a) __ALIGN_MASK(x,(typeof(x))(a)-1UL) -#define __ALIGN_MASK(x,mask) (((x)+(mask))&~(mask)) - -typedef long intn_t; -typedef unsigned long uintn_t; - -#include <EfiTypes.h> -#include <EfiFirmwareVolumeHeader.h> -#include <PiFirmwareFile.h> -#include <PeiHob.h> -#include <MemoryAllocationHob.h> - -#define EFI_DXE_FILE_GUID \ - { 0xb1644c1a, 0xc16a, 0x4c5b, { 0x88, 0xde, 0xea, 0xfb, 0xa9, 0x7e, 0x74, 0xd8 } } - diff --git a/payloads/tianocoreboot/libpayload.config b/payloads/tianocoreboot/libpayload.config deleted file mode 100644 index e63fee8..0000000 --- a/payloads/tianocoreboot/libpayload.config +++ /dev/null @@ -1,58 +0,0 @@ -# -# Automatically generated make config: don't edit -# libpayload version: 0.2.0 -# Thu Jan 17 12:32:59 2013 -# - -# -# Generic Options -# -# CONFIG_EXPERIMENTAL is not set -# CONFIG_OBSOLETE is not set -# CONFIG_DEVELOPER is not set -# CONFIG_CHROMEOS is not set - -# -# Architecture Options -# -# CONFIG_ARCH_ARM is not set -# CONFIG_ARCH_POWERPC is not set -CONFIG_ARCH_X86=y -# CONFIG_MEMMAP_RAM_ONLY is not set -# CONFIG_MULTIBOOT is not set - -# -# Standard Libraries -# -CONFIG_LIBC=y -# CONFIG_CURSES is not set -CONFIG_CBFS=y -CONFIG_LZMA=y - -# -# Console Options -# -# CONFIG_SKIP_CONSOLE_INIT is not set -CONFIG_CBMEM_CONSOLE=y -CONFIG_SERIAL_CONSOLE=y -CONFIG_SERIAL_IOBASE=0x3f8 -# CONFIG_SERIAL_SET_SPEED is not set -# CONFIG_SERIAL_ACS_FALLBACK is not set -CONFIG_VIDEO_CONSOLE=y -CONFIG_VGA_VIDEO_CONSOLE=y -# CONFIG_GEODELX_VIDEO_CONSOLE is not set -CONFIG_COREBOOT_VIDEO_CONSOLE=y -# CONFIG_PC_KEYBOARD is not set - -# -# Drivers -# -# CONFIG_PCI is not set -# CONFIG_NVRAM is not set -# CONFIG_RTC_PORT_EXTENDED_VIA is not set -# CONFIG_SPEAKER is not set -# CONFIG_STORAGE is not set -# CONFIG_USB is not set -# CONFIG_BIG_ENDIAN is not set -CONFIG_LITTLE_ENDIAN=y -CONFIG_ARCH_SPECIFIC_OPTIONS=y diff --git a/payloads/tianocoreboot/tianocoreboot.c b/payloads/tianocoreboot/tianocoreboot.c deleted file mode 100644 index bbdcfaf..0000000 --- a/payloads/tianocoreboot/tianocoreboot.c +++ /dev/null @@ -1,529 +0,0 @@ -/* - * This file is part of the TianoCoreBoot project. - * - * Copyright (C) 2013 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <libpayload.h> -#include <endian.h> -#include <cbfs.h> -#include <efi.h> -#include <coff.h> - -#define DXE_CORE_SIZE (256*1024) -#define UEFI_STACK_SIZE (128*1024) -#define HOB_LIST_SIZE (16*1024) - -#undef VERBOSE -#undef INVENTORY - -static void print_guid(EFI_GUID *guid) -{ - printf("%08x-%04x-%04x-%02x%02x-%02x%02x%02x%02x%02x%02x", - guid->Data1, guid->Data2, guid->Data3, - guid->Data4[0], guid->Data4[1], guid->Data4[2], guid->Data4[3], - guid->Data4[4], guid->Data4[5], guid->Data4[6], guid->Data4[7]); -} - -static void dump_uefi_firmware_volume_header(EFI_FIRMWARE_VOLUME_HEADER *fvh) -{ - printf("Found UEFI firmware volume.\n"); - printf(" GUID: "); - print_guid(&(fvh->FileSystemGuid)); - printf("\n"); - printf(" length: 0x%016llx\n", fvh->FvLength); -#ifdef VERBOSE - printf(" signature: 0x%08x\n", fvh->Signature); - printf(" attributes: 0x%08x\n", fvh->Attributes); - printf(" header length: 0x%04x\n", fvh->HeaderLength); - printf(" checksum: 0x%04x\n", fvh->Checksum); - printf(" revision: 0x%02x\n", fvh->Revision); - printf(" block map:\n"); - int i = 0; - EFI_FV_BLOCK_MAP_ENTRY *fbm = &(fvh->FvBlockMap[0]); - while (fbm[i].NumBlocks || fbm[i].BlockLength) { - printf(" %2d. numblocks = 0x%08x length = 0x%08x\n", - i+1, fbm[i].NumBlocks, fbm[i].BlockLength); - i++; - } -#endif - printf("\n"); -} - -#ifdef INVENTORY -static void dump_uefi_ffs_file_header(EFI_FFS_FILE_HEADER *file) -{ - int size; - -#ifdef VERBOSE - printf("Found FFS file:\n GUID: "); -#endif - print_guid(&(file->Name)); -#ifdef VERBOSE - printf("\n integrity check: %02x %02x\n", - file->IntegrityCheck.Checksum.Header, - file->IntegrityCheck.Checksum.File); - printf(" file type: "); -#else - printf(" "); -#endif - switch (file->Type) { - case EFI_FV_FILETYPE_RAW: printf("raw"); break; - case EFI_FV_FILETYPE_FREEFORM: printf("free form"); break; - case EFI_FV_FILETYPE_SECURITY_CORE: printf("security core"); break; - case EFI_FV_FILETYPE_PEI_CORE: printf("PEIM core"); break; - case EFI_FV_FILETYPE_DXE_CORE: printf("DXE core"); break; - case EFI_FV_FILETYPE_PEIM: printf("PEIM"); break; - case EFI_FV_FILETYPE_DRIVER: printf("driver"); break; - case EFI_FV_FILETYPE_COMBINED_PEIM_DRIVER: printf("combined PEIM driver"); break; - case EFI_FV_FILETYPE_APPLICATION: printf("application"); break; - case EFI_FV_FILETYPE_FIRMWARE_VOLUME_IMAGE: printf("firmware volume image"); break; - case EFI_FV_FILETYPE_FFS_PAD: printf("FFS pad"); break; - default: printf("unknown"); - } -#ifdef VERBOSE - printf("\n"); - printf(" attributes: 0x%02x\n", file->Attributes); -#endif - size = file->Size[0] | (file->Size[1] << 8) | (file->Size[2] << 16); -#ifdef VERBOSE - printf(" size: 0x%06x\n", size); - printf(" state: 0x%02x\n", file->State); -#else - printf(" (%d bytes)\n", size); -#endif -} -#endif - -void *load_dxe_core(void *pe, void *target) -{ - dos_header_t *dos_hdr = (dos_header_t *)pe; - -#if VERBOSE - printf("Loading DXE core at %p\n", pe); -#endif - - if (*(uint16_t *)pe != 0x5a4d) { - printf("DXE core not a PE binary.\n"); - return NULL; - } - -#ifdef VERBOSE - printf("e_lfanew = 0x%08x\n", dos_hdr->e_lfanew); -#endif - - coff_header_t *coff_hdr = (coff_header_t *)(pe + dos_hdr->e_lfanew); -#ifdef VERBOSE - printf("Machine: %x\n", coff_hdr->Machine); - printf("NumberOfSections: %x\n", coff_hdr->NumberOfSections); - printf("TimeDateStamp: %x\n", coff_hdr->TimeDateStamp); - printf("PointerToSymbolTable: %x\n", coff_hdr->PointerToSymbolTable); - printf("NumberOfSymbols: %x\n", coff_hdr->NumberOfSymbols); - printf("SizeOfOptionalHeader: %x\n", coff_hdr->SizeOfOptionalHeader); - printf("Characteristics: %x\n", coff_hdr->Characteristics); -#endif - if (coff_hdr->Machine != 0x14c) { - printf("Only x86 supported right now.\n"); - return NULL; - } - - /* Right after the coff header */ - pe_opt_header_t *pe_hdr = (pe_opt_header_t *)(&coff_hdr[1]); - if (pe_hdr->signature != 267) { - printf("No valid PE opt header\n"); - return NULL; - } - -#ifdef VERBOSE - printf("\n"); - printf("MajorLinkerVersion: %x\n", pe_hdr->MajorLinkerVersion); - printf("MinorLinkerVersion: %x\n", pe_hdr->MinorLinkerVersion); - printf("SizeOfCode: %x\n", pe_hdr->SizeOfCode); - printf("SizeOfInitializedData: %x\n", pe_hdr->SizeOfInitializedData); - printf("SizeOfUninitializedData: %x\n", pe_hdr->SizeOfUninitializedData); - printf("AddressOfEntryPoint: %x\n", pe_hdr->AddressOfEntryPoint); - printf("BaseOfCode: %x\n", pe_hdr->BaseOfCode); - printf("BaseOfData: %x\n", pe_hdr->BaseOfData); - printf("ImageBase: %x\n", pe_hdr->ImageBase); - printf("SectionAlignment: %x\n", pe_hdr->SectionAlignment); - printf("FileAlignment: %x\n", pe_hdr->FileAlignment); - printf("MajorOSVersion: %x\n", pe_hdr->MajorOSVersion); - printf("MinorOSVersion: %x\n", pe_hdr->MinorOSVersion); - printf("MajorImageVersion: %x\n", pe_hdr->MajorImageVersion); - printf("MinorImageVersion: %x\n", pe_hdr->MinorImageVersion); - printf("MajorSubsystemVersion: %x\n", pe_hdr->MajorSubsystemVersion); - printf("MinorSubsystemVersion: %x\n", pe_hdr->MinorSubsystemVersion); - printf("Reserved: %x\n", pe_hdr->Reserved); - printf("SizeOfImage: %x\n", pe_hdr->SizeOfImage); - printf("SizeOfHeaders: %x\n", pe_hdr->SizeOfHeaders); - printf("Checksum: %x\n", pe_hdr->Checksum); - printf("Subsystem: %x\n", pe_hdr->Subsystem); - printf("DLLCharacteristics: %x\n", pe_hdr->DLLCharacteristics); - printf("SizeOfStackReserve: %x\n", pe_hdr->SizeOfStackReserve); - printf("SizeOfStackCommit: %x\n", pe_hdr->SizeOfStackCommit); - printf("SizeOfHeapReserve: %x\n", pe_hdr->SizeOfHeapReserve); - printf("SizeOfHeapCommit: %x\n", pe_hdr->SizeOfHeapCommit); - printf("LoaderFlags: %x\n", pe_hdr->LoaderFlags); - printf("NumberOfRvaAndSizes: %x\n", pe_hdr->NumberOfRvaAndSizes); -#endif - - if(pe_hdr->Subsystem != 0xb) { - printf("Not an EFI binary.\n"); - return NULL; - } - - int i; -#ifdef VERBOSE - for (i = 0; i < pe_hdr->NumberOfRvaAndSizes; i++) { - if (!pe_hdr->DataDirectory[i].Size) - continue; - printf("Data Directory %d\n", i+1); - printf(" VirtualAddress %x\n", pe_hdr->DataDirectory[i].VirtualAddress); - printf(" Size %x\n", pe_hdr->DataDirectory[i].Size); - } -#endif - - pe_section_t *sections = (pe_section_t *)(&pe_hdr[1]); - - int offset = 0; - - for (i = 0; i < coff_hdr->NumberOfSections; i++) { - int j; - printf(" Section %d: ", i); - for (j = 0; j < 8; j++) - printf("%c", sections[i].SectionName[j] ? sections[i].SectionName[j] : ' '); - - printf(" size=%08x rva=%08x in file=%08x/%08x flags=%08x\n", - sections[i].Size, sections[i].RVA, sections[i].PhysicalSizeOnDisk, - sections[i].PhysicalLocationOnDisk, sections[i].SectionFlags); - - if (!strncmp((char *)sections[i].SectionName, ".text", 6)) { - // .text section - // size=157a0 rva=240 size on disk=157a0 location on disk=240 flags=60000020 - memcpy(target, pe + sections[i].PhysicalLocationOnDisk, - sections[i].PhysicalSizeOnDisk); - offset = sections[i].RVA; - } else - if (!strncmp((char *)sections[i].SectionName, ".data", 6)) { - // .data section - // size=6820 rva=159e0 size on disk=6820 location on disk=159e0 flags=c0000040 - memcpy(target + sections[i].RVA - offset, pe + sections[i].PhysicalLocationOnDisk, - sections[i].PhysicalSizeOnDisk); - } else - if (!strncmp((char *)sections[i].SectionName, ".reloc", 7)) { - // .reloc section - // section 2: .reloc - // size=1080 rva=1c200 size on disk=1080 location on disk=1c200 flags=42000040 - relocation_t *reloc = (relocation_t *) - (pe + sections[i].PhysicalLocationOnDisk); - while (reloc && reloc->SizeOfBlock) { -#ifdef VERBOSE - printf("Relocation Block Virtual %08x Size %08x\n", - reloc->VirtualAddress, reloc->SizeOfBlock); -#endif - for (i = sizeof(relocation_t); i < reloc->SizeOfBlock; i+= 2) { - uint16_t r = *(uint16_t *)((void *)reloc + i); - switch (r>>12) { - case 3: -#ifdef VERBOSE - printf(" HIGHLOW %08x\n", - reloc->VirtualAddress + (r & 0xfff)); -#endif - *(uint32_t *)(target - offset + reloc->VirtualAddress + (r & 0xfff)) - += (unsigned long)target - offset; - break; - case 0: -#ifdef VERBOSE - printf(" ABSOLUTE %08x\n", r & 0xfff); -#endif - break; - default: - printf("Unknown relocation type %x\n", r); - return NULL; - } - } - - reloc = (relocation_t *)(((void *)reloc) + reloc->SizeOfBlock); - } - } else - if (!strncmp((char *)sections[i].SectionName, ".debug", 7)) { - // debug section, silently ignored. - } else { - printf("section type "); - for (j = 0; j < 8; j++) - if (sections[i].SectionName[j]) - printf("%c", sections[i].SectionName[j]); - printf(" unknown. ignored.\n"); - } - } - - return (target + pe_hdr->AddressOfEntryPoint - offset); -} - -void start_dxe_core(void *entry, void *stack, void *hoblist) -{ - printf("\nJumping to DXE core at %p\n", entry); - asm volatile( - "movl %1, %%esp\n" - "pushl %2\n" - "call *%0\n" - : : "r"(entry), "r"(stack), "r"(hoblist) : "esp" - ); -} - -static const EFI_HOB_HANDOFF_INFO_TABLE HandoffInformationTable = { - { EFI_HOB_TYPE_HANDOFF, sizeof(EFI_HOB_HANDOFF_INFO_TABLE), 0 }, - EFI_HOB_HANDOFF_TABLE_VERSION, - BOOT_WITH_FULL_CONFIGURATION, - 0 /* EfiMemoryTop */, - 0 /* EfiMemoryBottom */, - 0 /* EfiFreeMemoryTop */, - 0 /* EfiFreeMemoryBottom */, - 0 /* EfiEndOfHobList */ -}; - -static const EFI_HOB_FIRMWARE_VOLUME FirmwareVolume = { - { EFI_HOB_TYPE_FV, sizeof(EFI_HOB_FIRMWARE_VOLUME), 0 }, - 0 /* BaseAddress */, - 0 /* Length */ -}; - -/* 1..n */ -static const EFI_HOB_RESOURCE_DESCRIPTOR ResourceDescriptor = { - { EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, sizeof(EFI_HOB_RESOURCE_DESCRIPTOR), 0 }, - { 0 }, // owner EFI_GUID - EFI_RESOURCE_SYSTEM_MEMORY, - EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | - EFI_RESOURCE_ATTRIBUTE_TESTED, - 0, /* PhysicalStart */ - 0 /* ResourceLength */ -}; - -static const EFI_HOB_MEMORY_ALLOCATION_MODULE MemoryAllocationModule = { - { EFI_HOB_TYPE_MEMORY_ALLOCATION, sizeof(EFI_HOB_MEMORY_ALLOCATION_MODULE), 0 }, - { EFI_HOB_MEMORY_ALLOC_MODULE_GUID, 0 /* MemoryBaseAddress */, 0 /* MemoryLength */, EfiBootServicesCode, {0,0,0,0} }, - EFI_DXE_FILE_GUID, - 0x0 // ADDR EntryPoint -}; - -static const EFI_HOB_CPU Cpu = { - { EFI_HOB_TYPE_CPU, sizeof(EFI_HOB_CPU), 0 }, - 32, /* SizeOfMemorySpace, u8 */ - 16, /* SizeOfIoSpace */ - { 0,0,0,0,0,0 } -}; - -static const EFI_HOB_GENERIC_HEADER End = - { EFI_HOB_TYPE_END_OF_HOB_LIST, sizeof(EFI_HOB_GENERIC_HEADER), 0 }; - - -static void prepare_handoff_blocks(void *hoblist, EFI_FIRMWARE_VOLUME_HEADER *fvh, - unsigned long EfiMemoryTop, unsigned long EfiMemoryBottom, - unsigned long EfiFreeMemoryTop, unsigned long EfiFreeMemoryBottom, - unsigned long dxecore_base) -{ - void *ptr = hoblist; - int i; - - EFI_HOB_HANDOFF_INFO_TABLE *hit = (EFI_HOB_HANDOFF_INFO_TABLE *)ptr; - memcpy(ptr, &HandoffInformationTable, sizeof(HandoffInformationTable)); - ptr += sizeof(HandoffInformationTable); - - EFI_HOB_FIRMWARE_VOLUME *fv = (EFI_HOB_FIRMWARE_VOLUME *)ptr; - memcpy(ptr, &FirmwareVolume, sizeof(FirmwareVolume)); - ptr += sizeof(FirmwareVolume); - - for (i = 0; i < lib_sysinfo.n_memranges; i++) { - EFI_HOB_RESOURCE_DESCRIPTOR *resource; - if (lib_sysinfo.memrange[i].type != CB_MEM_RAM) - continue; - resource = (EFI_HOB_RESOURCE_DESCRIPTOR *)ptr; - memcpy(ptr, &ResourceDescriptor, sizeof(ResourceDescriptor)); - ptr += sizeof(ResourceDescriptor); - resource->PhysicalStart = lib_sysinfo.memrange[i].base; - resource->ResourceLength = lib_sysinfo.memrange[i].size; - } - - EFI_HOB_MEMORY_ALLOCATION_MODULE *allocation = (EFI_HOB_MEMORY_ALLOCATION_MODULE *)ptr; - memcpy(ptr, &MemoryAllocationModule, sizeof(MemoryAllocationModule)); - ptr += sizeof(MemoryAllocationModule); - - memcpy(ptr, &Cpu, sizeof(Cpu)); - ptr += sizeof(Cpu); - - memcpy(ptr, &End, sizeof(End)); - ptr += sizeof(Cpu); - - /* Handoff Information Table HOB */ - hit->EfiMemoryTop = EfiMemoryTop; - hit->EfiMemoryBottom = EfiMemoryBottom; - hit->EfiFreeMemoryTop = EfiFreeMemoryTop; - hit->EfiFreeMemoryBottom = EfiFreeMemoryBottom; - hit->EfiEndOfHobList = (unsigned long)ptr; - - /* Firmware Volume HOB */ - fv->BaseAddress = (unsigned long)fvh; - fv->Length = fvh->FvLength; - - allocation->MemoryAllocationHeader.MemoryBaseAddress = dxecore_base; - allocation->MemoryAllocationHeader.MemoryLength = DXE_CORE_SIZE; -} - -int main(void) -{ - int i; - struct cbfs_file *file; - void *tiano; - unsigned long long ram_seg_base = 0, ram_seg_size = 0; - EFI_FIRMWARE_VOLUME_HEADER *fvh = NULL; - EFI_PEI_HOB_POINTERS hoblist; - EFI_COMMON_SECTION_HEADER *dxecore = NULL; - - printf("\nTiano Core Loader v1.0\n"); - printf("Copyright (C) 2013 Google Inc. All rights reserved.\n\n"); - - printf("Memory Map (%d entries):\n", lib_sysinfo.n_memranges); - for (i = 0; i < lib_sysinfo.n_memranges; i++) { - printf(" %d. %016llx - %016llx [%02x]\n", i + 1, - lib_sysinfo.memrange[i].base, - lib_sysinfo.memrange[i].base + - lib_sysinfo.memrange[i].size - 1, - lib_sysinfo.memrange[i].type); - - /* Look for the last chunk of memory below 4G */ - if (lib_sysinfo.memrange[i].type == CB_MEM_RAM && - lib_sysinfo.memrange[i].base < 0xffffffff) { - ram_seg_base = lib_sysinfo.memrange[i].base; - ram_seg_size = lib_sysinfo.memrange[i].size; - } - } - printf("\n"); - - if (!ram_seg_base || ram_seg_size < (1024*1024)) { - printf("No usable RAM found.\n"); - halt(); - } - - /* Find the end of our memory block, align to 4K */ - unsigned long memory = (ram_seg_base + ram_seg_size) & 0xfffff000; - - /* 256K for DXE core. It's 116K on my system but you never know. */ - memory -= DXE_CORE_SIZE; - unsigned long dxecore_base = memory; - memory -= UEFI_STACK_SIZE; - unsigned long uefi_stack = memory; - - memory -= 1024*1024; // FIXME this should go away - unsigned long free_memory = memory; // FIXME this should go away - - memory -= HOB_LIST_SIZE; - unsigned long hoblist_base = memory; - - printf("DXE code: %08lx\n", dxecore_base); - printf("DXE stack: %08lx\n", uefi_stack); - printf("HOB list: %08lx\n\n", hoblist_base); - - /* Find UEFI firmware volume in CBFS */ - file = cbfs_find("fallback/tianocore.fd"); - if (!file) { - printf("Could not find fallback/tianocore.fd in CBFS.\n"); - halt(); - } - - tiano = CBFS_SUBHEADER(file); - while (tiano < (void *)CBFS_SUBHEADER(file) + ntohl(file->len)) { - /* Verify UEFI firmware volume consistency */ - fvh = (EFI_FIRMWARE_VOLUME_HEADER *)tiano; - if (fvh->Signature != 0x4856465f) { - printf("Not an UEFI firmware volume.\n"); - halt(); - } - - /* Dump UEFI firmware volume header */ - dump_uefi_firmware_volume_header(fvh); - - /* Dump UEFI firmware file headers */ - for (i = fvh->HeaderLength; i < fvh->FvLength;) { - int size; - EFI_FFS_FILE_HEADER *ffs; - - ffs = (EFI_FFS_FILE_HEADER *)(tiano + i); - - size = ffs->Size[0] | (ffs->Size[1] << 8) | (ffs->Size[2] << 16); - if (size == 0xffffff) - break; -#ifdef INVENTORY - printf("%08x - ", i); - dump_uefi_ffs_file_header(ffs); -#endif - - if (ffs->Type == EFI_FV_FILETYPE_DXE_CORE) { - dxecore = (EFI_COMMON_SECTION_HEADER *)&ffs[1]; -#ifndef INVENTORY - break; -#endif - } - - i = ALIGN(i + size, 8); - } - - tiano += fvh->FvLength; -#ifdef INVENTORY - printf("\n"); -#endif - } - - /* Prepare Hand Off Blocks */ - prepare_handoff_blocks((void *)hoblist_base, fvh, - // FIXME memory top, memory bottom - (ram_seg_base + ram_seg_size) & 0xfffff000, ram_seg_base, - // FIXME free memory top, free memory bottom - uefi_stack, free_memory, - dxecore_base); - hoblist.Raw = (void *)hoblist_base; - - if (!dxecore) { - printf("No DXE core found.\n"); - halt(); - } - - printf("Found DXE core at %p\n", &dxecore[1]); -#ifdef VERBOSE - int size = dxecore->Size[0] | (dxecore->Size[1] << 8) | (dxecore->Size[2] << 16); - printf(" size = %d, type = %x\n", size, dxecore->Type); -#endif - - void *pe = (void *)&dxecore[1]; - - void *entry; - entry = load_dxe_core(pe, (void *)dxecore_base); - - if (!entry) { - printf("Could not load DXE code.\n"); - halt(); - } - - start_dxe_core(entry, (void *)(uefi_stack + UEFI_STACK_SIZE - 4), hoblist.Raw); - - printf("The end.\n"); - halt(); - - return 0; -} - -PAYLOAD_INFO(name, "TianoCoreBoot"); -PAYLOAD_INFO(listname, "Tiano Core"); -PAYLOAD_INFO(desc, "Tiano Core Loader");

1 0

New patch to review for coreboot: 7c1f2a3 nvramtool: make sure that strings are 0-terminated
by Patrick Georgi 01 Dec '14

01 Dec '14

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7621 -gerrit commit 7c1f2a325cda74e0c09bca5c5dec1c64fe526afe Author: Patrick Georgi <pgeorgi(a)google.com> Date: Mon Dec 1 22:09:33 2014 +0100 nvramtool: make sure that strings are 0-terminated The call site expects them to be. Change-Id: Ic05fc5831f5743d94fe617dfb3b9e329f01866d1 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- util/nvramtool/cmos_lowlevel.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/nvramtool/cmos_lowlevel.c b/util/nvramtool/cmos_lowlevel.c index 618e8d2..87d0acc 100644 --- a/util/nvramtool/cmos_lowlevel.c +++ b/util/nvramtool/cmos_lowlevel.c @@ -125,7 +125,7 @@ unsigned long long cmos_read(const cmos_entry_t * e) result = 0; if (e->config == CMOS_ENTRY_STRING) { - int strsz = (length + 7) / 8; + int strsz = (length + 7) / 8 + 1; char *newstring = alloca(strsz); unsigned usize = (8 * sizeof(unsigned long long));

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2014