coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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1346 discussions

New patch to review for coreboot: e41ab71 nvramtool: cmos_read(): Use malloc() instead of alloca()
by Andrew Engelbrecht 01 Dec '14

01 Dec '14

Andrew Engelbrecht (sudoman(a)ninthfloor.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7620 -gerrit commit e41ab71f527ffc4627b5ea059e2913b0e97159f9 Author: Andrew Engelbrecht <sudoman(a)ninthfloor.org> Date: Mon Dec 1 12:22:48 2014 -0500 nvramtool: cmos_read(): Use malloc() instead of alloca() Fixes crash occurring when 'nvramtool -a' tried to free a prematurely freed pointer. (Tested on x60) malloc() is correct because the pointer is accessed outside the calling function. The pointer is freed in the parent function list_cmos_entry(). Change-Id: I1723f09740657f0f0d9e6954bd6d11c0a3820a42 Signed-off-by: Andrew Engelbrecht <sudoman(a)ninthfloor.org> --- util/nvramtool/cmos_lowlevel.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/util/nvramtool/cmos_lowlevel.c b/util/nvramtool/cmos_lowlevel.c index 618e8d2..c46e480 100644 --- a/util/nvramtool/cmos_lowlevel.c +++ b/util/nvramtool/cmos_lowlevel.c @@ -112,6 +112,9 @@ static inline void put_bits(unsigned char value, unsigned bit, * Read value from nonvolatile RAM at position given by 'bit' and 'length' * and return this value. The I/O privilege level of the currently executing * process must be set appropriately. + * + * Returned value is either (unsigned long long), or malloc()'d (char *) + * cast to (unsigned long long) ****************************************************************************/ unsigned long long cmos_read(const cmos_entry_t * e) { @@ -126,7 +129,7 @@ unsigned long long cmos_read(const cmos_entry_t * e) if (e->config == CMOS_ENTRY_STRING) { int strsz = (length + 7) / 8; - char *newstring = alloca(strsz); + char *newstring = malloc(strsz); unsigned usize = (8 * sizeof(unsigned long long)); if (!newstring) {

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New patch to review for coreboot: 1991f39 UCB RISCV: Switch to DYNAMIC_CBMEM
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7619 -gerrit commit 1991f399f8a5ca617f58fd7f3cf30709a7137631 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Dec 1 20:35:43 2014 +0200 UCB RISCV: Switch to DYNAMIC_CBMEM Change-Id: Iaaf68fd19f7b9a5b6849fffde3a9c68cb7862367 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/riscv/tables.c | 20 -------------------- src/soc/ucb/riscv/Kconfig | 1 + 2 files changed, 1 insertion(+), 20 deletions(-) diff --git a/src/arch/riscv/tables.c b/src/arch/riscv/tables.c index 0265949..6300f7b 100644 --- a/src/arch/riscv/tables.c +++ b/src/arch/riscv/tables.c @@ -29,15 +29,6 @@ #define MAX_COREBOOT_TABLE_SIZE (8 * 1024) -#if ! IS_ENABLED(CONFIG_DYNAMIC_CBMEM) -/* - * TODO: "High" tables are a convention used on x86. Maybe we can - * clean up that naming at some point. - */ -uint64_t high_tables_base = 0; -uint64_t high_tables_size; -#endif - void cbmem_arch_init(void) { } @@ -47,14 +38,6 @@ static struct lb_memory *wtf_write_tables(void) { unsigned long table_pointer, new_table_pointer; -#if ! IS_ENABLED(CONFIG_DYNAMIC_CBMEM) - if (!high_tables_base) { - printk(BIOS_ERR, "ERROR: high_tables_base is not set.\n"); - } - - printk(BIOS_DEBUG, "high_tables_base: %llx.\n", high_tables_base); -#endif - post_code(0x9d); table_pointer = (unsigned long)cbmem_add(CBMEM_ID_CBTABLE, @@ -91,6 +74,3 @@ void write_tables(void) void cbmem_fail_resume(void) { } -void get_cbmem_table(uint64_t *base, uint64_t *size) -{ -} diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig index d1e4ba7..be4a675 100644 --- a/src/soc/ucb/riscv/Kconfig +++ b/src/soc/ucb/riscv/Kconfig @@ -3,6 +3,7 @@ config SOC_UCB_RISCV select ARCH_BOOTBLOCK_RISCV select ARCH_ROMSTAGE_RISCV select ARCH_RAMSTAGE_RISCV + select DYNAMIC_CBMEM bool default n

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Patch merged into coreboot/master: e0e784a Add UCB RISCV support for architecture, soc, and emulation mainboard..
by gerrit＠coreboot.org 01 Dec '14

01 Dec '14

the following patch was just integrated into master: commit e0e784a456c4d64e5e88ce578371fe6c538db559 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Nov 26 19:25:47 2014 +0000 Add UCB RISCV support for architecture, soc, and emulation mainboard.. Works in the RISCV version of QEMU. Note that the lzmadecode is so unclean that it needs a lot of work. A cleanup is in progress. We decided in Prague to do this as one thing, because it forms a nice case study of the bare minimum you need to add to get a new architecture going in qemu. Change-Id: If5af15c3a70733d219973e0d032746f8ab027e4d Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: http://review.coreboot.org/7584 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7584 for details. -gerrit

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Patch set updated for coreboot: 00045c7 AGESA: Remove duplicate OemCustomizeInitEarly declarations
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7158 -gerrit commit 00045c7a237c609550986a2bb493788ead54136b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 13:43:46 2014 +0300 AGESA: Remove duplicate OemCustomizeInitEarly declarations Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/inagua/PlatformGnbPcie.c | 1 + src/mainboard/amd/inagua/PlatformGnbPcieComplex.h | 2 -- src/mainboard/amd/olivehill/PlatformGnbPcie.c | 3 +- .../amd/olivehill/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/amd/parmer/PlatformGnbPcie.c | 3 +- src/mainboard/amd/parmer/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/amd/persimmon/PlatformGnbPcie.c | 1 + .../amd/persimmon/PlatformGnbPcieComplex.h | 4 --- src/mainboard/amd/south_station/PlatformGnbPcie.c | 1 + .../amd/south_station/PlatformGnbPcieComplex.h | 4 --- src/mainboard/amd/thatcher/PlatformGnbPcie.c | 3 +- .../amd/thatcher/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/amd/torpedo/PlatformGnbPcie.c | 1 + src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 4 --- src/mainboard/amd/union_station/PlatformGnbPcie.c | 1 + .../amd/union_station/PlatformGnbPcieComplex.h | 4 --- src/mainboard/asrock/e350m1/PlatformGnbPcie.c | 1 + .../asrock/e350m1/PlatformGnbPcieComplex.h | 4 --- src/mainboard/asrock/imb-a180/PlatformGnbPcie.c | 3 +- .../asrock/imb-a180/PlatformGnbPcieComplex.h | 32 ---------------------- src/mainboard/asus/f2a85-m/PlatformGnbPcie.c | 5 +++- .../asus/f2a85-m/PlatformGnbPcieComplex.h | 31 --------------------- src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c | 1 + .../gizmosphere/gizmo/PlatformGnbPcieComplex.h | 4 --- .../hp/pavilion_m6_1035dx/PlatformGnbPcie.c | 5 +++- .../hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h | 31 --------------------- .../jetway/nf81-t56n-lf/PlatformGnbPcie.c | 1 + .../jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h | 2 -- src/mainboard/lenovo/g505s/PlatformGnbPcie.c | 5 +++- .../lenovo/g505s/PlatformGnbPcieComplex.h | 31 --------------------- .../lippert/frontrunner-af/PlatformGnbPcie.c | 1 + .../frontrunner-af/PlatformGnbPcieComplex.h | 4 --- src/mainboard/lippert/toucan-af/PlatformGnbPcie.c | 1 + .../lippert/toucan-af/PlatformGnbPcieComplex.h | 4 --- src/northbridge/amd/agesa/agesawrapper.h | 3 ++ src/northbridge/amd/agesa/family12/agesawrapper.c | 2 -- src/northbridge/amd/agesa/family14/agesawrapper.c | 2 -- src/northbridge/amd/agesa/family15/agesawrapper.c | 4 +-- .../amd/agesa/family15rl/agesawrapper.c | 2 -- .../amd/agesa/family15tn/agesawrapper.c | 2 -- .../amd/agesa/family16kb/agesawrapper.c | 2 -- 41 files changed, 35 insertions(+), 276 deletions(-) diff --git a/src/mainboard/amd/inagua/PlatformGnbPcie.c b/src/mainboard/amd/inagua/PlatformGnbPcie.c index 08cd998..4e8e15f 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcie.c +++ b/src/mainboard/amd/inagua/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h index 111ad6f..0b93d9c 100644 --- a/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/inagua/PlatformGnbPcieComplex.h @@ -64,6 +64,4 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS *InitEarly); - #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcie.c b/src/mainboard/amd/olivehill/PlatformGnbPcie.c index 0775ad3..903d1bb 100644 --- a/src/mainboard/amd/olivehill/PlatformGnbPcie.c +++ b/src/mainboard/amd/olivehill/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h b/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h deleted file mode 100644 index b3c69cf..0000000 --- a/src/mainboard/amd/olivehill/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/parmer/PlatformGnbPcie.c b/src/mainboard/amd/parmer/PlatformGnbPcie.c index 784f6d9..50f8be5 100644 --- a/src/mainboard/amd/parmer/PlatformGnbPcie.c +++ b/src/mainboard/amd/parmer/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* diff --git a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h b/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h deleted file mode 100644 index b3c69cf..0000000 --- a/src/mainboard/amd/parmer/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcie.c b/src/mainboard/amd/persimmon/PlatformGnbPcie.c index de797c0..0ecc4f1 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcie.c +++ b/src/mainboard/amd/persimmon/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h index ec8a6e3..4a01875 100644 --- a/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/persimmon/PlatformGnbPcieComplex.h @@ -65,9 +65,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/south_station/PlatformGnbPcie.c b/src/mainboard/amd/south_station/PlatformGnbPcie.c index 3798251..884d813 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/south_station/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/south_station/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcie.c b/src/mainboard/amd/thatcher/PlatformGnbPcie.c index 4072112..58cc105 100644 --- a/src/mainboard/amd/thatcher/PlatformGnbPcie.c +++ b/src/mainboard/amd/thatcher/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE /* diff --git a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h b/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h deleted file mode 100644 index b3c69cf..0000000 --- a/src/mainboard/amd/thatcher/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcie.c b/src/mainboard/amd/torpedo/PlatformGnbPcie.c index a17a7ed..f8ad709 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcie.c +++ b/src/mainboard/amd/torpedo/PlatformGnbPcie.c @@ -20,6 +20,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f12/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X12_F12PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/amd/union_station/PlatformGnbPcie.c b/src/mainboard/amd/union_station/PlatformGnbPcie.c index aa0eedb..12ded1e 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcie.c +++ b/src/mainboard/amd/union_station/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h +++ b/src/mainboard/amd/union_station/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c index eefd27f..9f6af52 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcie.c +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h index 5efcd7d..8660e0a 100644 --- a/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h +++ b/src/mainboard/asrock/e350m1/PlatformGnbPcieComplex.h @@ -64,9 +64,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c index 24d8381..75fb0c2 100644 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c +++ b/src/mainboard/asrock/imb-a180/PlatformGnbPcie.c @@ -21,9 +21,10 @@ #include "amdlib.h" #include "Ids.h" #include "heapManager.h" -#include "PlatformGnbPcieComplex.h" #include "Filecode.h" +#include <northbridge/amd/agesa/agesawrapper.h> + #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE static const PCIe_PORT_DESCRIPTOR PortList [] = { diff --git a/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h b/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h deleted file mode 100644 index 1db8b2d..0000000 --- a/src/mainboard/asrock/imb-a180/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include "Porting.h" -#include "AGESA.h" -#include "amdlib.h" - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c index 3a8be41..91b5028 100644 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c +++ b/src/mainboard/asus/f2a85-m/PlatformGnbPcie.c @@ -17,8 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "PlatformGnbPcieComplex.h" +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h b/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h deleted file mode 100644 index add9008..0000000 --- a/src/mainboard/asus/f2a85-m/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> -#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c index cc4bbfb..00bd809 100755 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcie.c @@ -26,6 +26,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> /*---------------------------------------------------------------------------------------*/ /** diff --git a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h index 5cd4b41..88dc25b 100755 --- a/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h +++ b/src/mainboard/gizmosphere/gizmo/PlatformGnbPcieComplex.h @@ -66,9 +66,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c index de046ac..378b48f 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcie.c @@ -17,8 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "PlatformGnbPcieComplex.h" +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h b/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h deleted file mode 100644 index add9008..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> -#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c index ad4934e..cdeca0b 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcie.c @@ -21,6 +21,7 @@ #include "PlatformGnbPcieComplex.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h index dd6f7d7..0d1738e 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h +++ b/src/mainboard/jetway/nf81-t56n-lf/PlatformGnbPcieComplex.h @@ -79,6 +79,4 @@ #define GNB_GPP_PORT8_CHANNEL_TYPE 4 #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 -void OemCustomizeInitEarly (IN OUT AMD_EARLY_PARAMS *InitEarly); - #endif /* _PLATFORM_GNB_PCIE_COMPLEX_H */ diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c index de046ac..378b48f 100644 --- a/src/mainboard/lenovo/g505s/PlatformGnbPcie.c +++ b/src/mainboard/lenovo/g505s/PlatformGnbPcie.c @@ -17,8 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "PlatformGnbPcieComplex.h" +#include "Porting.h" +#include "AGESA.h" +#include "amdlib.h" +#include <northbridge/amd/agesa/agesawrapper.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h b/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h deleted file mode 100644 index add9008..0000000 --- a/src/mainboard/lenovo/g505s/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -#include <vendorcode/amd/agesa/f15tn/AGESA.h> -#include <vendorcode/amd/agesa/f15tn/Lib/amdlib.h> - -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c index c06296f..331e27d 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h index 02c7f4e..0b57605 100644 --- a/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/frontrunner-af/PlatformGnbPcieComplex.h @@ -65,9 +65,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c index f8ba912..5677aa8 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcie.c @@ -25,6 +25,7 @@ #include "Filecode.h" #include <string.h> +#include <northbridge/amd/agesa/agesawrapper.h> #define FILECODE PROC_RECOVERY_MEM_NB_ON_MRNON_FILECODE diff --git a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h index 69e2615..301938c 100644 --- a/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h +++ b/src/mainboard/lippert/toucan-af/PlatformGnbPcieComplex.h @@ -65,9 +65,5 @@ //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) #define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced -VOID -OemCustomizeInitEarly ( - IN OUT AMD_EARLY_PARAMS *InitEarly - ); #endif //_PLATFORM_GNB_PCIE_COMPLEX_H diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index b94ddf7..49f6666 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -65,4 +65,7 @@ void *agesawrapper_getlateinitptr (int pick); AGESA_STATUS agesawrapper_fchs3earlyrestore(void); AGESA_STATUS agesawrapper_fchs3laterestore(void); +void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly); +void OemCustomizeInitPost(AMD_POST_PARAMS *InitPost); + #endif /* _AGESAWRAPPER_H_ */ diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 8a5f03f..7309262 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -47,8 +47,6 @@ VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - UINT32 ReadAmdSbPmr(IN UINT8 IndexValue, OUT UINT8 * DataValue); UINT32 WriteAmdSbPmr(IN UINT8 IndexValue, IN UINT8 DataValue); diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index ee6caaf..1f580ef 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -46,8 +46,6 @@ VOID *AcpiWheaMce = NULL; VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(VOID) { UINT64 MsrReg; diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 74f9cb9..5c99551 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -47,11 +47,11 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; /* TODO: Function body should be in mainboard directory. */ -static VOID OemCustomizeInitEarly(AMD_EARLY_PARAMS * InitEarly) +void OemCustomizeInitEarly(AMD_EARLY_PARAMS *InitEarly) { } -static VOID OemCustomizeInitPost(AMD_POST_PARAMS *InitPost) +void OemCustomizeInitPost(AMD_POST_PARAMS *InitPost) { #if IS_ENABLED(CONFIG_BOARD_AMD_DINAR) InitPost->MemConfig.UmaMode = UMA_AUTO; diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 66a351c..2099a49 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; VOID *AcpiIvrs = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(void) { UINT64 MsrReg; diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 66a351c..2099a49 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; VOID *AcpiIvrs = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(void) { UINT64 MsrReg; diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 66a351c..2099a49 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -52,8 +52,6 @@ VOID *AcpiWheaCmc = NULL; VOID *AcpiAlib = NULL; VOID *AcpiIvrs = NULL; -VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); - AGESA_STATUS agesawrapper_amdinitcpuio(void) { UINT64 MsrReg;

1 0

Patch set updated for coreboot: 3c3e5ab AGESA fam15tn / fam15rl / fam16kb: Common agesawrapper
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7159 -gerrit commit 3c3e5abdd7f013bb1e50fc1f9825bc3a652e6a83 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 20 08:49:16 2014 +0300 AGESA fam15tn / fam15rl / fam16kb: Common agesawrapper Split FCH parts to southbridge/hudson. Change-Id: Ibe305fc3e47422523a57ffa9cf69cd401c786ee2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/Makefile.inc | 2 - src/mainboard/amd/olivehill/agesawrapper.c | 609 -------------------- src/mainboard/amd/parmer/Makefile.inc | 2 - src/mainboard/amd/parmer/agesawrapper.c | 612 -------------------- src/mainboard/amd/thatcher/Makefile.inc | 2 - src/mainboard/amd/thatcher/agesawrapper.c | 616 -------------------- src/mainboard/asrock/imb-a180/Makefile.inc | 2 - src/mainboard/asrock/imb-a180/agesawrapper.c | 638 --------------------- src/mainboard/asus/f2a85-m/Makefile.inc | 2 - src/mainboard/asus/f2a85-m/agesawrapper.c | 636 -------------------- src/mainboard/asus/f2a85-m_le/Makefile.inc | 2 - src/mainboard/asus/f2a85-m_le/agesawrapper.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc | 2 - src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 625 -------------------- src/mainboard/lenovo/g505s/Makefile.inc | 2 - src/mainboard/lenovo/g505s/agesawrapper.c | 625 -------------------- src/northbridge/amd/agesa/family15rl/Makefile.inc | 2 + .../amd/agesa/family15rl/agesawrapper.c | 499 ++++++++++++++++ src/northbridge/amd/agesa/family15tn/Makefile.inc | 2 + .../amd/agesa/family15tn/agesawrapper.c | 499 ++++++++++++++++ src/northbridge/amd/agesa/family16kb/Makefile.inc | 2 + .../amd/agesa/family16kb/agesawrapper.c | 499 ++++++++++++++++ src/southbridge/amd/agesa/hudson/Makefile.inc | 2 + src/southbridge/amd/agesa/hudson/agesawrapper.c | 92 +++ 24 files changed, 1597 insertions(+), 4378 deletions(-) diff --git a/src/mainboard/amd/olivehill/Makefile.inc b/src/mainboard/amd/olivehill/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/amd/olivehill/Makefile.inc +++ b/src/mainboard/amd/olivehill/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c deleted file mode 100644 index 242aa27..0000000 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/amd/parmer/Makefile.inc b/src/mainboard/amd/parmer/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/amd/parmer/Makefile.inc +++ b/src/mainboard/amd/parmer/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c deleted file mode 100644 index b4b39d0..0000000 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ /dev/null @@ -1,612 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/amd/thatcher/Makefile.inc b/src/mainboard/amd/thatcher/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/amd/thatcher/Makefile.inc +++ b/src/mainboard/amd/thatcher/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c deleted file mode 100644 index 7425eac..0000000 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ /dev/null @@ -1,616 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; -#if 1 /* TODO: Get the param from Nv storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); -#endif - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO:Get params from Volatile storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); -#endif - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#if 1 /* TODO: Save the params to NvStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#endif - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO: Save the params to VolatileStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage - ); -#endif - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/asrock/imb-a180/Makefile.inc b/src/mainboard/asrock/imb-a180/Makefile.inc index a83297a..0e63e9b 100644 --- a/src/mainboard/asrock/imb-a180/Makefile.inc +++ b/src/mainboard/asrock/imb-a180/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c deleted file mode 100644 index 1412392..0000000 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ /dev/null @@ -1,638 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <stdint.h> -#include <string.h> -#include <cpu/x86/mtrr.h> -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "cpuRegisters.h" -#include "cpuCacheInit.h" -#include "cpuApicUtilities.h" -#include "cpuEarlyInit.h" -#include "cpuLateInit.h" -#include "Dispatcher.h" -#include "cpuCacheInit.h" -#include "amdlib.h" -#include "PlatformGnbPcieComplex.h" -#include "Filecode.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "Fch.h" -#include <cpu/amd/agesa/s3_resume.h> -#include <arch/io.h> -#include <device/device.h> -#include "hudson.h" - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/asus/f2a85-m/Makefile.inc b/src/mainboard/asus/f2a85-m/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/asus/f2a85-m/Makefile.inc +++ b/src/mainboard/asus/f2a85-m/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asus/f2a85-m/agesawrapper.c b/src/mainboard/asus/f2a85-m/agesawrapper.c deleted file mode 100644 index 2a5f5c8..0000000 --- a/src/mainboard/asus/f2a85-m/agesawrapper.c +++ /dev/null @@ -1,636 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "PlatformGnbPcieComplex.h" - -#include <arch/io.h> -#include <cpu/amd/agesa/s3_resume.h> -#include <cpu/x86/mtrr.h> -#include <device/device.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <stdint.h> -#include <string.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -AGESA_STATUS agesawrapper_amdinitcpuio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ - PciData |= 1 << 7; /* set NP (non-posted) bit */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; -#if 1 /* TODO: Get the param from Nv storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); -#endif - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO:Get params from Volatile storage. */ - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); -#endif - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#if 1 /* TODO: Save the params to NvStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); -#endif - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - -#if 1 /* TODO: Save the params to VolatileStorage */ - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage - ); -#endif - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/asus/f2a85-m_le/Makefile.inc b/src/mainboard/asus/f2a85-m_le/Makefile.inc index 3103f70..ab1febc 100644 --- a/src/mainboard/asus/f2a85-m_le/Makefile.inc +++ b/src/mainboard/asus/f2a85-m_le/Makefile.inc @@ -18,11 +18,9 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c diff --git a/src/mainboard/asus/f2a85-m_le/agesawrapper.c b/src/mainboard/asus/f2a85-m_le/agesawrapper.c deleted file mode 100644 index d38e91c..0000000 --- a/src/mainboard/asus/f2a85-m_le/agesawrapper.c +++ /dev/null @@ -1 +0,0 @@ -#include "../f2a85-m/agesawrapper.c" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc index 7039c72..fae7fcc 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc +++ b/src/mainboard/hp/pavilion_m6_1035dx/Makefile.inc @@ -18,12 +18,10 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c ramstage-y += ec.c diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c deleted file mode 100644 index 1ceffa0..0000000 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "PlatformGnbPcieComplex.h" - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <device/device.h> -#include <string.h> -#include <stdint.h> - -#include <cpu/amd/agesa/s3_resume.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -uint32_t agesawrapper_amdinitcpuio(void) -{ - pci_devfn_t dev; - msr_t msr; - uint32_t reg32; - - dev = PCI_DEV(0, 0x18, 1); - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - pci_io_write_config32(dev, 0xf4, 1); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - * Last address before processor local APIC at FEE00000 - */ - pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7)); - - - /* Lowest NP address is HPET at FED00000 */ - pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3); - - /* Map the remaining PCI hole as posted MMIO */ - pci_io_write_config32(dev, 0x8C, 0x00fecf00); - - msr = rdmsr(0xc001001a); - reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */ - pci_io_write_config32(dev, 0x88, reg32); - - /* Send all IO (0000-FFFF) to southbridge. */ - pci_io_write_config32(dev, 0xc4, 0x0000f000); - pci_io_write_config32(dev, 0xc0, 0x00000003); - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/mainboard/lenovo/g505s/Makefile.inc b/src/mainboard/lenovo/g505s/Makefile.inc index 7039c72..fae7fcc 100644 --- a/src/mainboard/lenovo/g505s/Makefile.inc +++ b/src/mainboard/lenovo/g505s/Makefile.inc @@ -18,12 +18,10 @@ # romstage-y += buildOpts.c -romstage-y += agesawrapper.c romstage-y += BiosCallOuts.c romstage-y += PlatformGnbPcie.c ramstage-y += buildOpts.c -ramstage-y += agesawrapper.c ramstage-y += BiosCallOuts.c ramstage-y += PlatformGnbPcie.c ramstage-y += ec.c diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c deleted file mode 100644 index 1ceffa0..0000000 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ /dev/null @@ -1,625 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -/*---------------------------------------------------------------------------------------- - * M O D U L E S U S E D - *---------------------------------------------------------------------------------------- - */ - -#include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/BiosCallOuts.h> -#include "PlatformGnbPcieComplex.h" - -#define __SIMPLE_DEVICE__ - -#include <arch/io.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <device/device.h> -#include <string.h> -#include <stdint.h> - -#include <cpu/amd/agesa/s3_resume.h> -#include <southbridge/amd/agesa/hudson/hudson.h> -#include <vendorcode/amd/agesa/f15tn/Proc/Fch/FchPlatform.h> -#include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> - - -#define FILECODE UNASSIGNED_FILE_FILECODE - -/*---------------------------------------------------------------------------------------- - * D E F I N I T I O N S A N D M A C R O S - *---------------------------------------------------------------------------------------- - */ - -/* ACPI table pointers returned by AmdInitLate */ -VOID *DmiTable = NULL; -VOID *AcpiPstate = NULL; -VOID *AcpiSrat = NULL; -VOID *AcpiSlit = NULL; - -VOID *AcpiWheaMce = NULL; -VOID *AcpiWheaCmc = NULL; -VOID *AcpiAlib = NULL; -VOID *AcpiIvrs = NULL; - -/*---------------------------------------------------------------------------------------- - * T Y P E D E F S A N D S T R U C T U R E S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * P R O T O T Y P E S O F L O C A L F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*---------------------------------------------------------------------------------------- - * E X P O R T E D F U N C T I O N S - *---------------------------------------------------------------------------------------- - */ - -/*--------------------------------------------------------------------------------------- - * L O C A L F U N C T I O N S - *--------------------------------------------------------------------------------------- - */ -uint32_t agesawrapper_amdinitcpuio(void) -{ - pci_devfn_t dev; - msr_t msr; - uint32_t reg32; - - dev = PCI_DEV(0, 0x18, 1); - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - pci_io_write_config32(dev, 0xf4, 1); - - /* The platform BIOS needs to ensure the memory ranges of Hudson legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - * Last address before processor local APIC at FEE00000 - */ - pci_io_write_config32(dev, 0x84, 0x00fedf00 | (1 << 7)); - - - /* Lowest NP address is HPET at FED00000 */ - pci_io_write_config32(dev, 0x80, (0xfed00000 >> 8) | 3); - - /* Map the remaining PCI hole as posted MMIO */ - pci_io_write_config32(dev, 0x8C, 0x00fecf00); - - msr = rdmsr(0xc001001a); - reg32 = (msr.hi << 24) | (msr.lo >> 8) | 3; /* Equivalent to msr >> 8 */ - pci_io_write_config32(dev, 0x88, reg32); - - /* Send all IO (0000-FFFF) to southbridge. */ - pci_io_write_config32(dev, 0xc4, 0x0000f000); - pci_io_write_config32(dev, 0xc0, 0x00000003); - - return AGESA_SUCCESS; -} - -AGESA_STATUS agesawrapper_amdinitmmio(void) -{ - AGESA_STATUS Status; - UINT64 MsrReg; - AMD_CONFIG_PARAMS StdHeader; - - /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. - */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); - - /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. - */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); - MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - - /* Set ROM cache onto WP to decrease post time */ - MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); - - Status = AGESA_SUCCESS; - return Status; -} - -AGESA_STATUS agesawrapper_amdinitreset(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - LibAmdMemFill (&AmdResetParams, - 0, - sizeof (AMD_RESET_PARAMS), - &(AmdResetParams.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset ((AMD_RESET_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - return status; -} - -AGESA_STATUS agesawrapper_amdinitearly(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr; - OemCustomizeInitEarly (AmdEarlyParamsPtr); - - status = AmdInitEarly ((AMD_EARLY_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitpost(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - PostParams = (AMD_POST_PARAMS *)AmdParamStruct.NewStructPtr; - status = AmdInitPost (PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - /* Initialize heap space */ - EmptyHeap(); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitenv(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - status = AmdCreateStruct (&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *)AmdParamStruct.NewStructPtr; - - status = AmdInitEnv (EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); - /* Initialize Subordinate Bus Number and Secondary Bus Number - * In platform BIOS this address is allocated by PCI enumeration code - Modify D1F0x18 - */ - - return status; -} - -VOID * -agesawrapper_getlateinitptr ( - int pick - ) -{ - switch (pick) { - case PICK_DMI: - return DmiTable; - case PICK_PSTATE: - return AcpiPstate; - case PICK_SRAT: - return AcpiSrat; - case PICK_SLIT: - return AcpiSlit; - case PICK_WHEA_MCE: - return AcpiWheaMce; - case PICK_WHEA_CMC: - return AcpiWheaCmc; - case PICK_ALIB: - return AcpiAlib; - case PICK_IVRS: - return AcpiIvrs; - default: - return NULL; - } -} - -AGESA_STATUS agesawrapper_amdinitmid(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio (); - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct (&AmdParamStruct); - - ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0;/* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - status = AmdInitMid ((AMD_MID_PARAMS *)AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amdinitlate(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_LATE_PARAMS *AmdLateParams; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *)AmdParamStruct.NewStructPtr; - Status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(Status, AmdLateParams->StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - DmiTable = AmdLateParams->DmiTable; - AcpiPstate = AmdLateParams->AcpiPState; - AcpiSrat = AmdLateParams->AcpiSrat; - AcpiSlit = AmdLateParams->AcpiSlit; - - AcpiWheaMce = AmdLateParams->AcpiWheaMce; - AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; - AcpiAlib = AmdLateParams->AcpiAlib; - AcpiIvrs = AmdLateParams->AcpiIvrs; - - printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," - "AcpiSlit:%x, Mce:%x, Cmc:%x," - "Alib:%x, AcpiIvrs:%x in %s\n", - (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, - (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, - (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); - - /* AmdReleaseStruct (&AmdParamStruct); */ - return Status; -} - -AGESA_STATUS agesawrapper_amdlaterunaptask ( - UINT32 Func, - UINT32 Data, - VOID *ConfigPtr - ) -{ - AGESA_STATUS Status; - AP_EXE_PARAMS ApExeParams; - - LibAmdMemFill (&ApExeParams, - 0, - sizeof (AP_EXE_PARAMS), - &(ApExeParams.StdHeader)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; - ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; - ApExeParams.FunctionNumber = Func; - ApExeParams.RelatedDataBlock = ConfigPtr; - - Status = AmdLateRunApTask (&ApExeParams); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof (AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof (AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -extern UINT8 picr_data[0x54], intr_data[0x54]; - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - UINT8 byte; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - //FchParams = InitEnvCfgDefault; - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} -#endif - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof (AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amdreadeventlog ( - UINT8 HeapStatus - ) -{ - AGESA_STATUS Status; - EVENT_PARAMS AmdEventParams; - - LibAmdMemFill (&AmdEventParams, - 0, - sizeof (EVENT_PARAMS), - &(AmdEventParams.StdHeader)); - - AmdEventParams.StdHeader.AltImageBasePtr = 0; - AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; - AmdEventParams.StdHeader.Func = 0; - AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog (&AmdEventParams); - while (AmdEventParams.EventClass != 0) { - printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass,(unsigned int)AmdEventParams.EventInfo); - printk(BIOS_DEBUG," Param1 = %x, Param2 = %x.\n",(unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); - printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n",(unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog (&AmdEventParams); - } - - return Status; -} diff --git a/src/northbridge/amd/agesa/family15rl/Makefile.inc b/src/northbridge/amd/agesa/family15rl/Makefile.inc index 5013364..831aab1 100644 --- a/src/northbridge/amd/agesa/family15rl/Makefile.inc +++ b/src/northbridge/amd/agesa/family15rl/Makefile.inc @@ -18,6 +18,8 @@ # romstage-y += dimmSpd.c +romstage-y += agesawrapper.c ramstage-y += iommu.c ramstage-y += northbridge.c +ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c new file mode 100644 index 0000000..66a351c --- /dev/null +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -0,0 +1,499 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32) MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + + status = AmdInitEnv(EnvParam); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +VOID *agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + + ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitLate(AmdLateParams); + AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return status; +} + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct(&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog(&AmdEventParams); + } + + return Status; +} diff --git a/src/northbridge/amd/agesa/family15tn/Makefile.inc b/src/northbridge/amd/agesa/family15tn/Makefile.inc index 5013364..831aab1 100644 --- a/src/northbridge/amd/agesa/family15tn/Makefile.inc +++ b/src/northbridge/amd/agesa/family15tn/Makefile.inc @@ -18,6 +18,8 @@ # romstage-y += dimmSpd.c +romstage-y += agesawrapper.c ramstage-y += iommu.c ramstage-y += northbridge.c +ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c new file mode 100644 index 0000000..66a351c --- /dev/null +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -0,0 +1,499 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32) MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + + status = AmdInitEnv(EnvParam); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +VOID *agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + + ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitLate(AmdLateParams); + AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return status; +} + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct(&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog(&AmdEventParams); + } + + return Status; +} diff --git a/src/northbridge/amd/agesa/family16kb/Makefile.inc b/src/northbridge/amd/agesa/family16kb/Makefile.inc index 4a75499..f821940 100644 --- a/src/northbridge/amd/agesa/family16kb/Makefile.inc +++ b/src/northbridge/amd/agesa/family16kb/Makefile.inc @@ -18,5 +18,7 @@ # romstage-y += dimmSpd.c +romstage-y += agesawrapper.c ramstage-y += northbridge.c +ramstage-y += agesawrapper.c diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c new file mode 100644 index 0000000..66a351c --- /dev/null +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -0,0 +1,499 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +#define FILECODE UNASSIGNED_FILE_FILECODE + +/* ACPI table pointers returned by AmdInitLate */ +VOID *DmiTable = NULL; +VOID *AcpiPstate = NULL; +VOID *AcpiSrat = NULL; +VOID *AcpiSlit = NULL; + +VOID *AcpiWheaMce = NULL; +VOID *AcpiWheaCmc = NULL; +VOID *AcpiAlib = NULL; +VOID *AcpiIvrs = NULL; + +VOID OemCustomizeInitEarly(IN OUT AMD_EARLY_PARAMS * InitEarly); + +AGESA_STATUS agesawrapper_amdinitcpuio(void) +{ + UINT64 MsrReg; + UINT32 PciData; + PCI_ADDR PciAddress; + AMD_CONFIG_PARAMS StdHeader; + + /* Enable legacy video routing: D18F1xF4 VGA Enable */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); + PciData = 1; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* The platform BIOS needs to ensure the memory ranges of Hudson legacy + * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are + * set to non-posted regions. + */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciData |= 1 << 7; /* set NP (non-posted) bit */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Map the remaining PCI hole as posted MMIO */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); + PciData = 0x00FECF00; /* last address before non-posted range */ + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + LibAmdMsrRead(0xC001001A, &MsrReg, &StdHeader); + MsrReg = (MsrReg >> 8) | 3; + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); + PciData = (UINT32) MsrReg; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + /* Send all IO (0000-FFFF) to southbridge. */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); + PciData = 0x0000F000; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); + PciData = 0x00000003; + LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitmmio(void) +{ + UINT64 MsrReg; + AMD_CONFIG_PARAMS StdHeader; + + /* + Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base + Address MSR register. + */ + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse(CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); + + /* + Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + */ + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); + MsrReg = MsrReg | 0x0000400000000000; + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); + + /* Set ROM cache onto WP to decrease post time */ + MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_amdinitreset(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESET_PARAMS AmdResetParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + LibAmdMemFill(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS), &(AmdResetParams.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; + AmdParamStruct.AllocationMethod = ByHost; + AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); + AmdParamStruct.NewStructPtr = &AmdResetParams; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + AmdResetParams.HtConfig.Depth = 0; + + status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + return status; +} + +AGESA_STATUS agesawrapper_amdinitearly(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_EARLY_PARAMS *AmdEarlyParamsPtr; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + OemCustomizeInitEarly(AmdEarlyParamsPtr); + + status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitpost(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_POST_PARAMS *PostParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitPost(PostParams); + AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + /* Initialize heap space */ + EmptyHeap(); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitenv(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_ENV_PARAMS *EnvParam; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + status = AmdCreateStruct(&AmdParamStruct); + EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + + status = AmdInitEnv(EnvParam); + AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + /* Initialize Subordinate Bus Number and Secondary Bus Number + * In platform BIOS this address is allocated by PCI enumeration code + Modify D1F0x18 + */ + + return status; +} + +VOID *agesawrapper_getlateinitptr(int pick) +{ + switch (pick) { + case PICK_DMI: + return DmiTable; + case PICK_PSTATE: + return AcpiPstate; + case PICK_SRAT: + return AcpiSrat; + case PICK_SLIT: + return AcpiSlit; + case PICK_WHEA_MCE: + return AcpiWheaMce; + case PICK_WHEA_CMC: + return AcpiWheaCmc; + case PICK_ALIB: + return AcpiAlib; + case PICK_IVRS: + return AcpiIvrs; + default: + return NULL; + } +} + +AGESA_STATUS agesawrapper_amdinitmid(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + AmdCreateStruct(&AmdParamStruct); + + ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitlate(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_LATE_PARAMS *AmdLateParams; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; + AmdParamStruct.AllocationMethod = PostMemDram; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + + /* NOTE: if not call amdcreatestruct, the initializer(AmdInitLateInitializer) would not be called */ + AmdCreateStruct(&AmdParamStruct); + AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; + status = AmdInitLate(AmdLateParams); + AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + DmiTable = AmdLateParams->DmiTable; + AcpiPstate = AmdLateParams->AcpiPState; + AcpiSrat = AmdLateParams->AcpiSrat; + AcpiSlit = AmdLateParams->AcpiSlit; + + AcpiWheaMce = AmdLateParams->AcpiWheaMce; + AcpiWheaCmc = AmdLateParams->AcpiWheaCmc; + AcpiAlib = AmdLateParams->AcpiAlib; + AcpiIvrs = AmdLateParams->AcpiIvrs; + + printk(BIOS_DEBUG, "DmiTable:%x, AcpiPstatein: %x, AcpiSrat:%x," + "AcpiSlit:%x, Mce:%x, Cmc:%x," + "Alib:%x, AcpiIvrs:%x in %s\n", + (unsigned int)DmiTable, (unsigned int)AcpiPstate, (unsigned int)AcpiSrat, + (unsigned int)AcpiSlit, (unsigned int)AcpiWheaMce, (unsigned int)AcpiWheaCmc, + (unsigned int)AcpiAlib, (unsigned int)AcpiIvrs, __func__); + + /* AmdReleaseStruct (&AmdParamStruct); */ + return status; +} + +AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) +{ + AGESA_STATUS status; + AP_EXE_PARAMS ApExeParams; + + LibAmdMemFill(&ApExeParams, 0, sizeof(AP_EXE_PARAMS), &(ApExeParams.StdHeader)); + + ApExeParams.StdHeader.AltImageBasePtr = 0; + ApExeParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + ApExeParams.StdHeader.Func = 0; + ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; + ApExeParams.RelatedDataBlock = ConfigPtr; + + status = AmdLateRunApTask(&ApExeParams); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS Status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + agesawrapper_amdinitcpuio(); + LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + Status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + return Status; +} + +#ifndef __PRE_RAM__ + +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS Status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + + AmdCreateStruct(&AmdInterfaceParams); + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + Status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(Status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + Status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + OemAgesaSaveMtrr(); + + AmdReleaseStruct(&AmdInterfaceParams); + + return Status; +} + +#endif /* #ifndef __PRE_RAM__ */ + +AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +{ + AGESA_STATUS Status; + EVENT_PARAMS AmdEventParams; + + LibAmdMemFill(&AmdEventParams, 0, sizeof(EVENT_PARAMS), &(AmdEventParams.StdHeader)); + + AmdEventParams.StdHeader.AltImageBasePtr = 0; + AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdEventParams.StdHeader.Func = 0; + AmdEventParams.StdHeader.ImageBasePtr = 0; + AmdEventParams.StdHeader.HeapStatus = HeapStatus; + Status = AmdReadEventLog(&AmdEventParams); + while (AmdEventParams.EventClass != 0) { + printk(BIOS_DEBUG, "\nEventLog: EventClass = %x, EventInfo = %x.\n", + (unsigned int)AmdEventParams.EventClass, (unsigned int)AmdEventParams.EventInfo); + printk(BIOS_DEBUG, " Param1 = %x, Param2 = %x.\n", + (unsigned int)AmdEventParams.DataParam1, (unsigned int)AmdEventParams.DataParam2); + printk(BIOS_DEBUG, " Param3 = %x, Param4 = %x.\n", + (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); + Status = AmdReadEventLog(&AmdEventParams); + } + + return Status; +} diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 98cac93..84f0d3e 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -10,6 +10,8 @@ ramstage-y += pci.c ramstage-y += pcie.c ramstage-y += sd.c +ramstage-y += agesawrapper.c + ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c diff --git a/src/southbridge/amd/agesa/hudson/agesawrapper.c b/src/southbridge/amd/agesa/hudson/agesawrapper.c new file mode 100644 index 0000000..4de59b9 --- /dev/null +++ b/src/southbridge/amd/agesa/hudson/agesawrapper.c @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <string.h> +#include <cpu/x86/mtrr.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "cpuRegisters.h" +#include "cpuCacheInit.h" +#include "cpuApicUtilities.h" +#include "cpuEarlyInit.h" +#include "cpuLateInit.h" +#include "Dispatcher.h" +#include "cpuCacheInit.h" +#include "amdlib.h" +#include "Filecode.h" +#include "heapManager.h" +#include "FchPlatform.h" +#include "Fch.h" +#include <cpu/amd/agesa/s3_resume.h> +#include <arch/io.h> +#include <device/device.h> +#include "hudson.h" + +extern UINT8 picr_data[0x54], intr_data[0x54]; + +AGESA_STATUS agesawrapper_fchs3earlyrestore (void) +{ + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3EarlyRestore(&FchParams); + + return AGESA_SUCCESS; +} + +AGESA_STATUS agesawrapper_fchs3laterestore (void) +{ + FCH_DATA_BLOCK FchParams; + AMD_CONFIG_PARAMS StdHeader; + UINT8 byte; + + StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; + StdHeader.AltImageBasePtr = 0; + StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; + StdHeader.Func = 0; + StdHeader.ImageBasePtr = 0; + + FchParams.StdHeader = &StdHeader; + s3_resume_init_data(&FchParams); + FchInitS3LateRestore(&FchParams); + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + return AGESA_SUCCESS; +}

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Patch set updated for coreboot: b5468fc AGESA: Trace execution with AGESA_EVENTLOG()
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7604 -gerrit commit b5468fc3ae4a5b6d21a4472a54aa95a4d279fca5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 14:19:04 2014 +0300 AGESA: Trace execution with AGESA_EVENTLOG() Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/agesawrapper_s3.c | 6 +- src/cpu/amd/agesa/amd_late_init.c | 5 +- src/mainboard/amd/dinar/romstage.c | 11 ++-- src/mainboard/amd/inagua/romstage.c | 11 ++-- src/mainboard/amd/olivehill/romstage.c | 15 +++-- src/mainboard/amd/parmer/romstage.c | 15 +++-- src/mainboard/amd/persimmon/romstage.c | 15 +++-- src/mainboard/amd/south_station/romstage.c | 11 ++-- src/mainboard/amd/thatcher/romstage.c | 16 ++--- src/mainboard/amd/torpedo/romstage.c | 11 ++-- src/mainboard/amd/union_station/romstage.c | 11 ++-- src/mainboard/asrock/e350m1/romstage.c | 11 ++-- src/mainboard/asrock/imb-a180/romstage.c | 15 +++-- src/mainboard/asus/f2a85-m/romstage.c | 15 +++-- src/mainboard/gizmosphere/gizmo/romstage.c | 15 +++-- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 15 +++-- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 15 +++-- src/mainboard/lenovo/g505s/romstage.c | 15 +++-- src/mainboard/lippert/frontrunner-af/romstage.c | 15 +++-- src/mainboard/lippert/toucan-af/romstage.c | 15 +++-- src/mainboard/supermicro/h8qgi/romstage.c | 11 ++-- src/mainboard/supermicro/h8scm/romstage.c | 11 ++-- src/mainboard/tyan/s8226/romstage.c | 11 ++-- src/northbridge/amd/agesa/agesawrapper.h | 5 +- src/northbridge/amd/agesa/agesawrapper_call.h | 73 ---------------------- src/northbridge/amd/agesa/eventlog.c | 71 +++++++++++++++++---- src/northbridge/amd/agesa/family10/northbridge.c | 2 +- src/northbridge/amd/agesa/family12/agesawrapper.c | 14 ++--- src/northbridge/amd/agesa/family12/northbridge.c | 3 +- src/northbridge/amd/agesa/family14/agesawrapper.c | 16 ++--- src/northbridge/amd/agesa/family14/northbridge.c | 3 +- src/northbridge/amd/agesa/family15/agesawrapper.c | 14 ++--- src/northbridge/amd/agesa/family15/northbridge.c | 3 +- .../amd/agesa/family15rl/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family15rl/northbridge.c | 5 +- .../amd/agesa/family15tn/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family15tn/northbridge.c | 5 +- .../amd/agesa/family16kb/agesawrapper.c | 12 ++-- src/northbridge/amd/agesa/family16kb/northbridge.c | 5 +- 39 files changed, 247 insertions(+), 299 deletions(-) diff --git a/src/cpu/amd/agesa/agesawrapper_s3.c b/src/cpu/amd/agesa/agesawrapper_s3.c index b9f5051..72bcf42 100644 --- a/src/cpu/amd/agesa/agesawrapper_s3.c +++ b/src/cpu/amd/agesa/agesawrapper_s3.c @@ -59,7 +59,7 @@ AGESA_STATUS agesawrapper_amdinitresume(void) status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG_(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -93,7 +93,7 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; @@ -122,7 +122,7 @@ AGESA_STATUS agesawrapper_amdS3Save(void) AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); ASSERT(status == AGESA_SUCCESS); S3DataType = S3DataTypeNonVolatile; diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 26442f4..53c2759 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -21,7 +21,6 @@ #include <bootstate.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> @@ -32,7 +31,7 @@ static void agesawrapper_post_device(void *unused) if (acpi_is_wakeup_s3()) return; - AGESAWRAPPER(amdinitlate); + agesawrapper_amdinitlate(); #if CONFIG_AMD_SB_CIMX sb_Late_Post(); @@ -40,7 +39,7 @@ static void agesawrapper_post_device(void *unused) if (!acpi_s3_resume_allowed()) return; - AGESAWRAPPER(amdS3Save); + agesawrapper_amdS3Save(); } BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 3b13ee6..b1e9a61 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -30,7 +30,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/sch4037/sch4037.h> #include <superio/smsc/sio1036/sio1036.h> @@ -64,7 +63,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x32); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); /* Halt if there was a built in self test failure */ post_code(0x33); @@ -81,10 +80,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x35); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x36); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x37); nb_Poweron_Init(); @@ -93,10 +92,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x40); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x43); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index e0cf1d3..3a5c761 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9f3cefc..512f723 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -51,7 +50,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) outb(0xD2, 0xcd6); outb(0x00, 0xcd7); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = inb(0xcd6); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index e8f3fa4..bf4c80e 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -43,7 +42,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -67,25 +66,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index fbe60fc..5434ed3 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> @@ -80,29 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index a64ba60..7dcd9b2 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81865f/f81865f.h> @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index e0c6c98..e1db87d 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -45,7 +44,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -78,25 +78,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/amd/torpedo/romstage.c b/src/mainboard/amd/torpedo/romstage.c index 682a76e..f2bcccc 100644 --- a/src/mainboard/amd/torpedo/romstage.c +++ b/src/mainboard/amd/torpedo/romstage.c @@ -29,7 +29,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/kbc1100/kbc1100.h> #include "cpu/x86/lapic.h" @@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x35); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -72,13 +71,13 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x36); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x37); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x38); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x39); printk(BIOS_DEBUG, "sb_before_pci_init "); @@ -86,7 +85,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "passed.\n"); post_code(0x40); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x43); copy_and_run(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index 7745338..ac583dd 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include <sb_cimx.h> @@ -69,19 +68,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index f297da6..c7c71a1 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -31,7 +31,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct5572d/nct5572d.h> @@ -75,19 +74,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 213e13d..8461f0d 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -31,7 +31,6 @@ #include <console/loglevel.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" #include "southbridge/amd/agesa/hudson/hudson.h" @@ -56,7 +55,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) //outb(0xD2, 0xcd6); //outb(0x00, 0xcd7); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -105,29 +104,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) val = inb(0xcd6); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x38); printk(BIOS_DEBUG, "Got past yangtze_early_setup\n"); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); /* TODO: Disable cache is not ok. */ disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 57450ee..fbc89a7 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -19,7 +19,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -76,7 +75,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); #endif - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); if (!cpu_init_detectedx && boot_cpu()) { @@ -128,24 +127,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 95c7041..92b5292 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -33,7 +33,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <cpu/x86/cache.h> #include <sb_cimx.h> @@ -88,29 +87,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 56e9126..c9a7d53 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -18,7 +18,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -39,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -63,25 +62,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 30215ce..534bdc4 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -19,7 +19,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -96,29 +95,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 56e9126..c9a7d53 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -18,7 +18,6 @@ */ #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include <arch/acpi.h> #include <arch/cpu.h> @@ -39,7 +38,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); hudson_lpc_port80(); @@ -63,25 +62,25 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); disable_cache_as_ram(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index 02f4bc7..c4bf978 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/smsc/smscsuperio/smscsuperio.h> #include "cpu/x86/lapic.h" @@ -79,33 +78,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = AGESAWRAPPER(amdinitpost); + val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 2714d7f..9d99894 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -32,7 +32,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "cpu/x86/bist.h" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -80,33 +79,33 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x35); - AGESAWRAPPER(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); post_code(0x39); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); int s3resume = acpi_is_wakeup_early() && acpi_s3_resume_allowed(); if (!s3resume) { post_code(0x40); /* Reboots with outb(3,0x92), outb(4,0xcf9) or triple-fault all * hang, looks like DRAM re-init goes wrong, don't know why. */ - val = AGESAWRAPPER(amdinitpost); + val = agesawrapper_amdinitpost(); if (val == 7) /* fatal, amdinitenv below is going to hang */ outb(0x06, 0x0cf9); /* reset system harder instead */ post_code(0x42); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); } else { /* S3 detect */ printk(BIOS_INFO, "S3 detected\n"); post_code(0x60); - AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitresume(); - AGESAWRAPPER(amds3laterestore); + agesawrapper_amds3laterestore(); post_code(0x61); prepare_for_resume(); diff --git a/src/mainboard/supermicro/h8qgi/romstage.c b/src/mainboard/supermicro/h8qgi/romstage.c index d584a4c..9c48601 100644 --- a/src/mainboard/supermicro/h8qgi/romstage.c +++ b/src/mainboard/supermicro/h8qgi/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -46,7 +45,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ @@ -66,7 +65,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -81,7 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. @@ -101,10 +100,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/mainboard/supermicro/h8scm/romstage.c b/src/mainboard/supermicro/h8scm/romstage.c index c67a926..2f4c828 100644 --- a/src/mainboard/supermicro/h8scm/romstage.c +++ b/src/mainboard/supermicro/h8scm/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -45,7 +44,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* Halt if there was a built in self test failure */ @@ -65,7 +64,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -80,7 +79,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); nb_Ht_Init(); @@ -95,10 +94,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/mainboard/tyan/s8226/romstage.c b/src/mainboard/tyan/s8226/romstage.c index a0e8bfd..8587ed1 100644 --- a/src/mainboard/tyan/s8226/romstage.c +++ b/src/mainboard/tyan/s8226/romstage.c @@ -28,7 +28,6 @@ #include "cpu/x86/lapic.h" #include <cpu/amd/car.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "northbridge/amd/agesa/family10/reset_test.h" #include <nb_cimx.h> #include <sb_cimx.h> @@ -44,7 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; post_code(0x30); - AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); + agesawrapper_amdinitmmio(); post_code(0x31); /* For serial port. */ @@ -69,7 +68,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); post_code(0x37); - AGESAWRAPPER(amdinitreset); + agesawrapper_amdinitreset(); if (!cpu_init_detectedx && boot_cpu()) { post_code(0x38); @@ -84,7 +83,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sb_Poweron_Init(); } post_code(0x3B); - AGESAWRAPPER(amdinitearly); + agesawrapper_amdinitearly(); post_code(0x3C); /* W83627DHG pin89,90 function select is RSTOUT3#, RSTOUT2# by default. @@ -104,10 +103,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } post_code(0x40); - AGESAWRAPPER(amdinitpost); + agesawrapper_amdinitpost(); post_code(0x41); - AGESAWRAPPER(amdinitenv); + agesawrapper_amdinitenv(); post_code(0x42); post_code(0x50); diff --git a/src/northbridge/amd/agesa/agesawrapper.h b/src/northbridge/amd/agesa/agesawrapper.h index e1eb69b..7b61b4c 100644 --- a/src/northbridge/amd/agesa/agesawrapper.h +++ b/src/northbridge/amd/agesa/agesawrapper.h @@ -23,7 +23,6 @@ #include <stdint.h> #include "Porting.h" #include "AGESA.h" -#include <northbridge/amd/agesa/agesawrapper_call.h> /* Define AMD Ontario APPU SSID/SVID */ #define AMD_APU_SVID 0x1022 @@ -48,7 +47,9 @@ AGESA_STATUS agesawrapper_amdinitlate(void); AGESA_STATUS agesawrapper_amdinitpost(void); AGESA_STATUS agesawrapper_amdinitmid(void); -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus); +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func); +#define AGESA_EVENTLOG(status, stdheader) \ + agesawrapper_trace(status, stdheader, __func__) AGESA_STATUS agesawrapper_amdinitcpuio(void); AGESA_STATUS agesawrapper_amdinitmmio(void); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h deleted file mode 100644 index 55742d4..0000000 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ /dev/null @@ -1,73 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef _AGESAWRAPPER_CALL_H_ -#define _AGESAWRAPPER_CALL_H_ - -#include <stdint.h> -#include <console/console.h> -#include "AGESA.h" - -/* - * Possible AGESA_STATUS values: - * - * 0x0 = AGESA_SUCCESS - * 0x1 = AGESA_UNSUPPORTED - * 0x2 = AGESA_BOUNDS_CHK - * 0x3 = AGESA_ALERT - * 0x4 = AGESA_WARNING - * 0x5 = AGESA_ERROR - * 0x6 = AGESA_CRITICAL - * 0x7 = AGESA_FATAL - */ -static const char * decodeAGESA_STATUS(AGESA_STATUS sret) -{ - const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", - "AGESA_BOUNDS_CHK", "AGESA_ALERT", - "AGESA_WARNING", "AGESA_ERROR", - "AGESA_CRITICAL", "AGESA_FATAL" - }; - if (sret > 7) return "unknown"; /* Non-AGESA error code */ - return statusStrings[sret]; -} - -static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) -{ - AGESA_STATUS ret; - printk(BIOS_DEBUG, "agesawrapper_%s() entry\n", name); - ret = func(); - printk(BIOS_DEBUG, "agesawrapper_%s() returned %s\n", - name, decodeAGESA_STATUS(ret)); - return (u32)ret; -} - -#define AGESAWRAPPER(func) do_agesawrapper(agesawrapper_ ## func, #func) - -#define AGESAWRAPPER_PRE_CONSOLE(func) agesawrapper_ ## func() - -#if CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14 - /* TODO: These families do not pass valid HeapStatus. */ -#define AGESA_EVENTLOG(status) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0) -#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x) -#else -#define AGESA_EVENTLOG(status, heapstatus) \ - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) -#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x,y) -#endif - -#endif diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 1deb343..90640d9 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -1,9 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ #include <console/console.h> +#include <stdint.h> +#include <string.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "amdlib.h" +#include "AGESA.h" +#include "AMD.h" + + +/* + * Possible AGESA_STATUS values: + * + * 0x0 = AGESA_SUCCESS + * 0x1 = AGESA_UNSUPPORTED + * 0x2 = AGESA_BOUNDS_CHK + * 0x3 = AGESA_ALERT + * 0x4 = AGESA_WARNING + * 0x5 = AGESA_ERROR + * 0x6 = AGESA_CRITICAL + * 0x7 = AGESA_FATAL + */ +static const char * decodeAGESA_STATUS(AGESA_STATUS sret) +{ + const char* statusStrings[] = { "AGESA_SUCCESS", "AGESA_UNSUPPORTED", + "AGESA_BOUNDS_CHK", "AGESA_ALERT", + "AGESA_WARNING", "AGESA_ERROR", + "AGESA_CRITICAL", "AGESA_FATAL" + }; + if (sret > 7) return "unknown"; /* Non-AGESA error code */ + return statusStrings[sret]; +} #if 0 @@ -42,6 +86,7 @@ static void agesa_alert(EVENT_PARAMS *event) switch (event->EventInfo) { case MEM_ALERT_USER_TMG_MODE_OVERRULED: printk(BIOS_DEBUG, "Socket %x Dct %x Channel %x " + "TIMING_MODE_SPECIFIC is requested but can not be applied to current configurations.\n", (unsigned int)event->DataParam1, (unsigned int)event->DataParam2, @@ -664,25 +709,19 @@ static void interpret_agesa_eventlog(EVENT_PARAMS *event) } #endif -/** - * @param HeapStatus -the current HeapStatus - */ -AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) +static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) { - AGESA_STATUS Status; EVENT_PARAMS AmdEventParams; - LibAmdMemFill(&AmdEventParams, - 0, - sizeof(EVENT_PARAMS), - &(AmdEventParams.StdHeader)); + memset(&AmdEventParams, 0, sizeof(EVENT_PARAMS)); AmdEventParams.StdHeader.AltImageBasePtr = 0; AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; - AmdEventParams.StdHeader.HeapStatus = HeapStatus; - Status = AmdReadEventLog(&AmdEventParams); + AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus; + + AmdReadEventLog(&AmdEventParams); while (AmdEventParams.EventClass != 0) { printk(BIOS_DEBUG,"\nEventLog: EventClass = %x, EventInfo = %x.\n", (unsigned int)AmdEventParams.EventClass, @@ -693,8 +732,14 @@ AGESA_STATUS agesawrapper_amdreadeventlog(UINT8 HeapStatus) printk(BIOS_DEBUG," Param3 = %x, Param4 = %x.\n", (unsigned int)AmdEventParams.DataParam3, (unsigned int)AmdEventParams.DataParam4); - Status = AmdReadEventLog(&AmdEventParams); + AmdReadEventLog(&AmdEventParams); } +} - return Status; + +void agesawrapper_trace(AGESA_STATUS ret, AMD_CONFIG_PARAMS *StdHeader, const char *func) +{ + printk(BIOS_DEBUG, "%s() returned %s\n", func, decodeAGESA_STATUS(ret)); + if (ret != AGESA_SUCCESS) + amd_readeventlog(StdHeader); } diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 1f615e5..2c46129 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -832,7 +832,7 @@ static void amdfam10_domain_enable_resources(device_t dev) { /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam10 - %s: AmdInitMid.\n", __func__); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 9a39c0e..8d0fe90 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -247,7 +247,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -296,7 +296,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -321,7 +321,7 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -370,7 +370,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -389,7 +389,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) AmdLateParams.StdHeader.ImageBasePtr = 0; status = AmdInitLate(&AmdLateParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdLateParams.StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams.DmiTable; @@ -417,7 +417,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf ApExeParams.StdHeader.ImageBasePtr = 0; status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index bcebcd9..8d82925 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -37,7 +37,6 @@ #include "sb_cimx.h" #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> //#define FX_DEVS NODE_NUMS #define FX_DEVS 1 @@ -777,7 +776,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index e182830..8d80ef1 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -157,7 +157,7 @@ AGESA_STATUS agesawrapper_amdinitreset(VOID) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -182,7 +182,7 @@ AGESA_STATUS agesawrapper_amdinitearly(VOID) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -204,7 +204,7 @@ AGESA_STATUS agesawrapper_amdinitpost(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitPost((AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ @@ -229,8 +229,10 @@ AGESA_STATUS agesawrapper_amdinitenv(VOID) AmdParamStruct.StdHeader.Func = 0; AmdParamStruct.StdHeader.ImageBasePtr = 0; AmdCreateStruct(&AmdParamStruct); + status = AmdInitEnv((AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); + /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -347,7 +349,7 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AmdCreateStruct(&AmdParamStruct); status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -375,7 +377,7 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) (u32) AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; @@ -414,7 +416,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf ApExeParams.RelatedDataBlock = ConfigPtr; status = AmdLateRunApTask(&ApExeParams); - AGESA_EVENTLOG(status); + AGESA_EVENTLOG(status, &ApExeParams.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index aec7157..8d95dc4 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -36,7 +36,6 @@ #include <cpu/amd/mtrr.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #if CONFIG_AMD_SB_CIMX #include <sb_cimx.h> #endif @@ -775,7 +774,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 4641881..0552a02 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -210,7 +210,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) #if (defined AGESA_ENTRY_INIT_RESET) && (AGESA_ENTRY_INIT_RESET == TRUE) status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); #endif - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -243,7 +243,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); GetCpuServicesOfCurrentCore((CONST CPU_SPECIFIC_SERVICES **) & FamilySpecificServices, &AmdParamStruct.StdHeader); @@ -281,7 +281,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) OemCustomizeInitPost(PostParams); status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); @@ -317,7 +317,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) } EnvParams = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParams); - AGESA_EVENTLOG(status, EnvParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -369,7 +369,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) return status; } status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -396,7 +396,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) printk(BIOS_DEBUG, "agesawrapper_amdinitlate: AmdLateParamsPtr = %X\n", (u32) AmdLateParamsPtr); status = AmdInitLate(AmdLateParamsPtr); - AGESA_EVENTLOG(status, AmdLateParamsPtr->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParamsPtr->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParamsPtr->DmiTable; @@ -438,7 +438,7 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf printk(BIOS_DEBUG, "AmdLateRunApTask on Core: %x\n", (uint32_t) Data); status = AmdLateRunApTask((AP_EXE_PARAMS *) ConfigPtr); - AGESA_EVENTLOG(status, AmdLateParams.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams.StdHeader); ASSERT((status == AGESA_SUCCESS) || (status == AGESA_UNSUPPORTED)); return status; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index de7d026..0700a5d 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #include "sb_cimx.h" #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -710,7 +709,7 @@ static void domain_enable_resources(device_t dev) /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index c5924d2..9d2fa9f 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -43,7 +43,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -697,14 +696,14 @@ static void domain_read_resources(struct device *dev) static void domain_enable_resources(struct device *dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 54a5c69..ac8d72a 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam15.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -695,14 +694,14 @@ static void domain_read_resources(device_t dev) static void domain_enable_resources(device_t dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 7685411..043442a 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -147,7 +147,7 @@ AGESA_STATUS agesawrapper_amdinitreset(void) AmdResetParams.HtConfig.Depth = 0; status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; } @@ -172,7 +172,7 @@ AGESA_STATUS agesawrapper_amdinitearly(void) OemCustomizeInitEarly(AmdEarlyParamsPtr); status = AmdInitEarly((AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -196,7 +196,7 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AmdCreateStruct(&AmdParamStruct); PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitPost(PostParams); - AGESA_EVENTLOG(status, PostParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &PostParams->StdHeader); AmdReleaseStruct(&AmdParamStruct); /* Initialize heap space */ EmptyHeap(); @@ -222,7 +222,7 @@ AGESA_STATUS agesawrapper_amdinitenv(void) EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitEnv(EnvParam); - AGESA_EVENTLOG(status, EnvParam->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &EnvParam->StdHeader); /* Initialize Subordinate Bus Number and Secondary Bus Number * In platform BIOS this address is allocated by PCI enumeration code Modify D1F0x18 @@ -273,7 +273,7 @@ AGESA_STATUS agesawrapper_amdinitmid(void) ((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr)->GnbMidConfiguration.iGpuVgaMode = 0; /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ status = AmdInitMid((AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); AmdReleaseStruct(&AmdParamStruct); return status; @@ -299,7 +299,7 @@ AGESA_STATUS agesawrapper_amdinitlate(void) AmdCreateStruct(&AmdParamStruct); AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); - AGESA_EVENTLOG(status, AmdLateParams->StdHeader.HeapStatus); + AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); DmiTable = AmdLateParams->DmiTable; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 849f40c..db12fc3 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -42,7 +42,6 @@ #include <cpu/amd/amdfam16.h> #include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> -#include <northbridge/amd/agesa/agesawrapper_call.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES) @@ -737,14 +736,14 @@ static void domain_read_resources(device_t dev) static void domain_enable_resources(device_t dev) { if (acpi_is_wakeup_s3()) - AGESAWRAPPER(fchs3laterestore); + agesawrapper_fchs3laterestore(); /* Must be called after PCI enumeration and resource allocation */ if (!acpi_is_wakeup_s3()) { /* Enable MMIO on AMD CPU Address Map Controller */ agesawrapper_amdinitcpuio(); - AGESAWRAPPER(amdinitmid); + agesawrapper_amdinitmid(); } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); }

1 0

Patch set updated for coreboot: 5800482 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7602 -gerrit commit 580048213899e7a8829d44c3e0cc7e480706afb6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Nov 21 17:40:37 2014 +0200 AGESA fam15tn / fam15rl / fam16kb: Move LPC decode enable for serial port Move LPC decode enable out of agesawrapper.c. It should not be on the execution path of AP CPUs and function is not related to AGESA per se. Change-Id: I19d6a20fbc7a3d28601caa9aaa1d73d6930257ae Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/olivehill/agesawrapper.c | 7 ------- src/mainboard/amd/olivehill/romstage.c | 3 +++ src/mainboard/amd/parmer/agesawrapper.c | 7 ------- src/mainboard/amd/parmer/romstage.c | 3 +++ src/mainboard/amd/thatcher/agesawrapper.c | 7 ------- src/mainboard/amd/thatcher/romstage.c | 14 ++++++-------- src/mainboard/asrock/imb-a180/agesawrapper.c | 7 ------- src/mainboard/asrock/imb-a180/romstage.c | 4 ++++ src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c | 7 ------- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 3 +++ src/mainboard/lenovo/g505s/agesawrapper.c | 7 ------- src/mainboard/lenovo/g505s/romstage.c | 3 +++ 12 files changed, 22 insertions(+), 50 deletions(-) diff --git a/src/mainboard/amd/olivehill/agesawrapper.c b/src/mainboard/amd/olivehill/agesawrapper.c index 22522db..242aa27 100644 --- a/src/mainboard/amd/olivehill/agesawrapper.c +++ b/src/mainboard/amd/olivehill/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 0a982b6..c7d9397 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -56,7 +56,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init(); diff --git a/src/mainboard/amd/parmer/agesawrapper.c b/src/mainboard/amd/parmer/agesawrapper.c index c457fa3..b4b39d0 100644 --- a/src/mainboard/amd/parmer/agesawrapper.c +++ b/src/mainboard/amd/parmer/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 886ca57..4ab4d76 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -48,7 +48,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port option, plug-in card on LPC. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init(); diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index cc3c069..7425eac 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -104,8 +104,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -122,11 +120,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 0dee909..46bb452 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -45,20 +45,18 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; - u8 byte; - device_t dev; AGESAWRAPPER_PRE_CONSOLE(amdinitmmio); hudson_lpc_port80(); - //__asm__ volatile ("1: jmp 1b"); - /* TODO: */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); - byte = pci_read_config8(dev, 0x48); - byte |= 3; /* 2e, 2f */ - pci_write_config8(dev, 0x48, byte); if (!cpu_init_detectedx && boot_cpu()) { + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + u8 byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); post_code(0x31); lpc47n217_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/asrock/imb-a180/agesawrapper.c b/src/mainboard/asrock/imb-a180/agesawrapper.c index 62fc053..1412392 100644 --- a/src/mainboard/asrock/imb-a180/agesawrapper.c +++ b/src/mainboard/asrock/imb-a180/agesawrapper.c @@ -133,8 +133,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -151,11 +149,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 877d458..5fe9209 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -77,7 +77,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) *addr32 = t32; if (!cpu_init_detectedx && boot_cpu()) { + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* For serial port. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); + post_code(0x31); /* w83627uhg has a default clk of 48MHz, p.9 of data-sheet */ diff --git a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 5ae2c68..852cb8c 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -44,7 +44,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* Set LPC decode enables. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init(); diff --git a/src/mainboard/lenovo/g505s/agesawrapper.c b/src/mainboard/lenovo/g505s/agesawrapper.c index 5de359e..1ceffa0 100644 --- a/src/mainboard/lenovo/g505s/agesawrapper.c +++ b/src/mainboard/lenovo/g505s/agesawrapper.c @@ -118,8 +118,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) { AGESA_STATUS Status; UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; AMD_CONFIG_PARAMS StdHeader; /* @@ -136,11 +134,6 @@ AGESA_STATUS agesawrapper_amdinitmmio(void) MsrReg = MsrReg | 0x0000400000000000; LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); - /* For serial port */ - PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 5ae2c68..852cb8c 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -44,7 +44,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) { + pci_devfn_t dev = PCI_DEV(0, 0x14, 3); post_code(0x30); + /* Set LPC decode enables. */ + pci_write_config32(dev, 0x44, 0xff03ffd5); post_code(0x31); console_init();

1 0

Patch set updated for coreboot: d90cc36 AGESA: Common agesawrapper for S3 resume
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7162 -gerrit commit d90cc3659f128d83abeecc31a2fc8b94865d3428 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 20 07:41:20 2014 +0300 AGESA: Common agesawrapper for S3 resume Change-Id: I27cd073331659e47d241a0ce249b2d080b4bab5c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/Makefile.inc | 4 +- src/cpu/amd/agesa/agesawrapper_s3.c | 147 +++++++++++++++++++++ src/mainboard/amd/olivehill/romstage.c | 1 + src/mainboard/amd/parmer/romstage.c | 1 + src/mainboard/amd/thatcher/romstage.c | 1 + src/mainboard/asrock/imb-a180/romstage.c | 1 + src/mainboard/asus/f2a85-m/romstage.c | 1 + src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 1 + src/mainboard/lenovo/g505s/romstage.c | 1 + src/northbridge/amd/agesa/agesawrapper_call.h | 2 + src/northbridge/amd/agesa/family12/agesawrapper.c | 3 - src/northbridge/amd/agesa/family12/northbridge.c | 3 + src/northbridge/amd/agesa/family14/agesawrapper.c | 119 ----------------- src/northbridge/amd/agesa/family14/northbridge.c | 6 +- src/northbridge/amd/agesa/family15/agesawrapper.c | 3 - src/northbridge/amd/agesa/family15/northbridge.c | 3 + .../amd/agesa/family15rl/agesawrapper.c | 127 ------------------ src/northbridge/amd/agesa/family15rl/northbridge.c | 7 +- .../amd/agesa/family15tn/agesawrapper.c | 127 ------------------ src/northbridge/amd/agesa/family15tn/northbridge.c | 7 +- .../amd/agesa/family16kb/agesawrapper.c | 127 ------------------ src/northbridge/amd/agesa/family16kb/northbridge.c | 7 +- 22 files changed, 184 insertions(+), 515 deletions(-) diff --git a/src/cpu/amd/agesa/Makefile.inc b/src/cpu/amd/agesa/Makefile.inc index 668efbe..1b7ff3c 100644 --- a/src/cpu/amd/agesa/Makefile.inc +++ b/src/cpu/amd/agesa/Makefile.inc @@ -24,8 +24,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += family15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += family15rl subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += family16kb -romstage-y += s3_resume.c -ramstage-y += s3_resume.c +romstage-y += s3_resume.c agesawrapper_s3.c +ramstage-y += s3_resume.c agesawrapper_s3.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs += $(src)/cpu/amd/agesa/cache_as_ram.inc diff --git a/src/cpu/amd/agesa/agesawrapper_s3.c b/src/cpu/amd/agesa/agesawrapper_s3.c new file mode 100644 index 0000000..b9f5051 --- /dev/null +++ b/src/cpu/amd/agesa/agesawrapper_s3.c @@ -0,0 +1,147 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/mtrr.h> +#include <stdint.h> +#include <string.h> + +#include <cpu/amd/agesa/s3_resume.h> +#include <northbridge/amd/agesa/agesawrapper.h> +#include <northbridge/amd/agesa/BiosCallOuts.h> +#include "heapManager.h" + +AGESA_STATUS agesawrapper_amdinitresume(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_RESUME_PARAMS *AmdResumeParamsPtr; + S3_DATA_TYPE S3DataType; + + memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); + + AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; + AmdParamStruct.AllocationMethod = PreMemHeap; + AmdParamStruct.StdHeader.AltImageBasePtr = 0; + AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdParamStruct.StdHeader.Func = 0; + AmdParamStruct.StdHeader.ImageBasePtr = 0; + AmdCreateStruct(&AmdParamStruct); + + AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + + AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; + AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeNonVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, + (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); + + status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); + + AGESA_EVENTLOG_(status, AmdParamStruct.StdHeader.HeapStatus); + AmdReleaseStruct(&AmdParamStruct); + + return status; +} + +AGESA_STATUS agesawrapper_amds3laterestore(void) +{ + AGESA_STATUS status; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + AMD_S3LATE_PARAMS AmdS3LateParams; + AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; + S3_DATA_TYPE S3DataType; + + memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.AllocationMethod = ByHost; + AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; + AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdS3LateParamsPtr = &AmdS3LateParams; + AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; + S3DataType = S3DataTypeVolatile; + + OemAgesaGetS3Info(S3DataType, + (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, + (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); + + status = AmdS3LateRestore(AmdS3LateParamsPtr); + AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + return status; +} + +#ifndef __PRE_RAM__ +AGESA_STATUS agesawrapper_amdS3Save(void) +{ + AGESA_STATUS status; + AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; + AMD_INTERFACE_PARAMS AmdInterfaceParams; + S3_DATA_TYPE S3DataType; + + memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); + + AmdInterfaceParams.StdHeader.ImageBasePtr = 0; + AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; + AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; + AmdInterfaceParams.AllocationMethod = PostMemDram; + AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; + AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; + AmdInterfaceParams.StdHeader.Func = 0; + AmdCreateStruct(&AmdInterfaceParams); + + AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; + AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + + status = AmdS3Save(AmdS3SaveParamsPtr); + AGESA_EVENTLOG_(status, AmdInterfaceParams.StdHeader.HeapStatus); + ASSERT(status == AGESA_SUCCESS); + + S3DataType = S3DataTypeNonVolatile; + + status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.NvStorage); + + if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { + S3DataType = S3DataTypeVolatile; + + status = OemAgesaSaveS3Info(S3DataType, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, + AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); + } + + OemAgesaSaveMtrr(); + AmdReleaseStruct(&AmdInterfaceParams); + + return status; +} +#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index c7d9397..9f3cefc 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -101,6 +101,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 4ab4d76..e8f3fa4 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -84,6 +84,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 46bb452..e0c6c98 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -95,6 +95,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index 5fe9209..213e13d 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -126,6 +126,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index 385dad4..57450ee 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -144,6 +144,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 852cb8c..56e9126 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -80,6 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 852cb8c..56e9126 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -80,6 +80,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x60); AGESAWRAPPER(amdinitresume); + agesawrapper_amdinitcpuio(); AGESAWRAPPER(amds3laterestore); post_code(0x61); diff --git a/src/northbridge/amd/agesa/agesawrapper_call.h b/src/northbridge/amd/agesa/agesawrapper_call.h index 3720dd3..55742d4 100644 --- a/src/northbridge/amd/agesa/agesawrapper_call.h +++ b/src/northbridge/amd/agesa/agesawrapper_call.h @@ -63,9 +63,11 @@ static inline u32 do_agesawrapper(AGESA_STATUS (*func)(void), const char *name) /* TODO: These families do not pass valid HeapStatus. */ #define AGESA_EVENTLOG(status) \ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(0) +#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x) #else #define AGESA_EVENTLOG(status, heapstatus) \ if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(heapstatus) +#define AGESA_EVENTLOG_(x,y) AGESA_EVENTLOG(x,y) #endif #endif diff --git a/src/northbridge/amd/agesa/family12/agesawrapper.c b/src/northbridge/amd/agesa/family12/agesawrapper.c index 39b4f75..9a39c0e 100644 --- a/src/northbridge/amd/agesa/family12/agesawrapper.c +++ b/src/northbridge/amd/agesa/family12/agesawrapper.c @@ -357,9 +357,6 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 1e22025..bcebcd9 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -774,6 +774,9 @@ static void domain_enable_resources(device_t dev) sb_Mid_Post_Init(); #endif + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/agesawrapper.c b/src/northbridge/amd/agesa/family14/agesawrapper.c index 84a01b0..e182830 100644 --- a/src/northbridge/amd/agesa/family14/agesawrapper.c +++ b/src/northbridge/amd/agesa/family14/agesawrapper.c @@ -335,9 +335,6 @@ AGESA_STATUS agesawrapper_amdinitmid(VOID) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -402,122 +399,6 @@ AGESA_STATUS agesawrapper_amdinitlate(VOID) return status; } -AGESA_STATUS agesawrapper_amdinitresume(VOID) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(VOID) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_amdS3Save(VOID) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - - OemAgesaSaveMtrr(); - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} -#endif /* #ifndef __PRE_RAM__ */ - AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * ConfigPtr) { AGESA_STATUS status; diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index a604718..aec7157 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -771,8 +771,12 @@ static void domain_enable_resources(device_t dev) /* Must be called after PCI enumeration and resource allocation */ printk(BIOS_DEBUG, "\nFam14h - %s\n", __func__); - if (!acpi_is_wakeup_s3()) + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); } diff --git a/src/northbridge/amd/agesa/family15/agesawrapper.c b/src/northbridge/amd/agesa/family15/agesawrapper.c index 5c99551..4641881 100644 --- a/src/northbridge/amd/agesa/family15/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15/agesawrapper.c @@ -355,9 +355,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5a53371..de7d026 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -707,6 +707,9 @@ static void domain_enable_resources(device_t dev) #if CONFIG_AMD_SB_CIMX sb_After_Pci_Init(); #endif + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); printk(BIOS_DEBUG, " Fam15 - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15rl/agesawrapper.c b/src/northbridge/amd/agesa/family15rl/agesawrapper.c index 4f2e535..7685411 100644 --- a/src/northbridge/amd/agesa/family15rl/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15rl/agesawrapper.c @@ -260,9 +260,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -345,127 +342,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index a0f299b..c5924d2 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -700,9 +700,12 @@ static void domain_enable_resources(struct device *dev) AGESAWRAPPER(fchs3laterestore); /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family15tn/agesawrapper.c b/src/northbridge/amd/agesa/family15tn/agesawrapper.c index 4f2e535..7685411 100644 --- a/src/northbridge/amd/agesa/family15tn/agesawrapper.c +++ b/src/northbridge/amd/agesa/family15tn/agesawrapper.c @@ -260,9 +260,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -345,127 +342,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index a98d1e9..54a5c69 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -698,9 +698,12 @@ static void domain_enable_resources(device_t dev) AGESAWRAPPER(fchs3laterestore); /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving %s.\n", __func__); } diff --git a/src/northbridge/amd/agesa/family16kb/agesawrapper.c b/src/northbridge/amd/agesa/family16kb/agesawrapper.c index 4f2e535..7685411 100644 --- a/src/northbridge/amd/agesa/family16kb/agesawrapper.c +++ b/src/northbridge/amd/agesa/family16kb/agesawrapper.c @@ -260,9 +260,6 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS status; AMD_INTERFACE_PARAMS AmdParamStruct; - /* Enable MMIO on AMD CPU Address Map Controller */ - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; @@ -345,127 +342,3 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf return status; } - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **)&AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume((AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr); - - AGESA_EVENTLOG(status, AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct(&AmdParamStruct); - - return status; -} - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS), &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct(&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info(S3DataType, - (u32 *) & AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **)&AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS), &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) & GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(Status, AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info(S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct(&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index def29d1..849f40c 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -740,9 +740,12 @@ static void domain_enable_resources(device_t dev) AGESAWRAPPER(fchs3laterestore); /* Must be called after PCI enumeration and resource allocation */ - if (!acpi_is_wakeup_s3()) - AGESAWRAPPER(amdinitmid); + if (!acpi_is_wakeup_s3()) { + /* Enable MMIO on AMD CPU Address Map Controller */ + agesawrapper_amdinitcpuio(); + AGESAWRAPPER(amdinitmid); + } printk(BIOS_DEBUG, " ader - leaving domain_enable_resources.\n"); }

1 0

Patch set updated for coreboot: 5f2ab8a AGESA fam16kb: Move clearing of NoSnoopEnable bit
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7603 -gerrit commit 5f2ab8af7c6d486aa808c8d8dfa593443092a229 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 16:03:12 2014 +0200 AGESA fam16kb: Move clearing of NoSnoopEnable bit Originally from commit 4ca72139 move this code now from cpu/ to northbridge/. Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/amd_late_init.c | 18 ------------------ src/northbridge/amd/agesa/family16kb/northbridge.c | 16 ++++++++++++++++ 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index a0a3516..26442f4 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -19,10 +19,6 @@ #include <arch/acpi.h> #include <bootstate.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci_def.h> -#include <device/pci_ops.h> #include <northbridge/amd/agesa/agesawrapper.h> #include <northbridge/amd/agesa/agesawrapper_call.h> @@ -38,20 +34,6 @@ static void agesawrapper_post_device(void *unused) AGESAWRAPPER(amdinitlate); -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY_16KB) - device_t dev; - u32 value; - dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - /* disable No Snoop */ - dev = dev_find_slot(0, PCI_DEVFN(1, 1)); - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); -#endif - #if CONFIG_AMD_SB_CIMX sb_Late_Post(); #endif diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 72967c1..def29d1 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -653,9 +653,25 @@ static const struct pci_driver family10_northbridge __pci_driver = { .device = PCI_DEVICE_ID_AMD_10H_NB_HT, }; +static void fam16_finalize(void *chip_info) +{ + device_t dev; + u32 value; + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); /* clear IoapicSbFeatureEn */ + pci_write_config32(dev, 0xF8, 0); + pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ + + /* disable No Snoop */ + dev = dev_find_slot(0, PCI_DEVFN(1, 1)); + value = pci_read_config32(dev, 0x60); + value &= ~(1 << 11); + pci_write_config32(dev, 0x60, value); +} + struct chip_operations northbridge_amd_agesa_family16kb_ops = { CHIP_NAME("AMD FAM16 Northbridge") .enable_dev = 0, + .final = fam16_finalize, }; static void domain_read_resources(device_t dev)

1 0

Patch set updated for coreboot: 8814105 AGESA fam14: Move agesawrapper_amdinitmmio()
by Kyösti Mälkki 01 Dec '14

01 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7163 -gerrit commit 881410512ccb6380bb6b0d0f98be327b0e063b0d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 14:03:29 2014 +0200 AGESA fam14: Move agesawrapper_amdinitmmio() Enabling MMCONF PCI-e configuration access should be done before console_init(). This will likely move further to bootblock one day. Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/romstage.c | 5 ++--- src/mainboard/amd/inagua/romstage.c | 5 ++--- src/mainboard/amd/persimmon/romstage.c | 5 ++--- src/mainboard/amd/south_station/romstage.c | 5 ++--- src/mainboard/amd/union_station/romstage.c | 5 ++--- src/mainboard/asrock/e350m1/romstage.c | 5 ++--- src/mainboard/gizmosphere/gizmo/romstage.c | 5 ++--- src/mainboard/jetway/nf81-t56n-lf/romstage.c | 5 ++--- src/mainboard/lippert/frontrunner-af/romstage.c | 5 ++--- src/mainboard/lippert/toucan-af/romstage.c | 5 ++--- 10 files changed, 20 insertions(+), 30 deletions(-) diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index b1e9a61..c011038 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -43,6 +43,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); @@ -62,9 +64,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) } - post_code(0x32); - agesawrapper_amdinitmmio(); - /* Halt if there was a built in self test failure */ post_code(0x33); report_bist_failure(bist); diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c index 3a5c761..68822e0 100644 --- a/src/mainboard/amd/inagua/romstage.c +++ b/src/mainboard/amd/inagua/romstage.c @@ -54,6 +54,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 5434ed3..b0c1624 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -60,6 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -78,9 +80,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/south_station/romstage.c b/src/mainboard/amd/south_station/romstage.c index 7dcd9b2..727b92d 100644 --- a/src/mainboard/amd/south_station/romstage.c +++ b/src/mainboard/amd/south_station/romstage.c @@ -55,6 +55,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/amd/union_station/romstage.c b/src/mainboard/amd/union_station/romstage.c index ac583dd..4d31d2b 100644 --- a/src/mainboard/amd/union_station/romstage.c +++ b/src/mainboard/amd/union_station/romstage.c @@ -50,6 +50,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) __writemsr (0x20c, (0x0100000000ull - CACHE_ROM_SIZE) | 5); __writemsr (0x20d, (0x1000000000ull - CACHE_ROM_SIZE) | 0x800); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -67,9 +69,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index c7c71a1..ea59a8d 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,6 +55,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr(0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -73,9 +75,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/gizmosphere/gizmo/romstage.c b/src/mainboard/gizmosphere/gizmo/romstage.c index 92b5292..5132eef 100755 --- a/src/mainboard/gizmosphere/gizmo/romstage.c +++ b/src/mainboard/gizmosphere/gizmo/romstage.c @@ -68,6 +68,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) msr.hi = 0; wrmsr (MSR_PSTATE_CONTROL, msr); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -86,9 +88,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/romstage.c index 534bdc4..d7fa6bc 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/romstage.c @@ -76,6 +76,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -94,9 +96,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/lippert/frontrunner-af/romstage.c b/src/mainboard/lippert/frontrunner-af/romstage.c index c4bf978..52da850 100644 --- a/src/mainboard/lippert/frontrunner-af/romstage.c +++ b/src/mainboard/lippert/frontrunner-af/romstage.c @@ -59,6 +59,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -77,9 +79,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset(); diff --git a/src/mainboard/lippert/toucan-af/romstage.c b/src/mainboard/lippert/toucan-af/romstage.c index 9d99894..13d6f66 100644 --- a/src/mainboard/lippert/toucan-af/romstage.c +++ b/src/mainboard/lippert/toucan-af/romstage.c @@ -60,6 +60,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* All cores: set pstate 0 (1600 MHz) early to save a few ms of boot time */ __writemsr (0xc0010062, 0); + agesawrapper_amdinitmmio(); + if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_Poweron_Init(); @@ -78,9 +80,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x35); - agesawrapper_amdinitmmio(); - post_code(0x37); agesawrapper_amdinitreset();

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coreboot-gerrit December 2014