coreboot-gerrit December 2014

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Patch set updated for coreboot: 5332b2d mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREE
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7625 -gerrit commit 5332b2dae3e192d1d06598802cfef853adbdb205 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 19:35:28 2014 +1100 mainboard/lenovo/g505s/Kconfig: Remove HUDSON_LEGACY_FREE The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: I0b4e99cc0d6f89f0261f26ee61b8c175a373c730 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/Kconfig | 4 ---- src/mainboard/lenovo/g505s/romstage.c | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index fb753dc..fc3a6ac 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -68,8 +68,4 @@ config VGA_BIOS_ID string default "1002,990b" -config HUDSON_LEGACY_FREE - bool - default y - endif # BOARD_LENOVO_G505S diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index 9411ac8..d142a9d 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; agesawrapper_amdinitmmio(); - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) {

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Patch set updated for coreboot: 2b3aabe mainboard/lenovo/g505s/Kconfig: Toggle some menuconfig options
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7629 -gerrit commit 2b3aabecb2c324481aaf95c6fcfdd823cd2708f3 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 22:56:17 2014 +1100 mainboard/lenovo/g505s/Kconfig: Toggle some menuconfig options kconfig has a few options on by default that we /do not/ want on and some off that we /do/ want. Toggle these. Change-Id: Idc53738dad6fe48a04d0d872c008e198a9bb3af9 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/Kconfig | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/src/mainboard/lenovo/g505s/Kconfig b/src/mainboard/lenovo/g505s/Kconfig index fc3a6ac..6018759 100644 --- a/src/mainboard/lenovo/g505s/Kconfig +++ b/src/mainboard/lenovo/g505s/Kconfig @@ -68,4 +68,29 @@ config VGA_BIOS_ID string default "1002,990b" +# # NOTE !!! # +# Disable blobs by-default on board +config HUDSON_IMC_FWM + bool + default n +config HUDSON_XHCI_FWM + bool + default n +config HUDSON_XHCI_ENABLE + bool + default n +# # NOTE !!! # + +# Board does not have a SuperIO UART for serial +# uses EHCI debug port instead! +config CONSOLE_SERIAL + bool + default n +config DRIVERS_UART_8250IO + bool + default n +config USBDEBUG + bool + default y + endif # BOARD_LENOVO_G505S

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Patch set updated for coreboot: 462b022 mainboard/hp/pavilion_m6_1035dx: Remove HUDSON_LEGACY_FREE
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7628 -gerrit commit 462b022b5dc8dc71f2dc4fbb18a1be4436fec7ad Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Tue Dec 2 21:04:13 2014 +1100 mainboard/hp/pavilion_m6_1035dx: Remove HUDSON_LEGACY_FREE The Embedded Controller sits behind the LPC bridge and so needs LPC decodes to be enabled. Remove the LPC decode enable out of agesawrapper.c. The enable is in fact done in: 'VOID FchInitResetLpcProgram(IN VOID *FchDataPtr)' which writes the magic '0xFF03FFD5' to register 0x44 of the PCI 14.3 LPC Bridge to enable LPC decodes when HUDSON_LEGACY_FREE is not defined. Change-Id: Ia487d21faa0fceb2557dbce14ef8822116fada91 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/hp/pavilion_m6_1035dx/Kconfig | 4 ---- src/mainboard/hp/pavilion_m6_1035dx/romstage.c | 4 ---- 2 files changed, 8 deletions(-) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig index 12e0579..30e50c1 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/Kconfig +++ b/src/mainboard/hp/pavilion_m6_1035dx/Kconfig @@ -69,8 +69,4 @@ config VGA_BIOS_ID string default "1002,9900" -config HUDSON_LEGACY_FREE - bool - default y - endif # BOARD_HP_PAVILION_M6_1035DX diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index 9411ac8..d142a9d 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -40,10 +40,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; agesawrapper_amdinitmmio(); - /* Set LPC decode enables. */ - pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - pci_write_config32(dev, 0x44, 0xff03ffd5); - hudson_lpc_port80(); if (!cpu_init_detectedx && boot_cpu()) {

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New patch to review for coreboot: 265bf12 device/cpu_device.c: x86 bits winding up in ARM builds
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7634 -gerrit commit 265bf1279c8209e147eebb7db1adf0d5312cf306 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Wed Dec 3 19:28:36 2014 +1100 device/cpu_device.c: x86 bits winding up in ARM builds This seems to happen during clang builds. Change-Id: I13df19024549a732922496527f7881bc566f723b Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/device/cpu_device.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/device/cpu_device.c b/src/device/cpu_device.c index e76b539..2eada9c 100644 --- a/src/device/cpu_device.c +++ b/src/device/cpu_device.c @@ -20,6 +20,7 @@ #include <device/device.h> #include <console/console.h> +#if CONFIG_ARCH_X86 #include <cpu/x86/lapic.h> void remap_bsp_lapic(struct bus *cpu_bus) @@ -36,6 +37,7 @@ void remap_bsp_lapic(struct bus *cpu_bus) cpu->path.apic.apic_id = bsp_lapic_id; } } +#endif /* CONFIG_ARCH_X86 */ device_t add_cpu_device(struct bus *cpu_bus, unsigned apic_id, int enabled) {

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Patch merged into coreboot/master: e453b9a AGESA fam14: Move agesawrapper_amdinitmmio()
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit e453b9a91134eb56bf8076d72d0b89a044093753 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 14:03:29 2014 +0200 AGESA fam14: Move agesawrapper_amdinitmmio() Enabling MMCONF PCI-e configuration access should be done before console_init(). This will likely move further to bootblock one day. Change-Id: I20c93fe6e79ef7e7981b2f1cd3c6b446feea0f4e Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7163 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7163 for details. -gerrit

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Patch merged into coreboot/master: 1aa35c6 AGESA: Trace execution with AGESA_EVENTLOG()
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit 1aa35c6f6c2f3d3820d574579e929cbafd4304a7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 14:19:04 2014 +0300 AGESA: Trace execution with AGESA_EVENTLOG() Change-Id: I5601ed92ca808603b0a9edad118ca54aa168aceb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7604 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7604 for details. -gerrit

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Patch merged into coreboot/master: b139b5e AGESA: Common agesawrapper for S3 resume
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit b139b5efcc7f1caf541156fa8d213e3eaf231603 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Oct 20 07:41:20 2014 +0300 AGESA: Common agesawrapper for S3 resume Change-Id: I27cd073331659e47d241a0ce249b2d080b4bab5c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7162 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7162 for details. -gerrit

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Patch merged into coreboot/master: 13fdf36 AGESA: Add common eventlog
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit 13fdf36ef9f7d03135c2f0984967f56a6cda13ce Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 16:18:00 2014 +0300 AGESA: Add common eventlog Change-Id: Ibbf10a53ea671990d336340fdc96dfb37b5defd0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7161 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7161 for details. -gerrit

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Patch merged into coreboot/master: 4ee82c6 AGESA fam16kb: Move clearing of NoSnoopEnable bit
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit 4ee82c69a2ecfe1afc9a357fc7ddbaa06c10d2b5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 25 16:03:12 2014 +0200 AGESA fam16kb: Move clearing of NoSnoopEnable bit Originally from commit 4ca72139 move this code now from cpu/ to northbridge/. Change-Id: I38517cff273dd8f78bf5eda1d48fd1cd820ced88 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7603 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/7603 for details. -gerrit

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Patch merged into coreboot/master: 34ad72c AGESA: Remove duplicate OemCustomizeInitEarly declarations
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit 34ad72cd03923461d1a2cd80c798002e94f92069 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 21 13:43:46 2014 +0300 AGESA: Remove duplicate OemCustomizeInitEarly declarations Change-Id: I59b2c3f235a6b30e68e78c2fe4065fbc0488bc4c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: http://review.coreboot.org/7158 Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7158 for details. -gerrit

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coreboot-gerrit December 2014