coreboot-gerrit December 2014

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Patch set updated for coreboot: 185c9c3 northbridge/amd/agesa/family15rl: Sanitize #includes
by Edward O'Callaghan 04 Dec '14

04 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7640 -gerrit commit 185c9c387aeeec3b2c8d55a5e82cd08e79bb6b59 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Dec 4 23:23:11 2014 +1100 northbridge/amd/agesa/family15rl: Sanitize #includes Change-Id: I7cf2b33fed428d843b946b175288403aad7ce33c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family15rl/chip.h | 4 +++- src/northbridge/amd/agesa/family15rl/northbridge.c | 28 ++++++++++------------ 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/northbridge/amd/agesa/family15rl/chip.h b/src/northbridge/amd/agesa/family15rl/chip.h index 4d92f22..bab48bc 100644 --- a/src/northbridge/amd/agesa/family15rl/chip.h +++ b/src/northbridge/amd/agesa/family15rl/chip.h @@ -20,9 +20,11 @@ #ifndef _NB_AGESA_CHIP_H_ #define _NB_AGESA_CHIP_H_ +#include <stdint.h> + struct northbridge_amd_agesa_family15rl_config { u8 spdAddrLookup[2][2][4]; }; -#endif +#endif /* _NB_AGESA_CHIP_H_ */ diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 9d2fa9f..6c14557 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -18,31 +18,29 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/io.h> #include <arch/acpi.h> #include <arch/acpigen.h> -#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/amd/amdfam15.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> #include <device/device.h> +#include <device/hypertransport.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> +#include <lib.h> +#include <stdint.h> #include <stdlib.h> #include <string.h> -#include <lib.h> -#include <cpu/cpu.h> -#include <cbmem.h> -#include <AGESA.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/mtrr.h> - -#include <Porting.h> -#include <Options.h> -#include <Topology.h> -#include <cpu/amd/amdfam15.h> -#include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f15tn/AGESA.h> +#include <vendorcode/amd/agesa/f15tn/Include/Options.h> +#include <vendorcode/amd/agesa/f15tn/Include/Topology.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)

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New patch to review for coreboot: ca73324 northbridge/amd/agesa/family15rl: Sanitize #includes
by Edward O'Callaghan 04 Dec '14

04 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7640 -gerrit commit ca733247571ab9bbc37ddce275ea1eb2c3aaa194 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Dec 4 23:23:11 2014 +1100 northbridge/amd/agesa/family15rl: Sanitize #includes Change-Id: I7cf2b33fed428d843b946b175288403aad7ce33c Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/northbridge/amd/agesa/family15rl/chip.h | 4 ++- src/northbridge/amd/agesa/family15rl/northbridge.c | 30 ++++++++++------------ 2 files changed, 16 insertions(+), 18 deletions(-) diff --git a/src/northbridge/amd/agesa/family15rl/chip.h b/src/northbridge/amd/agesa/family15rl/chip.h index 4d92f22..bab48bc 100644 --- a/src/northbridge/amd/agesa/family15rl/chip.h +++ b/src/northbridge/amd/agesa/family15rl/chip.h @@ -20,9 +20,11 @@ #ifndef _NB_AGESA_CHIP_H_ #define _NB_AGESA_CHIP_H_ +#include <stdint.h> + struct northbridge_amd_agesa_family15rl_config { u8 spdAddrLookup[2][2][4]; }; -#endif +#endif /* _NB_AGESA_CHIP_H_ */ diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index 9d2fa9f..e92fa83 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -18,31 +18,27 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> #include <arch/io.h> -#include <arch/acpi.h> -#include <arch/acpigen.h> -#include <stdint.h> +#include <console/console.h> +#include <cbmem.h> +#include <cpu/amd/amdfam15.h> +#include <cpu/cpu.h> +#include <cpu/x86/lapic.h> +#include <cpu/amd/mtrr.h> #include <device/device.h> +#include <device/hypertransport.h> #include <device/pci.h> #include <device/pci_ids.h> -#include <device/hypertransport.h> +#include <lib.h> +#include <stdint.h> #include <stdlib.h> #include <string.h> -#include <lib.h> -#include <cpu/cpu.h> -#include <cbmem.h> -#include <AGESA.h> -#include <cpu/x86/lapic.h> -#include <cpu/amd/mtrr.h> - -#include <Porting.h> -#include <Options.h> -#include <Topology.h> -#include <cpu/amd/amdfam15.h> -#include <cpuRegisters.h> #include <northbridge/amd/agesa/agesawrapper.h> +#include <vendorcode/amd/agesa/f15tn/AGESA.h> +#include <vendorcode/amd/agesa/f15tn/Include/Options.h> +#include <vendorcode/amd/agesa/f15tn/Include/Topology.h> +#include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h> #define MAX_NODE_NUMS (MAX_NODES * MAX_DIES)

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Patch merged into coreboot/master: 2697c07 to-wiki.sh: Show the same status for clones.
by gerrit＠coreboot.org 04 Dec '14

04 Dec '14

the following patch was just integrated into master: commit 2697c0767b9983c63e19d109bea5b9558088a6d6 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Nov 23 10:32:03 2014 +0100 to-wiki.sh: Show the same status for clones. While it may not be the best way theoretically as theoretically only one of clones may fail if clones are not perfect, in practice there is more variance between e.g. different X60 variants than between most of the clones, yet we put all X60 variants together. Also in most cases we don't even have a way to tell the clones apart. Change-Id: I786aeed55300026fae0d9f0497d0c830a9f5e452 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7564 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> See http://review.coreboot.org/7564 for details. -gerrit

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Patch merged into coreboot/master: 2073459 via/epia-n: Switch to per-device ACPI
by gerrit＠coreboot.org 04 Dec '14

04 Dec '14

the following patch was just integrated into master: commit 20734594f94f048d74d9ee9ce3b7d93c83beb630 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Mon Sep 1 22:54:19 2014 +0200 via/epia-n: Switch to per-device ACPI Change-Id: Ica4d49b9f4f192b1544ba8cbd5f28a4019259be0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/6942 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> See http://review.coreboot.org/6942 for details. -gerrit

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Patch merged into coreboot/master: 5cb29b8 southbridge/amd/agesa/hudson/Kconfig: Fix space/tab usage
by gerrit＠coreboot.org 04 Dec '14

04 Dec '14

the following patch was just integrated into master: commit 5cb29b8f34feba617a358639eacc4f8d3d15b135 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Dec 4 04:47:16 2014 +1100 southbridge/amd/agesa/hudson/Kconfig: Fix space/tab usage Change-Id: I390c14b3e145dab45b96e25833fe5fed2e5a0adc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Reviewed-on: http://review.coreboot.org/7637 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> See http://review.coreboot.org/7637 for details. -gerrit

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Patch merged into coreboot/master: 24813c1 i945: Consolidate acpi/platform.asl
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit 24813c1490b016a10d91acbb9cc26c5b030f7314 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Oct 16 10:39:06 2014 +0200 i945: Consolidate acpi/platform.asl Change-Id: Iccb2dda8a427e483c04693e46b00e0bc2452a26b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7086 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7086 for details. -gerrit

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Patch merged into coreboot/master: 4aad743 i82801gx: Enable upper CMOS in bootblock.
by gerrit＠coreboot.org 03 Dec '14

03 Dec '14

the following patch was just integrated into master: commit 4aad743434516d6c96f1afe21dd00b631e2c3692 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Nov 22 20:36:58 2014 +0100 i82801gx: Enable upper CMOS in bootblock. Otherwise checksum may not work correctly on early stages. For compatibility with old bootblocks also enable it early in romstage. Change-Id: Ie541d71bd76af182e445aa5ef21fe5ba77091159 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> Reviewed-on: http://review.coreboot.org/7556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/7556 for details. -gerrit

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New patch to review for coreboot: 923d175 AGESA fam12 fam14: Revert to old behaviour when accessing eventlog
by Kyösti Mälkki 03 Dec '14

03 Dec '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7639 -gerrit commit 923d1759083f519c008b9630fa8b4ec2f907f6a4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Dec 3 18:55:06 2014 +0200 AGESA fam12 fam14: Revert to old behaviour when accessing eventlog There is some problem reading back from AGESA eventlog. When commit 1aa35c6 added the change of passing StdHeader.HeapStatus, like we should, we see the following failed ASSERTs and execution would continue with invalid NULL pointer dereferences. agesawrapper_amdinitpost() returned AGESA_WARNING ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f14/Proc/CPU/heapManager.c', line 578 ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c', line 283 Revert to old behaviour that without those failing ASSERTs until we have a proper solution for this. This will print a series of events like this in early romstage: EventLog: EventClass = 2, EventInfo = 8040100. Param1 = a00a, Param2 = 0. Param3 = 0, Param4 = 0. agesawrapper_amdinitpost() returned AGESA_WARNING Change-Id: Ic6e13a5ec5ba567cbd665785e87929871d8e234d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/eventlog.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/amd/agesa/eventlog.c b/src/northbridge/amd/agesa/eventlog.c index 90640d9..e153f9e 100644 --- a/src/northbridge/amd/agesa/eventlog.c +++ b/src/northbridge/amd/agesa/eventlog.c @@ -719,7 +719,10 @@ static void amd_readeventlog(AMD_CONFIG_PARAMS *StdHeader) AmdEventParams.StdHeader.CalloutPtr = (CALLOUT_ENTRY) &GetBiosCallout; AmdEventParams.StdHeader.Func = 0; AmdEventParams.StdHeader.ImageBasePtr = 0; + +#if !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY14) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY12) AmdEventParams.StdHeader.HeapStatus = StdHeader->HeapStatus; +#endif AmdReadEventLog(&AmdEventParams); while (AmdEventParams.EventClass != 0) {

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New patch to review for coreboot: 49f0e2b southbridge/amd/agesa/hudson/Kconfig: Don't build blobs by default
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7638 -gerrit commit 49f0e2b5af22b0fc697fd3ba6c2c8ca12405aa5e Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Dec 4 04:50:40 2014 +1100 southbridge/amd/agesa/hudson/Kconfig: Don't build blobs by default Don't build in non-essential blobs by default. Here is a list of reasons: 1.) XHCI mess with EHCI debug port which is far more important to work by default. 2.) Coreboot is opensource firmware, not blobboot which uses any way it can just for USB 3.0 to 'work' by default. 3.) Let boards and/or users /choose to/ include firmware if they actually /need/ it, not the converse. Change-Id: Ie90f00d7c18d725f24fe1503fadaf098d3cefa4a Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 0779000..3b94c4c 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -45,7 +45,7 @@ config EHCI_BAR config HUDSON_XHCI_ENABLE bool "Enable Hudson XHCI Controller" - default y + default n help The XHCI controller must be enabled and the XHCI firmware must be added in order to have USB 3.0 support configured @@ -55,13 +55,13 @@ config HUDSON_XHCI_ENABLE config HUDSON_XHCI_FWM bool "Add xhci firmware" - default y + default n help Add Hudson 2/3/4 XHCI Firmware to support the onboard USB 3.0 config HUDSON_IMC_FWM bool "Add imc firmware" - default y + default n help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control

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New patch to review for coreboot: 083e071 southbridge/amd/agesa/hudson/Kconfig: Fix space/tab usage
by Edward O'Callaghan 03 Dec '14

03 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7637 -gerrit commit 083e0712929139466d24d3a0fccc994f19a1e04c Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Thu Dec 4 04:47:16 2014 +1100 southbridge/amd/agesa/hudson/Kconfig: Fix space/tab usage Change-Id: I390c14b3e145dab45b96e25833fe5fed2e5a0adc Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/southbridge/amd/agesa/hudson/Kconfig | 44 ++++++++++++++++---------------- 1 file changed, 22 insertions(+), 22 deletions(-) diff --git a/src/southbridge/amd/agesa/hudson/Kconfig b/src/southbridge/amd/agesa/hudson/Kconfig index 72370ea..0779000 100644 --- a/src/southbridge/amd/agesa/hudson/Kconfig +++ b/src/southbridge/amd/agesa/hudson/Kconfig @@ -62,32 +62,32 @@ config HUDSON_XHCI_FWM config HUDSON_IMC_FWM bool "Add imc firmware" default y - help + help Add Hudson 2/3/4 IMC Firmware to support the onboard fan control config HUDSON_GEC_FWM bool default n - help + help Add Hudson 2/3/4 GEC Firmware to support the onboard gigabit Ethernet MAC. Must be connected to a Broadcom B50610 or B50610M PHY on the motherboard. config HUDSON_XHCI_FWM_FILE - string "XHCI firmware path and filename" - default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + string "XHCI firmware path and filename" + default "3rdparty/southbridge/amd/hudson/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/xhci.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_XHCI_FWM config HUDSON_IMC_FWM_FILE - string "IMC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + string "IMC firmware path and filename" + default "3rdparty/southbridge/amd/hudson/imc.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/imc.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_IMC_FWM config HUDSON_GEC_FWM_FILE - string "GEC firmware path and filename" - default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON - default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE + string "GEC firmware path and filename" + default "3rdparty/southbridge/amd/hudson/gec.bin" if SOUTHBRIDGE_AMD_AGESA_HUDSON + default "3rdparty/southbridge/amd/yangtze/gec.bin" if SOUTHBRIDGE_AMD_AGESA_YANGTZE depends on HUDSON_GEC_FWM config HUDSON_FWM @@ -98,12 +98,12 @@ config HUDSON_FWM if HUDSON_FWM config HUDSON_FWM_POSITION - hex "Hudson Firmware ROM Position" - default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 - default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 - default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 - default 0xFF820000 if BOARD_ROMSIZE_KB_8192 - default 0xFF020000 if BOARD_ROMSIZE_KB_16384 + hex "Hudson Firmware ROM Position" + default 0xFFF20000 if BOARD_ROMSIZE_KB_1024 + default 0xFFE20000 if BOARD_ROMSIZE_KB_2048 + default 0xFFC20000 if BOARD_ROMSIZE_KB_4096 + default 0xFF820000 if BOARD_ROMSIZE_KB_8192 + default 0xFF020000 if BOARD_ROMSIZE_KB_16384 help Hudson requires the firmware MUST be located at a specific address (ROM start address + 0x20000), otherwise @@ -119,9 +119,9 @@ config HUDSON_FWM_POSITION endif # HUDSON_FWM config HUDSON_SATA_MODE - int "SATA Mode" - default 0 - range 0 6 + int "SATA Mode" + default 0 + range 0 6 help Select the mode in which SATA should be driven. NATIVE AHCI, or RAID. The default is NATIVE. @@ -177,8 +177,8 @@ if HUDSON_SATA_MODE = 1 config RAID_ROM_ID string "RAID device PCI IDs" default "1022,7802" - help - 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode + help + 1022,7802 for SATA NON-RAID5 module, 1022,7803 for SATA RAID5 mode config RAID_ROM_FILE string "RAID ROM path and filename"

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coreboot-gerrit December 2014