coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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1346 discussions

Patch merged into coreboot/master: 30eda3e fsp_baytrail: remove register option for TSEG size
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit 30eda3edd72f70b3ff7ef46f5cb6e0e346683062 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Nov 16 20:28:57 2014 -0700 fsp_baytrail: remove register option for TSEG size Set the UPD entry based on the Kconfig value instead of having two separate places that the value needs to be set. Change-Id: I3d32111b59152d0a8fc49e15320c7b5a140228a6 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7490 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> Reviewed-by: FEI WANG <wangfei.jimei(a)gmail.com> See http://review.coreboot.org/7490 for details. -gerrit

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Patch merged into coreboot/master: bdfe98f fsp_baytrail: update printk to use FSP_INFO_LEVEL
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit bdfe98f92fc1e9a69aa30ba87bb679dc28e9727c Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Nov 18 19:52:46 2014 -0700 fsp_baytrail: update printk to use FSP_INFO_LEVEL Update the printk statements to use FSP_INFO_LEVEL instead of BIOS_DEBUG. These values are currently identical, but by using the second #define, it lets them all be changed as a unit. This can be overridden for a particular platform by adding a #define in chipset_fsp_util.c. Change-Id: Idbf7e55090230ec940c7c8cd3ec8632461561428 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7520 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7520 for details. -gerrit

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Patch merged into coreboot/master: 12d86e7 fsp_baytrail: update for UPD_DEVICE_CHECK macro
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit 12d86e75b067313e3464ebbc9d1ab2cd62fd61fc Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Nov 16 20:53:14 2014 -0700 fsp_baytrail: update for UPD_DEVICE_CHECK macro - Update chipset_fsp_util.c to use the UPD_DEVICE_CHECK macro. This makes the code more standardized and easier to read. - Add some debug printing that was removed in the transition. Change-Id: Iea24dd9ca53f39791bc6371291a3fa7a6fc5ed0f Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7498 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7498 for details. -gerrit

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Patch merged into coreboot/master: 5c8e7a4 fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macro
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit 5c8e7a4075a3f9f86414ea78ee790e04920e332b Author: Martin Roth <martin.roth(a)se-eng.com> Date: Tue Dec 2 10:49:21 2014 -0700 fsp_baytrail: update to add the UPD_MEMDOWN_CHECK macro - Update chipset_fsp_util.h to add the UPD_MEMDOWN_CHECK pointing into the PcdMemoryParameters structure. This is baytrail FSP specific, so it's put into the chipset code instead of the 'driver' code. Since some of the values need to be decremented and some do not, a second parameter was added to control this. This macro also does not print out the values as they are printed out separately if memory down is enabled. - Update chipset_fsp_util.c to use the UPD_MEMDOWN_CHECK macro. This makes the code more standardized and easier to read. Change-Id: I233e45db43af4726cab41f4880f1706cf8abb0b7 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7632 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7632 for details. -gerrit

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Patch merged into coreboot/master: 8d936ce fsp_baytrail: update for UPD_SPD_CHECK macro
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit 8d936ce8538d814c5981d3ac5677b53fc1b90272 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Nov 16 20:07:16 2014 -0700 fsp_baytrail: update for UPD_SPD_CHECK macro Update chipset_fsp_util.c to use the UPD_SPD_CHECK macro. This makes the code more standardized and easier to read. Change-Id: I9944e1a4df82e64a205598e98ed0f3b840af1019 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7489 Reviewed-by: Ronald G. Minnich <rminnich(a)gmail.com> Tested-by: build bot (Jenkins) See http://review.coreboot.org/7489 for details. -gerrit

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Patch merged into coreboot/master: e8d1901 fsp_baytrail: update to add the UPD_DEFAULT_CHECK macro
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit e8d1901134f01434b09f5edb790ac8465305db1c Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Nov 16 20:06:23 2014 -0700 fsp_baytrail: update to add the UPD_DEFAULT_CHECK macro - Update chipset_fsp_util.c to use the UPD_DEFAULT_CHECK macro. This makes the code more standardized and easier to read. - Update chip.h to use standardized macros Change-Id: Icbe5ec92b0aa31e21f3dd1593a96b246d83008f7 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7488 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7488 for details. -gerrit

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Patch merged into coreboot/master: 09dd70e drivers/intel/fsp: add upd macros and #defines
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit 09dd70ebb8f31b36d536f05af289e8edc069c893 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Sun Nov 16 17:32:56 2014 -0700 drivers/intel/fsp: add upd macros and #defines Add macros and #defines for working with the UPD data. This makes the code look much cleaner. Remove the UPD_ENABLE / UPD_DISABLE from fsp_rangeley/chip.h and include the fsp_values header instead. This fixes a conflict. Change-Id: I72c9556065e5c7461432a4593b75da2c8a220a12 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> Reviewed-on: http://review.coreboot.org/7487 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones(a)se-eng.com> See http://review.coreboot.org/7487 for details. -gerrit

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New patch to review for coreboot: 345d136 mainboard/lenovo/g505s: Add VGA ASL to control LCD brightness
by Edward O'Callaghan 05 Dec '14

05 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7652 -gerrit commit 345d136c3edce257dc7b1cff588c39969a25fa22 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Dec 6 01:48:05 2014 +1100 mainboard/lenovo/g505s: Add VGA ASL to control LCD brightness NOTFORMERGE - yet Change-Id: I3c9cf9148c40a58c38a96a8dcde7e8399bccb4f2 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/acpi/mainboard.asl | 24 ++- src/mainboard/lenovo/g505s/acpi/vga.asl | 280 ++++++++++++++++++++++++++ src/mainboard/lenovo/g505s/dsdt.asl | 4 + 3 files changed, 306 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/g505s/acpi/mainboard.asl b/src/mainboard/lenovo/g505s/acpi/mainboard.asl index 2e87c2c..94da877 100644 --- a/src/mainboard/lenovo/g505s/acpi/mainboard.asl +++ b/src/mainboard/lenovo/g505s/acpi/mainboard.asl @@ -110,9 +110,29 @@ Scope (\_SB) { /* Lid closed */ Method (LIDC) { /* Stub */ } /* Increase brightness */ - Method (BRTU) { /* Stub */ } + Method (BRTU) // _Q12 + { + // P80H is Port 80 for debug.. + //Store(0x12, P80H) + If (LEqual (^^PCI0.LIBR.EC0.BRTS, 0x0F)) + { +// when the screen brightness is full tilt do something? +// Notify(VPC0, 0x80) + } + Notify(^^PCI0.VGA.LCD, 0x86) + } /* Decrease brightness */ - Method (BRTD) { /* Stub */ } + Method (BRTD) // _Q11 + { + // P80H is Port 80 for debug.. + //Store(0x11, P80H) + If (LEqual (^^PCI0.LIBR.EC0.BRTS, Zero)) + { +// when the screen brightness is zero turn it off +// Notify(VPC0, 0x80) + } + Notify(^^PCI0.VGA.LCD, 0x87) + } /* Switch display */ Method (DSPS) { /* Stub */ } /* Toggle wireless */ diff --git a/src/mainboard/lenovo/g505s/acpi/vga.asl b/src/mainboard/lenovo/g505s/acpi/vga.asl new file mode 100644 index 0000000..2a8d357 --- /dev/null +++ b/src/mainboard/lenovo/g505s/acpi/vga.asl @@ -0,0 +1,280 @@ +Device (VGA) +{ + Name (_ADR, 0x00010000) // _ADR: Address + Name (PXEN, 0x80000000) + Name (PXID, 0x00020000) + Name (PXMX, 0x80000001) + Name (PXFX, 0x80000000) + Name (PXDY, 0x80000000) + Name (AF7E, 0x80000001) + OperationRegion (PCIG, PCI_Config, Zero, 0x50) + Field (PCIG, ByteAcc, NoLock, Preserve) + { + Offset (0x18), + GBA2, 32 + } + + OperationRegion (GFMM, SystemMemory, GBA2, 0x6000) + Field (GFMM, DWordAcc, NoLock, Preserve) + { + Offset (0x5F68), + AZPS, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0F) + } + + Name (DOSA, Zero) + Method (_DOS, 1, NotSerialized) // _DOS: Disable Output Switching + { + Store (Arg0, DOSA) + } + + Method (_DOD, 0, Serialized) // _DOD: Display Output Devices + { + Name (DODL, Package (0x05) + { + 0x00010100, + 0x00010110, + 0x0200, + 0x00010210, + 0x00010220 + }) + Return (DODL) + } + + Device (LCD) + { + Name (_ADR, 0x0110) // _ADR: Address + Name (BRLV, Package (0x12) + { + 0x4E, + 0x18, + One, + 0x06, + 0x0C, + 0x12, + 0x18, + 0x1E, + 0x24, + 0x2A, + 0x30, + 0x36, + 0x3C, + 0x42, + 0x48, + 0x4E, + 0x54, + 0x64 + }) + Name (BRTB, Package (0x10) {}) + Name (BRL2, Package (0x67) + { + 0x46, + 0x1E, + Zero, + One, + 0x02, + 0x03, + 0x04, + 0x05, + 0x06, + 0x07, + 0x08, + 0x09, + 0x0A, + 0x0B, + 0x0C, + 0x0D, + 0x0E, + 0x0F, + 0x10, + 0x11, + 0x12, + 0x13, + 0x14, + 0x15, + 0x16, + 0x17, + 0x18, + 0x19, + 0x1A, + 0x1B, + 0x1C, + 0x1D, + 0x1E, + 0x1F, + 0x20, + 0x21, + 0x22, + 0x23, + 0x24, + 0x25, + 0x26, + 0x27, + 0x28, + 0x29, + 0x2A, + 0x2B, + 0x2C, + 0x2D, + 0x2E, + 0x2F, + 0x30, + 0x31, + 0x32, + 0x33, + 0x34, + 0x35, + 0x36, + 0x37, + 0x38, + 0x39, + 0x3A, + 0x3B, + 0x3C, + 0x3D, + 0x3E, + 0x3F, + 0x40, + 0x41, + 0x42, + 0x43, + 0x44, + 0x45, + 0x46, + 0x47, + 0x48, + 0x49, + 0x4A, + 0x4B, + 0x4C, + 0x4D, + 0x4E, + 0x4F, + 0x50, + 0x51, + 0x52, + 0x53, + 0x54, + 0x55, + 0x56, + 0x57, + 0x58, + 0x59, + 0x5A, + 0x5B, + 0x5C, + 0x5D, + 0x5E, + 0x5F, + 0x60, + 0x61, + 0x62, + 0x63, + 0x64 + }) + Name (BRL3, Package (0x0D) + { + 0x64, + 0x43, + One, + 0x02, + 0x03, + 0x05, + 0x08, + 0x0C, + 0x12, + 0x1B, + 0x27, + 0x43, + 0x64 + }) + Method (_BCL, 0, NotSerialized) // _BCL: Brightness Control Levels + { + If (LEqual (^^^LIBR.EC0.OSTY, 0x02)) + { + Return (BRL3) + } + + If (LEqual (^^^LIBR.EC0.OSTY, 0x04)) + { + Return (BRL2) + } + Else + { + Return (BRLV) + } + } + + Method (_BCM, 1, NotSerialized) // _BCM: Brightness Control Method + { + If (LEqual (AF7E, 0x80000001)) + { + Divide (Multiply (Arg0, 0xFF), 0x64, Local1, Local0) + If (LEqual (^^^LIBR.EC0.OSTY, 0x04)) + { + If (LEqual (Arg0, Zero)) + { + Store (One, Arg0) + } + + Store (Arg0, ^^^LIBR.EC0.BRTS) + } + + If (LEqual (^^^LIBR.EC0.OSTY, 0x03)) + { + Store (LVLS (Arg0), Local1) + Store (Local1, ^^^LIBR.EC0.BRTS) + //Notify (^^^LIBR.EC0.VPC0, 0x80) + } + + // ^^^AFN7 (Local0) + } + Else + { + //Acquire (^^^LIBR.PSMX, 0xFFFF) + Store (LVLS (Arg0), Local1) + Store (Local1, ^^^LIBR.EC0.BRTS) + Store (DerefOf (Index (BRTB, Local1)), Local2) + //Store (Local2, BRTL) + //Store (0x72, BCMD) + //BSMI (Zero) + //Notify (^^^LIBR.EC0.VPC0, 0x80) + //Release (^^^LIBR.PSMX) + } + } + + Method (LVLS, 1, NotSerialized) + { + Store (One, Local0) + Store (Zero, Local1) + While (Local0) + { + Add (Local1, 0x02, Local2) + Store (DerefOf (Index (BRLV, Local2)), Local3) + And (Arg0, 0xFF, Local4) + If (LEqual (Local4, Local3)) + { + Store (Zero, Local0) + } + + If (LGreaterEqual (Local1, 0x0F)) + { + Store (Zero, Local0) + } + + If (Local0) + { + Add (One, Local1, Local1) + } + } + + Return (Local1) + } + } + + // more?? +} diff --git a/src/mainboard/lenovo/g505s/dsdt.asl b/src/mainboard/lenovo/g505s/dsdt.asl index 96038ab..bfd16ac 100644 --- a/src/mainboard/lenovo/g505s/dsdt.asl +++ b/src/mainboard/lenovo/g505s/dsdt.asl @@ -75,6 +75,10 @@ DefinitionBlock ( #include "acpi/ec.asl" } + Scope(\_SB.PCI0) { + #include "acpi/vga.asl" + } + /* Describe SMBUS for the Southbridge */ #include <southbridge/amd/agesa/hudson/acpi/smbus.asl>

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New patch to review for coreboot: b47bcd7 mainboard/lenovo/g505s: Build in EC ASL support for KBD/AUX ports
by Edward O'Callaghan 05 Dec '14

05 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7651 -gerrit commit b47bcd779d8e0b2824f852c1b9d2a5c336622afc Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 22:46:02 2014 +1100 mainboard/lenovo/g505s: Build in EC ASL support for KBD/AUX ports Rather than have Linux report: i8042: PNP: No PS/2 controller found. Probing directly. and go off probing PNP config space, build in EC ASL for the PS/2 keyboard and mouse. The ASL explicitly passes these resources to the Linux to avoid said probe. ASL Details: PS/2 keyboard (PNP0303 at 0x60,0x64 irq 1 ) PS/2 mouse (PNP0F13 at 0x60,0x64 irq 12) Change-Id: I0697fab65915907fbe2b3551182b3a1b0d665ddb Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/acpi/superio.asl | 10 ++++++++++ src/mainboard/lenovo/g505s/mainboard.h | 5 +++++ 2 files changed, 15 insertions(+) diff --git a/src/mainboard/lenovo/g505s/acpi/superio.asl b/src/mainboard/lenovo/g505s/acpi/superio.asl index e69de29..e3bb6fb 100644 --- a/src/mainboard/lenovo/g505s/acpi/superio.asl +++ b/src/mainboard/lenovo/g505s/acpi/superio.asl @@ -0,0 +1,10 @@ +/* + * Copyright (C) 2014 Edward O'Callaghan <eocallaghan(a)alterapraxis.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +/* Defines EC bits specific to the mainboard, needed by EC ASL */ +#include "mainboard.h" + +/* ACPI code for EC SuperIO functions */ +#include <ec/compal/ene932/acpi/superio.asl> diff --git a/src/mainboard/lenovo/g505s/mainboard.h b/src/mainboard/lenovo/g505s/mainboard.h index 6131df2..fa8eba8 100644 --- a/src/mainboard/lenovo/g505s/mainboard.h +++ b/src/mainboard/lenovo/g505s/mainboard.h @@ -22,4 +22,9 @@ #define PME_GPE 0x0b #define PCIE_GPE 0x18 +/* Enable PS/2 Keyboard */ +#define SIO_EC_ENABLE_PS2K +/* Enable PS/2 Mouse */ +#define SIO_EC_ENABLE_PS2M + #endif /* _MAINBOARD_LENOVO_G505S_MAINBOARD_H */

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New patch to review for coreboot: f659ee7 ec/compal/ene932/acpi/superio.asl: Provide PNP0F13 AUX ASL
by Edward O'Callaghan 05 Dec '14

05 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7650 -gerrit commit f659ee763ca83ff10de5fd6c745b8d1b8a0fa563 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Fri Dec 5 22:43:35 2014 +1100 ec/compal/ene932/acpi/superio.asl: Provide PNP0F13 AUX ASL Provide ASL to support the AUX port (a.k.a Mouse) found at 0x60,0x64 irq 12 on this EC. Change-Id: I6969ae4d492570136a8e14e42509638857e1ed85 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/ec/compal/ene932/acpi/superio.asl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/ec/compal/ene932/acpi/superio.asl b/src/ec/compal/ene932/acpi/superio.asl index db4b412..e7d5551 100644 --- a/src/ec/compal/ene932/acpi/superio.asl +++ b/src/ec/compal/ene932/acpi/superio.asl @@ -54,4 +54,35 @@ Device (SIO) { }) } #endif + +#ifdef SIO_EC_ENABLE_PS2M + Device (PS2M) // AUX port (a.k.a Mouse) + { + Name (_UID, 0) + Name (_ADR, 0) + Name (_HID, EISAID("PNP0F13")) + Name (_CID, EISAID("PNP0F13")) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate() + { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + }) + + Name (_PRS, ResourceTemplate() + { + StartDependentFn (0, 0) { + FixedIO (0x60, 0x01) + FixedIO (0x64, 0x01) + IRQNoFlags () {12} + } + EndDependentFn () + }) + } +#endif }

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coreboot-gerrit December 2014