coreboot-gerrit December 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 44e5b6e libpayload: arm: Pass the coreboot table location to the payload.
by Marc Jones 05 Dec '14

05 Dec '14

Marc Jones (marc.jones(a)se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7655 -gerrit commit 44e5b6ee51d1681a176113f7d01dfe8d1cc9638e Author: Gabe Black <gabeblack(a)google.com> Date: Sat Feb 8 06:30:49 2014 -0800 libpayload: arm: Pass the coreboot table location to the payload. To find the coreboot tables, the payload has historically searched for their signature in a predefined region of memory. This is a little clumsy on x86, but it works because you can assume certain regions are RAM. Also, there are areas which are set aside for the firmware by convention. On x86 there's a forwarding entry which goes in one of those fairly small conventional areas and which points to the CBMEM area at the end of memory. On ARM there aren't areas like that, so we've left out the forwarding entry and gone directly to CBMEM. RAM may not start at the beginning of the address space or go to its end, and that means there isn't really anywhere fixed you can put the coreboot tables. That's meant that libpayload has to be configured on a per board basis to know where to look for CBMEM. Now that we have boards that don't have fixed amounts of memory, the location of the end of RAM isn't fixed even on a per board level which means even that workaround will no longer cut it. This change makes coreboot pass the location of the coreboot tables to libpayload using r0, the first argument register. That means we'll be able to find them no matter where CBMEM is, and we can get rid of the per board search ranges. We can extend this mechanism to x86 as well, but there may be more complications and it's less necessary there. It would be a good thing to do eventually though. BUG=None TEST=Built and booted on nyan. Changed the size of memory and saw that the payload could still find the coreboot tables where before it couldn't. Built for pit, snow, and big. BRANCH=None Original-Change-Id: I7218afd999da1662b0db8172fd8125670ceac471 Original-Signed-off-by: Gabe Black <gabeblack(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/185572 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Gabe Black <gabeblack(a)chromium.org> Original-Tested-by: Gabe Black <gabeblack(a)chromium.org> (cherry picked from commit ca88f39c21158b59abe3001f986207a292359cf5) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: Iab14e9502b6ce7a55f0a72e190fa582f89f11a1e --- payloads/libpayload/arch/arm/Config.in | 8 -------- payloads/libpayload/arch/arm/coreboot.c | 25 ++++++++++--------------- payloads/libpayload/arch/arm/head.S | 8 +++++++- src/arch/arm/boot.c | 10 ++++++++-- 4 files changed, 25 insertions(+), 26 deletions(-) diff --git a/payloads/libpayload/arch/arm/Config.in b/payloads/libpayload/arch/arm/Config.in index b2ee527..b1f2bb4 100644 --- a/payloads/libpayload/arch/arm/Config.in +++ b/payloads/libpayload/arch/arm/Config.in @@ -33,12 +33,4 @@ config ARCH_SPECIFIC_OPTIONS # dummy def_bool y select LITTLE_ENDIAN -config COREBOOT_INFO_RANGE_BASE - hex "Base of the range to search for the coreboot tables" - -config COREBOOT_INFO_RANGE_SIZE - hex "Size of the range to search for the coreboot tables" - default 0x4000000 - - endif diff --git a/payloads/libpayload/arch/arm/coreboot.c b/payloads/libpayload/arch/arm/coreboot.c index b91db32..c7f371e 100644 --- a/payloads/libpayload/arch/arm/coreboot.c +++ b/payloads/libpayload/arch/arm/coreboot.c @@ -32,6 +32,9 @@ #include <libpayload.h> #include <coreboot_tables.h> +/* This pointer gets set in head.S and is passed in from coreboot. */ +void *cb_header_ptr; + /* * Some of this is x86 specific, and the rest of it is generic. Right now, * since we only support x86, we'll avoid trying to make lots of infrastructure @@ -169,22 +172,16 @@ static void cb_parse_string(unsigned char *ptr, char **info) *info = (char *)((struct cb_string *)ptr)->string; } -static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) +static int cb_parse_header(void *addr, struct sysinfo_t *info) { - struct cb_header *header; + struct cb_header *header = addr; unsigned char *ptr = addr; void *forward; int i; - for (i = 0; i < len; i += 16, ptr += 16) { - header = (struct cb_header *)ptr; - if (!strncmp((const char *)header->signature, "LBIO", 4)) - break; - } - - /* We walked the entire space and didn't find anything. */ - if (i >= len) - return -1; + /* No signature found. */ + if (strncmp((const char *)header->signature, "LBIO", 4)) + return -1; if (!header->table_bytes) return 0; @@ -209,7 +206,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) switch (rec->tag) { case CB_TAG_FORWARD: forward = phys_to_virt((void *)(unsigned long)((struct cb_forward *)rec)->forward); - return cb_parse_header(forward, len, info); + return cb_parse_header(forward, info); continue; case CB_TAG_MEMORY: cb_parse_memory(ptr, info); @@ -304,9 +301,7 @@ static int cb_parse_header(void *addr, int len, struct sysinfo_t *info) int get_coreboot_info(struct sysinfo_t *info) { - int ret = cb_parse_header( - phys_to_virt(CONFIG_LP_COREBOOT_INFO_RANGE_BASE), - CONFIG_LP_COREBOOT_INFO_RANGE_SIZE, info); + int ret = cb_parse_header(cb_header_ptr, info); return (ret == 1) ? 0 : -1; } diff --git a/payloads/libpayload/arch/arm/head.S b/payloads/libpayload/arch/arm/head.S index 54fdb5d..c5c96ea 100644 --- a/payloads/libpayload/arch/arm/head.S +++ b/payloads/libpayload/arch/arm/head.S @@ -34,12 +34,16 @@ */ ENTRY(_entry) + /* Save off the location of the coreboot tables */ + ldr r1, 1f + str r0, [r1] + /* TODO: disable interrupts */ /* TODO: Clear BSS */ /* Setup new stack */ - ldr sp, 1f + ldr sp, 2f /* TODO: Save old stack pointer and link register */ @@ -56,4 +60,6 @@ ENDPROC(_entry) .align 4 1: +.word cb_header_ptr +2: .word _stack diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index d872a79..85b2cce 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -17,12 +17,18 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <console/console.h> +#include <arch/cache.h> #include <arch/stages.h> +#include <cbmem.h> +#include <console/console.h> #include <payload_loader.h> void arch_payload_run(const struct payload *payload) { + void (*doit)(void *) = payload->entry; + void *cb_tables = cbmem_find(CBMEM_ID_CBTABLE); + printk(BIOS_SPEW, "entry = %p\n", payload->entry); - stage_exit(payload->entry); + cache_sync_instructions(); + doit(cb_tables); }

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Patch merged into coreboot/master: db3e2f0 ipq8064: Make clock code build in coreboot
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit db3e2f0931a52bee6e59d09df572fd0bfb481ff9 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Wed Apr 9 19:23:54 2014 -0700 ipq8064: Make clock code build in coreboot Include clock.c in the appropriate coreboot stages, modify the code to build cleanly. Use proper pointer cast in .h files. BUG=chrome-os-partner:27784 TEST='emerge-storm coreboot' still succeeds Original-Change-Id: I227c871b17e571f6a1db3ada3821dbb1ee884e59 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196407 (cherry picked from commit 75decceccd97298974891bb98b796eccfe11f46c) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I7d44464d4ca8153e84407fc05a25e2e79e74901e Reviewed-on: http://review.coreboot.org/7271 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See http://review.coreboot.org/7271 for details. -gerrit

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Patch merged into coreboot/master: 63956e6 ipq8064: prepare UART driver for use in coreboot
by gerrit＠coreboot.org 05 Dec '14

05 Dec '14

the following patch was just integrated into master: commit 63956e63ce6e9035aaf0a7f0363d064acb083816 Author: Vadim Bendebury <vbendeb(a)chromium.org> Date: Tue Apr 22 15:25:10 2014 -0700 ipq8064: prepare UART driver for use in coreboot These driver needs to be in src/lib, and the include file needs to be renamed to avoid collision with the top level uart.h. BUG=chrome-os-partner:27784 TEST=emerge-storm coreboot still works Original-Change-Id: Ie12f44e055bbef0eb8b1a3ffc8d6742e7a446942 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/196393 (cherry picked from commit c5618fd418642f5b009582f5f6bc51f7c9d54bec) Signed-off-by: Marc Jones <marc.jones(a)se-eng.com> Change-Id: I5e25ae350ac5e71b47a0daef078b03cc5ac35401 Reviewed-on: http://review.coreboot.org/7270 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/7270 for details. -gerrit

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New patch to review for coreboot: 79c0732 mainboard/lenovo/g505s/buildOpts.c: Trivial variable rename
by Edward O'Callaghan 05 Dec '14

05 Dec '14

Edward O'Callaghan (eocallaghan(a)alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7654 -gerrit commit 79c073249a42cfa508c9853737cf1f2ff9ce4672 Author: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> Date: Sat Dec 6 05:07:33 2014 +1100 mainboard/lenovo/g505s/buildOpts.c: Trivial variable rename Minor fix to avoid confusion, nothing to see here. Change-Id: I89d56a91d2df049e85cf49c23218620caba84880 Signed-off-by: Edward O'Callaghan <eocallaghan(a)alterapraxis.com> --- src/mainboard/lenovo/g505s/buildOpts.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index d6328bc..9ed4c74 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -385,7 +385,7 @@ GPIO_CONTROL lenovo_g505s_gpio[] = { #define SCI_MAP_XHCI_10_0 0x78 #define SCI_MAP_PWRBTN 0x73 -SCI_MAP_CONTROL m6_1035dx_sci_map[] = { +SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { {GEVENT_PIN( EC_SCI_GEVENT ), EC_SCI_GPE}, {GEVENT_PIN( EC_LID_GEVENT ), EC_LID_GPE}, {GEVENT_PIN( PCIE_GEVENT ), PCIE_GPE}, @@ -394,7 +394,7 @@ SCI_MAP_CONTROL m6_1035dx_sci_map[] = { {SCI_MAP_XHCI_10_0, PME_GPE}, {SCI_MAP_PWRBTN, PME_GPE}, }; -#define BLDCFG_FCH_SCI_MAP_LIST (&m6_1035dx_sci_map[0]) +#define BLDCFG_FCH_SCI_MAP_LIST (&lenovo_g505s_sci_map[0]) // The following definitions specify the default values for various parameters in which there are // no clearly defined defaults to be used in the common file. The values below are based on product

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New patch to review for coreboot: 0f2b94c fsp_baytrail: Update function disable code
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7653 -gerrit commit 0f2b94c57f4bbfd5b12f867b1c4b1fd9830c92b7 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Fri Dec 5 09:24:53 2014 -0700 fsp_baytrail: Update function disable code - The EDS has the function disable bit for eMMC incorrectly listed as 8. Changing it back to the correct bit 11. - The FSP will disable functions that it is told are disabled, so coreboot code that disables the functions is redundant. Removing it. Change-Id: I95c31d92d3af5182ddf7fd47f651bbb61cdedb82 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/baytrail/pmc.h | 4 +-- src/soc/intel/fsp_baytrail/southcluster.c | 48 ------------------------------- 2 files changed, 1 insertion(+), 51 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/baytrail/pmc.h b/src/soc/intel/fsp_baytrail/baytrail/pmc.h index ee15dd9..df6355a 100644 --- a/src/soc/intel/fsp_baytrail/baytrail/pmc.h +++ b/src/soc/intel/fsp_baytrail/baytrail/pmc.h @@ -83,11 +83,9 @@ # define HSUART1_DIS (1 << 3) # define HSUART2_DIS (1 << 4) # define SPI_DIS (1 << 5) -# define MMC45_DIS (1 << 8) -# define EMMC_DIS (1 << 8) # define SDIO_DIS (1 << 9) # define SD_DIS (1 << 10) -# define MIPI_DIS (1 << 11) +# define MMC_DIS (1 << 11) # define HDA_DIS (1 << 12) # define LPE_DIS (1 << 13) # define OTG_DIS (1 << 14) diff --git a/src/soc/intel/fsp_baytrail/southcluster.c b/src/soc/intel/fsp_baytrail/southcluster.c index 2216902..d87935b 100644 --- a/src/soc/intel/fsp_baytrail/southcluster.c +++ b/src/soc/intel/fsp_baytrail/southcluster.c @@ -424,44 +424,10 @@ static void sc_disable_devfn(device_t dev) fd2_mask |= name_ ## _DIS switch (dev->path.pci.devfn) { - SET_DIS_MASK(MIPI); - break; - SET_DIS_MASK(EMMC); - break; - SET_DIS_MASK(SDIO); - break; - SET_DIS_MASK(SD); - break; - SET_DIS_MASK(SATA); - break; - SET_DIS_MASK(XHCI); - /* Disable super speed PHY when XHCI is not available. */ - fd2_mask |= USH_SS_PHY_DIS; - break; SET_DIS_MASK(LPE); break; - SET_DIS_MASK(MMC45); - break; - SET_DIS_MASK(SIO_DMA1); - break; - SET_DIS_MASK(I2C1); - break; - SET_DIS_MASK(I2C2); - break; - SET_DIS_MASK(I2C3); - break; - SET_DIS_MASK(I2C4); - break; - SET_DIS_MASK(I2C5); - break; - SET_DIS_MASK(I2C6); - break; - SET_DIS_MASK(I2C7); - break; SET_DIS_MASK(TXE); break; - SET_DIS_MASK(HDA); - break; SET_DIS_MASK(PCIE_PORT1); break; SET_DIS_MASK(PCIE_PORT2); @@ -470,20 +436,6 @@ static void sc_disable_devfn(device_t dev) break; SET_DIS_MASK(PCIE_PORT4); break; - SET_DIS_MASK(EHCI); - break; - SET_DIS_MASK(SIO_DMA2); - break; - SET_DIS_MASK(PWM1); - break; - SET_DIS_MASK(PWM2); - break; - SET_DIS_MASK(HSUART1); - break; - SET_DIS_MASK(HSUART2); - break; - SET_DIS_MASK(SPI); - break; SET_DIS_MASK2(SMBUS); break; SET_DIS_MASK(OTG);

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Patch set updated for coreboot: dda7339 fsp_baytrail: Update microcode for Gold 3 FSP release
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7647 -gerrit commit dda733993c6cb91f82781c529232176666176883 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Dec 4 18:12:20 2014 -0700 fsp_baytrail: Update microcode for Gold 3 FSP release New microcode for Bay Trail I B2/B3 and D0 parts was released in the Gold 3 Bay Trail FSP release. Change the microcode size to an area instead of the exact size of the patches. This will hopefully reduce updates to the microcode size. Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 10 ++++++++-- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 51b6c19..709ff92 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,8 +19,14 @@ unsigned microcode[] = { -/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */ +/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M013067331E.h" // M0130673: Baytrail I B2 / B3 +#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 +#include "M0130679901.h" // M0130679: Baytrail I D0 + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index df6082d..ec55314 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,2 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x19800 +#define MICROCODE_REGION_LENGTH 0x30000

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Patch set updated for coreboot: 546c026 minnowmax board: Update Kconfig
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7649 -gerrit commit 546c02627d9ade91ad65720e6b0daf71c019d6e8 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Dec 4 20:46:55 2014 -0700 minnowmax board: Update Kconfig - The ROM chip is 8MB, not 4MB. - Default to the 2GB SKU instead of 1GB - that's what's out right now. - Set CBFS size to 3MB - that's what the firmware descriptor is set to. Change-Id: Ic77f5c1e898dca39de573623707ff5f5e5ca9682 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/mainboard/intel/minnowmax/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig index 6a65382..aacf174 100644 --- a/src/mainboard/intel/minnowmax/Kconfig +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -23,7 +23,7 @@ if BOARD_INTEL_MINNOWMAX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select SOC_INTEL_FSP_BAYTRAIL - select BOARD_ROMSIZE_KB_4096 + select BOARD_ROMSIZE_KB_8192 select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select OVERRIDE_MRC_CACHE_LOC @@ -49,7 +49,7 @@ config MAINBOARD_PART_NUMBER choice prompt "Memory SKU to build" - default MINNOWMAX_1GB_SKU + default MINNOWMAX_2GB_SKU config MINNOWMAX_1GB_SKU bool "1GB" @@ -81,7 +81,7 @@ config MRC_CACHE_LOC_OVERRIDE config CBFS_SIZE hex - default 0x00200000 + default 0x00300000 config DRIVERS_PS2_KEYBOARD bool

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Patch set updated for coreboot: 8213c6b fsp_baytrail: Kconfig update for Gold 3 FSP
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7648 -gerrit commit 8213c6b8b14a3185475e045b7548af4c91c8f927 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Dec 4 20:44:55 2014 -0700 fsp_baytrail: Kconfig update for Gold 3 FSP The documentation for the FSP gives the name as BAYTRAIL_FSP.fd instead of the old FvFsp.bin. Change-Id: I69c7c5ff49afd6552612cf50c9ca9b30cfb003e2 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/fsp/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_baytrail/fsp/Kconfig b/src/soc/intel/fsp_baytrail/fsp/Kconfig index 73800d6..cbe3a95 100644 --- a/src/soc/intel/fsp_baytrail/fsp/Kconfig +++ b/src/soc/intel/fsp_baytrail/fsp/Kconfig @@ -25,7 +25,7 @@ config BAYTRAIL_FSP_SPECIFIC_OPTIONS config FSP_FILE string - default "../intel/fsp/baytrail/FvFsp.bin" + default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd" help The path and filename of the Intel FSP binary for this platform.

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Patch set updated for coreboot: 8c426df FSP platform microcode: Update to remove Kconfig variable
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7646 -gerrit commit 8c426df388a560bb8f342d3614a2c30e1198ada2 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Dec 4 18:06:36 2014 -0700 FSP platform microcode: Update to remove Kconfig variable Move the Kconfig variable into a .h file - this does not need to be in Kconfig. Change-Id: I1db20790ddb32e0eb082503c6c60cbbefa818bb9 Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/cpu/intel/fsp_model_206ax/Kconfig | 6 ------ src/cpu/intel/fsp_model_206ax/Makefile.inc | 1 + src/cpu/intel/fsp_model_206ax/microcode_blob.h | 4 ++-- src/cpu/intel/fsp_model_206ax/microcode_size.h | 7 +++++++ src/cpu/intel/fsp_model_406dx/Kconfig | 6 ------ src/cpu/intel/fsp_model_406dx/Makefile.inc | 1 + src/cpu/intel/fsp_model_406dx/microcode_blob.c | 4 ++-- src/cpu/intel/fsp_model_406dx/microcode_size.h | 7 +++++++ src/drivers/intel/fsp/cache_as_ram.inc | 3 ++- src/soc/intel/fsp_baytrail/Kconfig | 6 ------ src/soc/intel/fsp_baytrail/microcode/Makefile.inc | 1 + src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 2 +- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 ++ 13 files changed, 26 insertions(+), 24 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/Kconfig b/src/cpu/intel/fsp_model_206ax/Kconfig index 043320c..c05b12b 100644 --- a/src/cpu/intel/fsp_model_206ax/Kconfig +++ b/src/cpu/intel/fsp_model_206ax/Kconfig @@ -58,12 +58,6 @@ config CPU_MICROCODE_CBFS_LOC depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff70000 -config CPU_MICROCODE_CBFS_LEN - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0xC000 if CPU_INTEL_FSP_MODEL_306AX - default 0x2800 if CPU_INTEL_FSP_MODEL_206AX - config MICROCODE_INCLUDE_PATH string "Location of the intel microcode patches" default "../intel/cpu/ivybridge/microcode" if CPU_INTEL_FSP_MODEL_306AX diff --git a/src/cpu/intel/fsp_model_206ax/Makefile.inc b/src/cpu/intel/fsp_model_206ax/Makefile.inc index e3d3ca5..577d44e 100644 --- a/src/cpu/intel/fsp_model_206ax/Makefile.inc +++ b/src/cpu/intel/fsp_model_206ax/Makefile.inc @@ -6,6 +6,7 @@ ramstage-y += acpi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c +CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_206ax ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.h b/src/cpu/intel/fsp_model_206ax/microcode_blob.h index e56bef1..6a3eaaf 100644 --- a/src/cpu/intel/fsp_model_206ax/microcode_blob.h +++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.h @@ -19,12 +19,12 @@ */ #if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX) - /* Size is 0x2800 - Update in Kconfigs when any included file changes*/ + /* Size is 0x2800 - Update in microcode_size.h when any included file changes*/ #include <microcode-m12206a7_00000029.h> #endif #if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX) - /* Size is 0xC000 - Update in Kconfigs when any included file changes*/ + /* Size is 0xC000 - Update in microcode_size.h when any included file changes*/ #include <microcode-m12306a2_00000008.h> #include <microcode-m12306a4_00000007.h> #include <microcode-m12306a5_00000007.h> diff --git a/src/cpu/intel/fsp_model_206ax/microcode_size.h b/src/cpu/intel/fsp_model_206ax/microcode_size.h new file mode 100644 index 0000000..0b0364c --- /dev/null +++ b/src/cpu/intel/fsp_model_206ax/microcode_size.h @@ -0,0 +1,7 @@ +/* Maximum size of the area that the FSP will search for the correct microcode */ + +#if IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_306AX) + #define MICROCODE_REGION_LENGTH 0xC000 +#elif IS_ENABLED(CONFIG_CPU_INTEL_FSP_MODEL_206AX) + #define MICROCODE_REGION_LENGTH 0x2800 +#endif diff --git a/src/cpu/intel/fsp_model_406dx/Kconfig b/src/cpu/intel/fsp_model_406dx/Kconfig index 11a92a0..5cd4c65 100644 --- a/src/cpu/intel/fsp_model_406dx/Kconfig +++ b/src/cpu/intel/fsp_model_406dx/Kconfig @@ -62,12 +62,6 @@ config CPU_MICROCODE_CBFS_LOC depends on SUPPORT_CPU_UCODE_IN_CBFS default 0xfff60040 -config CPU_MICROCODE_CBFS_LEN - hex - depends on SUPPORT_CPU_UCODE_IN_CBFS - default 0x14400 if FSP_MODEL_406DX_A1 - default 0x14800 if FSP_MODEL_406DX_B0 - config MICROCODE_INCLUDE_PATH string "Location of the intel microcode patches" default "../intel/cpu/rangeley/microcode" diff --git a/src/cpu/intel/fsp_model_406dx/Makefile.inc b/src/cpu/intel/fsp_model_406dx/Makefile.inc index 767cc20..e1b814d 100644 --- a/src/cpu/intel/fsp_model_406dx/Makefile.inc +++ b/src/cpu/intel/fsp_model_406dx/Makefile.inc @@ -23,6 +23,7 @@ subdirs-y += ../../x86/name ramstage-y += acpi.c cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c +CPPFLAGS_romstage += -I$(src)/cpu/intel/fsp_model_406dx ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) diff --git a/src/cpu/intel/fsp_model_406dx/microcode_blob.c b/src/cpu/intel/fsp_model_406dx/microcode_blob.c index a4b7d42..74fe76c 100644 --- a/src/cpu/intel/fsp_model_406dx/microcode_blob.c +++ b/src/cpu/intel/fsp_model_406dx/microcode_blob.c @@ -20,10 +20,10 @@ unsigned microcode[] = { #if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1) - /* Size is 0x14400 */ + /* Size is 0x14400 - update in microcode_size.h when the file changes */ #include <microcode-m01406d000e.h> #elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0) - /* Size is 0x14800 */ + /* Size is 0x14800 - update in microcode_size.h when the file changes */ #include <microcode-m01406d811d.h> #endif }; diff --git a/src/cpu/intel/fsp_model_406dx/microcode_size.h b/src/cpu/intel/fsp_model_406dx/microcode_size.h new file mode 100644 index 0000000..b638ae5 --- /dev/null +++ b/src/cpu/intel/fsp_model_406dx/microcode_size.h @@ -0,0 +1,7 @@ +/* Maximum size of the area that the FSP will search for the correct microcode */ + +#if IS_ENABLED(CONFIG_FSP_MODEL_406DX_A1) + #define MICROCODE_REGION_LENGTH 0x14400 +#elif IS_ENABLED(CONFIG_FSP_MODEL_406DX_B0) + #define MICROCODE_REGION_LENGTH 0x14800 +#endif diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc index 0fc33cb..9e8b2a2 100644 --- a/src/drivers/intel/fsp/cache_as_ram.inc +++ b/src/drivers/intel/fsp/cache_as_ram.inc @@ -22,6 +22,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> +#include <microcode_size.h> #include <cbmem.h> #ifndef CONFIG_FSP_LOC @@ -158,7 +159,7 @@ fake_fsp_stack: CAR_init_params: .long CONFIG_CPU_MICROCODE_CBFS_LOC - .long CONFIG_CPU_MICROCODE_CBFS_LEN + .long MICROCODE_REGION_LENGTH .long 0xFFFFFFFF - CACHE_ROM_SIZE + 1 /* Firmware Location */ .long CACHE_ROM_SIZE /* Total Firmware Length */ diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index e9391c3..85b3d32 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -102,12 +102,6 @@ config CPU_MICROCODE_CBFS_LOC hex default 0xfff10040 -config CPU_MICROCODE_CBFS_LEN - hex - default 0x19800 - help - This should be updated when the microcode patch changes. - config CBFS_SIZE hex default 0x200000 diff --git a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc index f6ee135..0082313 100644 --- a/src/soc/intel/fsp_baytrail/microcode/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/microcode/Makefile.inc @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # cpu_microcode-$(CONFIG_CPU_MICROCODE_CBFS_GENERATE) += microcode_blob.c +CPPFLAGS_romstage += -I$(src)/soc/intel/fsp_baytrail/microcode ifneq ($(CONFIG_MICROCODE_INCLUDE_PATH),) ifneq ($(wildcard $(shell readlink -f "$(top)/$(CONFIG_MICROCODE_INCLUDE_PATH)")),) diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 43cbf00..51b6c19 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,7 +19,7 @@ unsigned microcode[] = { -/* Size is 0x19800 - update in Kconfig when the patch gets updated. */ +/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */ #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 #include "M013067331E.h" // M0130673: Baytrail I B2 / B3 diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h new file mode 100644 index 0000000..df6082d --- /dev/null +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -0,0 +1,2 @@ +/* Maximum size of the area that the FSP will search for the correct microcode */ +#define MICROCODE_REGION_LENGTH 0x19800

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Patch set updated for coreboot: 9c3ccad fsp_baytrail: Update microcode for Gold 3 FSP release
by Martin Roth 05 Dec '14

05 Dec '14

Martin Roth (gaumless(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7647 -gerrit commit 9c3ccad770984b7aa2da5d9ed53cbb45a90681e1 Author: Martin Roth <martin.roth(a)se-eng.com> Date: Thu Dec 4 18:12:20 2014 -0700 fsp_baytrail: Update microcode for Gold 3 FSP release New microcode for Bay Trail I B2/B3 and D0 parts was released in the Gold 3 Bay Trail FSP release. Change the microcode size to an area instead of the exact size of the patches. This will hopefully reduce updates to the microcode size Change-Id: I58b4c57a4bb0e478ffd28bd74a5de6bb61540dfe Signed-off-by: Martin Roth <martin.roth(a)se-eng.com> --- src/soc/intel/fsp_baytrail/microcode/microcode_blob.c | 10 ++++++++-- src/soc/intel/fsp_baytrail/microcode/microcode_size.h | 2 +- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c index 51b6c19..709ff92 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_blob.c @@ -19,8 +19,14 @@ unsigned microcode[] = { -/* Size is 0x19800 - update in microcode_size.h when a patch gets changed. */ +/* Region size is 0x30000 - update in microcode_size.h if it gets larger. */ #include "M0230672228.h" // M0230672: Baytrail "Super SKU" B0/B1 -#include "M013067331E.h" // M0130673: Baytrail I B2 / B3 +#include "M0130673322.h" // M0130673: Baytrail I B2 / B3 +#include "M0130679901.h" // M0130679: Baytrail I D0 + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, }; diff --git a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h index df6082d..ec55314 100644 --- a/src/soc/intel/fsp_baytrail/microcode/microcode_size.h +++ b/src/soc/intel/fsp_baytrail/microcode/microcode_size.h @@ -1,2 +1,2 @@ /* Maximum size of the area that the FSP will search for the correct microcode */ -#define MICROCODE_REGION_LENGTH 0x19800 +#define MICROCODE_REGION_LENGTH 0x30000

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coreboot-gerrit December 2014