coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: 057a38b H8: make wlan CMOS option
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4652 -gerrit commit 057a38b7ba853fa31e24c7af7e1241658950e8a4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:45:53 2014 +0100 H8: make wlan CMOS option To stay in line with wwan and bluetooth. Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/h8.c | 6 +++++- src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 3 ++- src/mainboard/lenovo/x60/cmos.default | 2 ++ src/mainboard/lenovo/x60/cmos.layout | 1 + 6 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index c25903a..8b0ca20 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -174,7 +174,11 @@ static void h8_enable(device_t dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - h8_wlan_enable(1); + + if (get_option(&val, "wlan") != CB_SUCCESS) + val = 1; + h8_wlan_enable(val); + h8_trackpoint_enable(conf->trackpoint_enable); h8_usb_power_enable(1); diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index a179752..d5f3dbf 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -110,6 +110,7 @@ entries 1060 1 e 1 touchpad 1061 1 e 1 bluetooth 1062 1 e 1 wwan +1063 1 e 1 wlan 1064 8 h 0 volume 1072 1 e 9 first_battery # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..a6d8ed1 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -8,4 +8,5 @@ volume=0x3 first_battery=Primary bluetooth=Enable wwan=Enable +wlan=Enable touchpad=Enable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..db58edf 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +415 1 e 1 wlan +#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 5d82ff0..96d0922 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -12,3 +12,5 @@ volume=0x3 tft_brightness=0xff first_battery=Primary bluetooth=Enable +wlan=Enable +wwan=Enable \ No newline at end of file diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 45bb95a..730c63e 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -112,6 +112,7 @@ entries 1080 1 e 9 first_battery 1081 1 e 1 bluetooth 1082 1 e 1 wwan +1083 1 e 1 wwan # ----------------------------------------------------------------- enumerations

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New patch to review for coreboot: bef3bb4 H8: Remove wlan_enable and wwan_enable from device tree.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4651 -gerrit commit bef3bb45076f878f2a93b23794fba5d340f51dbc Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:42:09 2014 +0100 H8: Remove wlan_enable and wwan_enable from device tree. wwan_enable was never used. wlan_enable isn't something for device tree but for CMOS config if at all. Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/chip.h | 2 -- src/ec/lenovo/h8/h8.c | 2 +- src/mainboard/lenovo/t60/devicetree.cb | 1 - src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/lenovo/x60/devicetree.cb | 1 - 5 files changed, 1 insertion(+), 6 deletions(-) diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 6cb2f9b..58313d4 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -48,7 +48,5 @@ struct ec_lenovo_h8_config { u8 eventf_enable; u8 trackpoint_enable; - u8 wlan_enable; - u8 wwan_enable; }; #endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 4f9d228..c25903a 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -174,7 +174,7 @@ static void h8_enable(device_t dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - h8_wlan_enable(conf->wlan_enable); + h8_wlan_enable(1); h8_trackpoint_enable(conf->trackpoint_enable); h8_usb_power_enable(1); diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 3973f3b..57b9df4 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -143,7 +143,6 @@ chip northbridge/intel/i945 register "eventd_enable" = "0xff" register "eventc_enable" = "0x3c" - register "wlan_enable" = "0x01" register "trackpoint_enable" = "0x03" end diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..c06056b 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -73,7 +73,6 @@ chip northbridge/intel/nehalem register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - register "wlan_enable" = "0x01" register "trackpoint_enable" = "0x03" end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 91daf3a..d6e09bf 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -121,7 +121,6 @@ chip northbridge/intel/i945 register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - register "wlan_enable" = "0x01" register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382

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Patch set updated for coreboot: 4eb07e7 acpi/ec: Add missing delays
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4617 -gerrit commit 4eb07e70399097d0e795cbea49fde55bc8a35a22 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 06:50:10 2014 +0100 acpi/ec: Add missing delays Without these delays on fast systems like X230 the port is read before it's updated. Change-Id: I3e01fc348cc5170cec108a05095ba301055ed6b0 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/acpi/ec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/ec/acpi/ec.c b/src/ec/acpi/ec.c index ab287d6..634d2bb 100644 --- a/src/ec/acpi/ec.c +++ b/src/ec/acpi/ec.c @@ -53,6 +53,8 @@ int send_ec_command(u8 command) // return -1; } + udelay(10); + outb(command, ec_cmd_reg); return 0; } @@ -73,6 +75,8 @@ int send_ec_data(u8 data) // return -1; } + udelay(10); + outb(data, ec_data_reg); return 0; @@ -104,6 +108,8 @@ u8 recv_ec_data(void) // return -1; } + udelay(10); + data = inb(ec_data_reg); printk(BIOS_SPEW, "recv_ec_data: 0x%02x\n", data);

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Patch set updated for coreboot: c74956d nehalem: Restore frequency ratio registers on S3 resume
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4634 -gerrit commit c74956d2d2f66972367ba5b07c2e3986694a6da3 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:10:04 2014 +0100 nehalem: Restore frequency ratio registers on S3 resume Previously registers 274/265 and 6dc/6e8 were recomputed which lead to a slightly different values. On S3 resume it needs to be a perfect match. Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/raminit.c | 142 +++++++++++++++++--------------- 1 file changed, 77 insertions(+), 65 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 1c8ad5e..0ecd413 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -102,6 +102,10 @@ struct ram_training { u16 timing_offset[2][2][2][9]; u16 timing2_offset[2][2][2][9]; u16 timing2_bounds[2][2][2][9][2]; + u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ + u8 reg2ca9_bit0; + u32 reg_6dc; + u32 reg_6e8; }; #if !REAL @@ -259,8 +263,6 @@ struct raminfo { struct ram_training training; u32 last_500_command[2]; - u8 reg2ca9_bit0; - u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ u32 delay46_ps[2]; u32 delay54_ps[2]; u8 revision_flag_1; @@ -1680,6 +1682,9 @@ static void dump_timings(struct raminfo *info) #endif } +/* Read timings and other registers that need to be restored verbatim and + put them to CBMEM. + */ static void save_timings(struct raminfo *info) { #if CONFIG_EARLY_CBMEM_INIT @@ -1698,6 +1703,20 @@ static void save_timings(struct raminfo *info) train.reg_178 = read_1d0(0x178, 7); train.reg_10b = read_1d0(0x10b, 6); + for (channel = 0; channel < NUM_CHANNELS; channel++) { + u32 reg32; + reg32 = read_mchbar32 ((channel << 10) + 0x274); + train.reg274265[channel][0] = reg32 >> 16; + train.reg274265[channel][1] = reg32 & 0xffff; + train.reg274265[channel][2] = read_mchbar16 ((channel << 10) + 0x265) >> 8; + } + train.reg2ca9_bit0 = read_mchbar8(0x2ca9) & 1; + train.reg_6dc = read_mchbar32 (0x6dc); + train.reg_6e8 = read_mchbar32 (0x6e8); + + printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + /* Save the MRC S3 restore data to cbmem */ cbmem_initialize(); mrcdata = cbmem_add @@ -3491,6 +3510,13 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); + printk (BIOS_SPEW, "[%x] <= %x\n", reg, + ratios1.freq4_to_max_remainder | (ratios2. + freq4_to_max_remainder + << 8) + | (ratios1.divisor_f4_to_fmax << 16) | (ratios2. + divisor_f4_to_fmax + << 20)); write_mchbar32(reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder @@ -3553,7 +3579,7 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2, } } -static void set_2dxx_series(struct raminfo *info) +static void set_2dxx_series(struct raminfo *info, int s3resume) { set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005, 0, 1); @@ -3581,14 +3607,24 @@ static void set_2dxx_series(struct raminfo *info) set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency, frequency_11(info) / 2, 4000, 4000, 0, 0); - set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[0], 0, info->delay54_ps[0]); + if (s3resume) { + printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + write_mchbar32(0x6dc, info->cached_training->reg_6dc); + } else + set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[0], 0, + info->delay54_ps[0]); set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency, frequency_11(info), 2500, 0, 0, 0); set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); - set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[1], 0, info->delay54_ps[1]); + if (s3resume) { + printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + write_mchbar32(0x6e8, info->cached_training->reg_6e8); + } else + set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[1], 0, + info->delay54_ps[1]); set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0); set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455, 470, 0); @@ -3639,7 +3675,7 @@ static void set_274265(struct raminfo *info) int channel; delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info); - info->reg2ca9_bit0 = 0; + info->training.reg2ca9_bit0 = 0; for (channel = 0; channel < NUM_CHANNELS; channel++) { cycletime_ps = 900000 / lcm(2 * info->fsb_frequency, frequency_11(info)); @@ -3690,7 +3726,7 @@ static void set_274265(struct raminfo *info) if (info->delay46_ps[channel] < 2500) { info->delay46_ps[channel] = 2500; - info->reg2ca9_bit0 = 1; + info->training.reg2ca9_bit0 = 1; } delay_b_ps = halfcycle_ps(info) + delay_c_ps; if (delay_b_ps <= delay_a_ps) @@ -3703,25 +3739,24 @@ static void set_274265(struct raminfo *info) 2 * halfcycle_ps(info) * delay_e_cycles; if (info->delay54_ps[channel] < 2500) info->delay54_ps[channel] = 2500; - info->reg274265[channel][0] = delay_e_cycles; + info->training.reg274265[channel][0] = delay_e_cycles; if (delay_d_ps + 7 * halfcycle_ps(info) <= 24 * halfcycle_ps(info)) - info->reg274265[channel][1] = 0; + info->training.reg274265[channel][1] = 0; else - info->reg274265[channel][1] = + info->training.reg274265[channel][1] = div_roundup(delay_d_ps + 7 * halfcycle_ps(info), 4 * halfcycle_ps(info)) - 6; write_mchbar32((channel << 10) + 0x274, - info->reg274265[channel][1] | (info-> - reg274265[channel] - [0] << 16)); - info->reg274265[channel][2] = + info->training.reg274265[channel][1] + | (info->training.reg274265[channel][0] << 16)); + info->training.reg274265[channel][2] = div_roundup(delay_c_ps + 3 * fsbcycle_ps(info), 4 * halfcycle_ps(info)) + 1; write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->training.reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->training.reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -3733,12 +3768,12 @@ static void restore_274265(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32((channel << 10) + 0x274, - (info->reg274265[channel][0] << 16) | info-> - reg274265[channel][1]); + (info->cached_training->reg274265[channel][0] << 16) + | info->cached_training->reg274265[channel][1]); write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->cached_training->reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->cached_training->reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -4145,50 +4180,29 @@ void raminit(const int s3resume) udelay(1000); + info.cached_training = get_cached_training(); + if (x2ca8 == 0) { - if (s3resume) { -#if REAL && 0 - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 5; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xe; - info.reg274265[1][0] = 5; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xe; - info.delay46_ps[0] = 0xa86; - info.delay46_ps[1] = 0xa86; - info.delay54_ps[0] = 0xdc6; - info.delay54_ps[1] = 0xdc6; -#else - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 3; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xd; - info.reg274265[1][0] = 4; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xd; - info.delay46_ps[0] = 0x110a; - info.delay46_ps[1] = 0xb58; - info.delay54_ps[0] = 0x144a; - info.delay54_ps[1] = 0xe98; -#endif + int j; + if (s3resume && info.cached_training) { restore_274265(&info); - } else + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.cached_training->reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.cached_training->reg274265[i][j]); + } else { set_274265(&info); - int j; - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0); - for (i = 0; i < 2; i++) - for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", - i, j, info.reg274265[i][j]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i, - info.delay46_ps[i]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i, - info.delay54_ps[i]); - - set_2dxx_series(&info); + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.training.reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.training.reg274265[i][j]); + } + + set_2dxx_series(&info, s3resume); if (!(deven & 8)) { read_mchbar32(0x2cb0); @@ -4504,8 +4518,6 @@ void raminit(const int s3resume) udelay(1000); - info.cached_training = get_cached_training(); - if (s3resume) { if (info.cached_training == NULL) { u32 reg32;

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Patch set updated for coreboot: 7fdc2c2 nehalem: Small cleanup to raminint RE bindings
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4633 -gerrit commit 7fdc2c282b70794170ce44d86b19ab6bad3ccd39 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 10:59:38 2014 +0100 nehalem: Small cleanup to raminint RE bindings Change-Id: Ifd3f172a1c8a108909d1a7dae94f926b2778c2b1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/raminit.c | 29 +++-------------------------- 1 file changed, 3 insertions(+), 26 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 19af3bb..1c8ad5e 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1990,8 +1990,6 @@ static int have_match_ranks(struct raminfo *info, int channel, int ranks) return 1; } -#define WTF1 1 - static void read_4090(struct raminfo *info) { int i, channel, slot, rank, lane; @@ -3763,6 +3761,7 @@ static void dmi_setup(void) } #endif +#if REAL static void set_fsb_frequency (void) { @@ -3774,21 +3773,13 @@ set_fsb_frequency (void) smbus_block_write(0x69, 0, 5, block); } +#endif -#if REAL void raminit(const int s3resume) -#else -void raminit(int s3resume) -#endif { unsigned channel, slot, lane, rank; int i; struct raminfo info; - -#if !REAL - pre_raminit1(); -#endif - if (s3resume) { read_mchbar32(0x1e8); write_mchbar32(0x1e8, 0x6); @@ -3796,9 +3787,6 @@ void raminit(int s3resume) write_mchbar32(0x1e8, 0x4); } -#if !REAL - pre_raminit_2(); -#endif u8 x2ca8; gav(x2ca8 = read_mchbar8(0x2ca8)); @@ -3819,10 +3807,7 @@ void raminit(int s3resume) if (!s3resume) { pre_raminit_3(x2ca8); } -#endif - -#if !REAL - pre_raminit_4a(); + pre_raminit_4a(x2ca8); #endif dmi_setup(); @@ -5009,11 +4994,3 @@ unsigned long get_top_of_ram(void) return (unsigned long)tom; } #endif - -#if !REAL -int main(void) -{ - raminit(0); - return 0; -} -#endif

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Patch set updated for coreboot: d9a0a57 X201: Move early nehalem S3 magic to right place.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4632 -gerrit commit d9a0a57385508903ae0b89f9f1110c71ad0fe112 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:13:18 2014 +0100 X201: Move early nehalem S3 magic to right place. This MCH magic needs to be done before GPIO. Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 12 +++--------- src/northbridge/intel/nehalem/early_init.c | 6 ++++++ src/northbridge/intel/nehalem/raminit.c | 7 ------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8022d7b..fbf240e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -239,25 +239,19 @@ void main(unsigned long bist) if (bist == 0) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0); + nehalem_early_initialization(NEHALEM_MOBILE); + + pch_enable_lpc(); /* Enable USB Power. We need to do it early for usbdebug to work. */ ec_set_bit(0x3b, 4); - pch_enable_lpc(); - /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&x201_gpio_map); - nehalem_early_initialization(NEHALEM_MOBILE); /* This should probably go away. Until now it is required * and mainboard specific diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 81bac87..ee8c17a 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -166,4 +166,10 @@ void nehalem_early_initialization(int chipset_type) pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Magic for S3 resume. Must be done early. */ + if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) { + MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; + MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; + } } diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 0ecd413..f48b277 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3815,13 +3815,6 @@ void raminit(const int s3resume) unsigned channel, slot, lane, rank; int i; struct raminfo info; - if (s3resume) { - read_mchbar32(0x1e8); - write_mchbar32(0x1e8, 0x6); - read_mchbar32(0x1e8); - write_mchbar32(0x1e8, 0x4); - } - u8 x2ca8; gav(x2ca8 = read_mchbar8(0x2ca8));

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Patch set updated for coreboot: 2b92d48 Ibexpeak: add missing thermal init.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4636 -gerrit commit 2b92d48ec3c179c1f06e3a73ba8f1ed27d9fffe2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 23:41:48 2014 +0100 Ibexpeak: add missing thermal init. Without it ME doesn't always start correctly and no temperature is reported, no fan management and so on. Change-Id: Iff71f3afbc35a1453a20d182890ae2d196c556bd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 2 ++ src/southbridge/intel/ibexpeak/Makefile.inc | 2 +- src/southbridge/intel/ibexpeak/early_thermal.c | 47 ++++++++++++++++++++++++++ src/southbridge/intel/ibexpeak/pch.h | 1 + 4 files changed, 51 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8022d7b..5bcaccb 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -314,6 +314,8 @@ void main(unsigned long bist) pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); } + early_thermal_init(); + timestamp_add_now(TS_BEFORE_INITRAM); raminit(s3resume); diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index a29129d..e7f7d99 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -45,7 +45,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c -romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c +romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c romstage-y += ../bd82x6x/reset.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c new file mode 100644 index 0000000..9d96a34 --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include "pch.h" + +/* Early thermal init, must be done prior to giving ME its memory + which is done at the end of raminit. */ +void early_thermal_init(void) +{ + device_t dev; + + dev = PCI_DEV(0x0, 0x1f, 0x6); + + /* Program address for temporary BAR. */ + pci_write_config32(dev, 0x40, 0x40000000); + pci_write_config32(dev, 0x44, 0x0); + + /* Activate temporary BAR. */ + pci_write_config32(dev, 0x40, + pci_read_config32(dev, 0x40) | 5); + + /* Perform init. */ + write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0); + + /* Disable temporary BAR. */ + pci_write_config32(dev, 0x40, + pci_read_config32(dev, 0x40) & ~1); + pci_write_config32(dev, 0x40, 0); +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 356dd8a..df125f0 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -78,6 +78,7 @@ int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); int early_spi_read(u32 offset, u32 size, u8 *buffer); +void early_thermal_init(void); #endif #endif

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Patch set updated for coreboot: fb5295d X201: Enable expresscard hotplug.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4643 -gerrit commit fb5295d4ce7ef6c5523d7d7bd793e9ff918e1712 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jan 10 19:30:54 2014 +0100 X201: Enable expresscard hotplug. Change-Id: Ieefc2ad775c16de9aa974b2602d55ee047c9f568 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/acpi/gpe.asl | 14 ++++++++++++++ src/mainboard/lenovo/x201/devicetree.cb | 5 +++++ src/mainboard/lenovo/x201/dsdt.asl | 1 + src/mainboard/lenovo/x201/mainboard.c | 8 ++++++++ src/southbridge/intel/bd82x6x/acpi/pcie.asl | 11 +++++++++++ src/southbridge/intel/bd82x6x/acpi/pcie_port.asl | 6 ++++++ 6 files changed, 45 insertions(+) diff --git a/src/mainboard/lenovo/x201/acpi/gpe.asl b/src/mainboard/lenovo/x201/acpi/gpe.asl index b160b50..2f0ee16 100644 --- a/src/mainboard/lenovo/x201/acpi/gpe.asl +++ b/src/mainboard/lenovo/x201/acpi/gpe.asl @@ -27,4 +27,18 @@ Scope (\_GPE) /* Read EC register to clear wake status */ Store(\_SB.PCI0.LPCB.EC.WAKE, Local0) } + + Method (_L01, 0, NotSerialized) + { + If (\_SB.PCI0.RP04.HPCS) + { + Sleep (100) + Store (0x01, \_SB.PCI0.RP04.HPCS) + If (\_SB.PCI0.RP04.PDC) + { + Store (0x01, \_SB.PCI0.RP04.PDC) + Notify (\_SB.PCI0.RP04, 0x00) + } + } + } } diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..20e2259 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -128,6 +128,11 @@ chip northbridge/intel/nehalem device pci 1b.0 on # Audio Controller subsystemid 0x17aa 0x215e end + + device pci 1c.0 on end # PCIe Port #1 + device pci 1c.3 on end # PCIe Port #4 (Expresscard) + device pci 1c.4 on end # PCIe Port #4 (wlan) + device pci 1d.0 on # USB2 EHCI subsystemid 0x17aa 0x2163 end diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 783122e..0c921a6 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -23,6 +23,7 @@ #define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB #define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB #define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0 +#define RP04_IS_EXPRESSCARD 1 DefinitionBlock( "dsdt.aml", diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 6321777..75d875f 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -150,6 +150,14 @@ static void mainboard_enable(device_t dev) connected to anything and hence we don't init it. */ pc_keyboard_init(0); + + /* Enable expresscard hotplug events. */ + pci_write_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), + 0xd8, + pci_read_config32(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), 0xd8) + | (1 << 30)); + pci_write_config16(dev_find_slot(0, PCI_DEVFN(0x1c, 3)), + 0x42, 0x142); } struct chip_operations mainboard_ops = { diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie.asl b/src/southbridge/intel/bd82x6x/acpi/pcie.asl index 934cf78..785b486 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pcie.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pcie.asl @@ -167,6 +167,17 @@ Device (RP04) { Return (IRQM (RPPN)) } + +#ifdef RP04_IS_EXPRESSCARD + Device (SLOT) + { + Name (_ADR, 0x00) + Method (_RMV, 0, NotSerialized) + { + Return (0x01) + } + } +#endif } Device (RP05) diff --git a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl b/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl index fedd9c9..7c50bd6 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pcie_port.asl @@ -27,4 +27,10 @@ Field (RPCS, AnyAcc, NoLock, Preserve) Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number + Offset (0x5A), + , 3, + PDC, 1, + Offset (0xDF), + , 6, + HPCS, 1, }

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New patch to review for coreboot: a1038ce Make version look like something thinkpad_acpi would accept
by Vladimir Serbinenko 10 Jan '14

10 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4650 -gerrit commit a1038cecdb62f4ba162932400cfdd2e0f57c9b9f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Fri Jun 7 02:11:41 2013 +0200 Make version look like something thinkpad_acpi would accept thinkpad_acpi checks that BIOS version matches some pattern. Report version in this form. Not cleaned up as the idea of this patch seems to be met with resistance. Can make it Thinkpad-specific if the idea is accepted. Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/arch/x86/boot/smbios.c | 7 +++++-- src/mainboard/lenovo/Kconfig | 4 ++++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c index 308336a..587f5b8 100644 --- a/src/arch/x86/boot/smbios.c +++ b/src/arch/x86/boot/smbios.c @@ -130,12 +130,15 @@ static int smbios_write_type0(unsigned long *current, int handle) t->vendor = smbios_add_string(t->eos, "coreboot"); #if !CONFIG_CHROMEOS +#ifndef CONFIG_VENDOR_VERSION +#define CONFIG_VENDOR_VERSION "" +#endif t->bios_release_date = smbios_add_string(t->eos, COREBOOT_DMI_DATE); if (strlen(CONFIG_LOCALVERSION)) - t->bios_version = smbios_add_string(t->eos, CONFIG_LOCALVERSION); + t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION CONFIG_LOCALVERSION); else - t->bios_version = smbios_add_string(t->eos, COREBOOT_VERSION); + t->bios_version = smbios_add_string(t->eos, CONFIG_VENDOR_VERSION COREBOOT_VERSION); #else #define SPACES \ " " diff --git a/src/mainboard/lenovo/Kconfig b/src/mainboard/lenovo/Kconfig index 8ee2778..8aa9631 100644 --- a/src/mainboard/lenovo/Kconfig +++ b/src/mainboard/lenovo/Kconfig @@ -29,4 +29,8 @@ config MAINBOARD_VENDOR string default "Lenovo" +config VENDOR_VERSION + string + default "CBET4000 " + endif # VENDOR_LENOVO

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Patch set updated for coreboot: f53d04d intel/fsp: Fix microcode including
by Patrick Georgi 10 Jan '14

10 Jan '14

Patrick Georgi (patrick(a)georgi-clan.de) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4646 -gerrit commit f53d04dce4d27ba94e0948a2ce490e713aa7360e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jan 10 20:01:26 2014 +0100 intel/fsp: Fix microcode including IS_ENABLED() requires the full define (incl. CONFIG_ prefix) but isn't needed here. Change-Id: I91d504367c75ce3fcecc6fa2499afaa0896595d3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> --- src/cpu/intel/fsp_model_206ax/microcode_blob.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/cpu/intel/fsp_model_206ax/microcode_blob.c b/src/cpu/intel/fsp_model_206ax/microcode_blob.c index 309ea75..c2538e8 100644 --- a/src/cpu/intel/fsp_model_206ax/microcode_blob.c +++ b/src/cpu/intel/fsp_model_206ax/microcode_blob.c @@ -18,7 +18,5 @@ */ unsigned microcode[] = { -#if IS_ENABLED(SUPPORT_CPU_UCODE_IN_CBFS) #include "microcode_blob.h" -#endif };

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coreboot-gerrit January 2014