coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

1 participants
1801 discussions

Patch set updated for coreboot: cbe9dc3 ibexpeak / bd82x6x: Make SATA mode user-visible option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4658 -gerrit commit cbe9dc3e3be5800472e5c4f3b8b8a4552fa90931 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 07:46:50 2014 +0100 ibexpeak / bd82x6x: Make SATA mode user-visible option. Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/cmos.layout | 5 ++- src/mainboard/google/butterfly/devicetree.cb | 2 - src/mainboard/google/link/cmos.layout | 5 ++- src/mainboard/google/link/devicetree.cb | 2 - src/mainboard/google/parrot/cmos.layout | 5 ++- src/mainboard/google/parrot/devicetree.cb | 2 - src/mainboard/google/stout/cmos.layout | 5 ++- src/mainboard/google/stout/devicetree.cb | 2 - src/mainboard/intel/cougar_canyon2/cmos.layout | 5 ++- src/mainboard/intel/cougar_canyon2/devicetree.cb | 2 - src/mainboard/intel/emeraldlake2/cmos.layout | 5 ++- src/mainboard/intel/emeraldlake2/devicetree.cb | 2 - src/mainboard/kontron/ktqm77/cmos.layout | 5 ++- src/mainboard/kontron/ktqm77/devicetree.cb | 2 - src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 5 ++- src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/samsung/lumpy/cmos.layout | 5 ++- src/mainboard/samsung/lumpy/devicetree.cb | 2 - src/mainboard/samsung/stumpy/cmos.layout | 5 ++- src/mainboard/samsung/stumpy/devicetree.cb | 2 - src/southbridge/intel/bd82x6x/chip.h | 2 - src/southbridge/intel/bd82x6x/sata.c | 51 ++++++------------------ src/southbridge/intel/ibexpeak/sata.c | 51 ++++++------------------ 24 files changed, 67 insertions(+), 107 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624..ee5ee25 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -132,6 +133,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index e7a50c0..9a7a1d5 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -56,8 +56,6 @@ chip northbridge/intel/sandybridge #register "gpi1_routing" = "1" #SMI from EC register "gpi13_routing" = "2" #SCI from EC - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 15f420d..8f0ed3c 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi7_routing" = "2" register "gpi8_routing" = "1" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_port0_gen3_tx" = "0x00880a7f" diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf..59586cc 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge register "gpi8_routing" = "1" register "gpi15_routing" = "1" #lid switch gpe - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 6e02020..653d3fe 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi6_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s register "sata_interface_speed_support" = "0x2" diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index e66574e..c499a56 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/fsp_sandybridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" device pci 14.0 on end # XHCI diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0bb42d6..0d81502 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -50,8 +50,6 @@ chip northbridge/intel/sandybridge register "alt_gp_smi_en" = "0x0002" register "gpe0_en" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 47cd60f..dc6a44b 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 11 sata_mode +#412 4 r 0 unused # coreboot config options: additional mainboard options 416 4 e 10 systemp_type @@ -162,6 +163,8 @@ enumerations 10 2 LM75@90 10 3 GPIO16 10 4 LM75@9e +11 0 AHCI +11 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 65c03c4..f6390ac 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -36,8 +36,6 @@ chip northbridge/intel/sandybridge register "pirqg_routing" = "0x8b" register "pirqh_routing" = "0x8b" - register "ide_legacy_combined" = "0x0" # TODO: Does nothing since generations, remove from sb code? - register "sata_ahci" = "0x1" # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..858f203 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -9,3 +9,4 @@ first_battery=Primary bluetooth=Enable wwan=Enable touchpad=Enable +sata_mode=AHCI diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..9e9942e 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +417 1 e 9 sata_mode +#418 566 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -129,6 +130,8 @@ enumerations 7 2 Keep 8 0 Secondary 8 1 Primary +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..5549327 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -107,7 +107,6 @@ chip northbridge/intel/nehalem register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x33" register "gpe0_en" = "0x20022046" diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9552021..208e8ee 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..69729d7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi7_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xa00-0xa3f diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index 6d2ac45..ec393a5 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -84,7 +84,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ee01e8a..ab03c79 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -49,8 +49,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "0" register "gpi14_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # SuperIO range is 0x700-0x73f diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 828466c..0f2f0e9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -64,8 +64,6 @@ struct southbridge_intel_bd82x6x_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..5d5fdbd 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -45,6 +46,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -53,48 +55,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + /* AHCI */ + if (sata_mode == 0) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -156,6 +126,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -244,15 +215,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d30fae2..bf884aa 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -46,6 +47,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -54,48 +56,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); - } else if (config->sata_ahci) { + if (sata_mode == 0) { + /* AHCI */ u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -158,6 +128,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -245,15 +216,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8;

1 0

Patch merged into filo/master: 73484d6 drop hexdump() declaration
by gerrit＠coreboot.org 11 Jan '14

11 Jan '14

the following patch was just integrated into master: commit 73484d659450e7cb8a44ee3c47003c187b947793 Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jan 10 20:23:22 2014 +0100 drop hexdump() declaration Change-Id: I2a2691a33cde3b06111b92d63b81f4e5c2bd3f53 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/4648 for details. -gerrit

1 0

Patch set updated for coreboot: b0d9fda ibexpeak / bd82x6x: Make SATA mode user-visible option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4658 -gerrit commit b0d9fdab9db79cb526df653e5511122fbb331225 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 07:46:50 2014 +0100 ibexpeak / bd82x6x: Make SATA mode user-visible option. Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/cmos.layout | 5 ++- src/mainboard/google/link/cmos.layout | 5 ++- src/mainboard/google/link/devicetree.cb | 2 - src/mainboard/google/parrot/cmos.layout | 5 ++- src/mainboard/google/parrot/devicetree.cb | 2 - src/mainboard/google/stout/cmos.layout | 5 ++- src/mainboard/google/stout/devicetree.cb | 2 - src/mainboard/intel/cougar_canyon2/cmos.layout | 5 ++- src/mainboard/intel/cougar_canyon2/devicetree.cb | 2 - src/mainboard/intel/emeraldlake2/cmos.layout | 5 ++- src/mainboard/intel/emeraldlake2/devicetree.cb | 2 - src/mainboard/kontron/ktqm77/cmos.layout | 5 ++- src/mainboard/kontron/ktqm77/devicetree.cb | 2 - src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 5 ++- src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/samsung/lumpy/cmos.layout | 5 ++- src/mainboard/samsung/lumpy/devicetree.cb | 2 - src/mainboard/samsung/stumpy/cmos.layout | 5 ++- src/mainboard/samsung/stumpy/devicetree.cb | 2 - src/southbridge/intel/bd82x6x/chip.h | 2 - src/southbridge/intel/bd82x6x/sata.c | 51 ++++++------------------ src/southbridge/intel/ibexpeak/sata.c | 51 ++++++------------------ 23 files changed, 67 insertions(+), 105 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624..ee5ee25 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -132,6 +133,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 15f420d..8f0ed3c 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi7_routing" = "2" register "gpi8_routing" = "1" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_port0_gen3_tx" = "0x00880a7f" diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf..59586cc 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge register "gpi8_routing" = "1" register "gpi15_routing" = "1" #lid switch gpe - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 6e02020..653d3fe 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi6_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s register "sata_interface_speed_support" = "0x2" diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index e66574e..c499a56 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/fsp_sandybridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" device pci 14.0 on end # XHCI diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0bb42d6..0d81502 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -50,8 +50,6 @@ chip northbridge/intel/sandybridge register "alt_gp_smi_en" = "0x0002" register "gpe0_en" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 47cd60f..dc6a44b 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 11 sata_mode +#412 4 r 0 unused # coreboot config options: additional mainboard options 416 4 e 10 systemp_type @@ -162,6 +163,8 @@ enumerations 10 2 LM75@90 10 3 GPIO16 10 4 LM75@9e +11 0 AHCI +11 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 65c03c4..f6390ac 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -36,8 +36,6 @@ chip northbridge/intel/sandybridge register "pirqg_routing" = "0x8b" register "pirqh_routing" = "0x8b" - register "ide_legacy_combined" = "0x0" # TODO: Does nothing since generations, remove from sb code? - register "sata_ahci" = "0x1" # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..858f203 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -9,3 +9,4 @@ first_battery=Primary bluetooth=Enable wwan=Enable touchpad=Enable +sata_mode=AHCI diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..9e9942e 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +417 1 e 9 sata_mode +#418 566 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -129,6 +130,8 @@ enumerations 7 2 Keep 8 0 Secondary 8 1 Primary +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..5549327 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -107,7 +107,6 @@ chip northbridge/intel/nehalem register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x33" register "gpe0_en" = "0x20022046" diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9552021..208e8ee 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..69729d7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi7_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xa00-0xa3f diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index 6d2ac45..ec393a5 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -84,7 +84,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ee01e8a..ab03c79 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -49,8 +49,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "0" register "gpi14_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # SuperIO range is 0x700-0x73f diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 828466c..0f2f0e9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -64,8 +64,6 @@ struct southbridge_intel_bd82x6x_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..5d5fdbd 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -45,6 +46,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -53,48 +55,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + /* AHCI */ + if (sata_mode == 0) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -156,6 +126,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -244,15 +215,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d30fae2..bf884aa 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -46,6 +47,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -54,48 +56,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); - } else if (config->sata_ahci) { + if (sata_mode == 0) { + /* AHCI */ u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -158,6 +128,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -245,15 +216,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8;

1 0

Patch merged into coreboot/master: f53d04d intel/fsp: Fix microcode including
by gerrit＠coreboot.org 11 Jan '14

11 Jan '14

the following patch was just integrated into master: commit f53d04dce4d27ba94e0948a2ce490e713aa7360e Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Fri Jan 10 20:01:26 2014 +0100 intel/fsp: Fix microcode including IS_ENABLED() requires the full define (incl. CONFIG_ prefix) but isn't needed here. Change-Id: I91d504367c75ce3fcecc6fa2499afaa0896595d3 Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> See http://review.coreboot.org/4646 for details. -gerrit

1 0

Patch set updated for coreboot: 4882a43 ec/lenovo/h8: Make trackpoint enable a CMOS option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4654 -gerrit commit 4882a43ed3aac58c30ebbe29221fcf9384da0cf2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 04:22:35 2014 +0100 ec/lenovo/h8: Make trackpoint enable a CMOS option. To be consistent with touchpad counterpart. Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/pmh7/pmh7.c | 12 ++++++++++++ src/ec/lenovo/pmh7/pmh7.h | 1 + src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 3 ++- src/mainboard/lenovo/x60/cmos.default | 3 ++- src/mainboard/lenovo/x60/cmos.layout | 1 + 7 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 9607c83..a4d0ccc 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -55,6 +55,14 @@ void pmh7_touchpad_enable(int onoff) pmh7_register_set_bit(0x51, 2); } +void pmh7_trackpoint_enable(int onoff) +{ + if (onoff) + pmh7_register_clear_bit(0x51, 0); + else + pmh7_register_set_bit(0x51, 0); +} + void pmh7_ultrabay_power_enable(int onoff) { if (onoff) @@ -116,6 +124,10 @@ static void enable_dev(device_t dev) if (get_option(&val, "touchpad") != CB_SUCCESS) val = 1; pmh7_touchpad_enable(val); + + if (get_option(&val, "trackpoint") != CB_SUCCESS) + val = 1; + pmh7_trackpoint_enable(val); } struct chip_operations ec_lenovo_pmh7_ops = { diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index 6e13b17..4cd9535 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -35,4 +35,5 @@ void pmh7_backlight_enable(int onoff); void pmh7_dock_event_enable(int onoff); void pmh7_touchpad_enable(int onoff); void pmh7_ultrabay_power_enable(int onoff); +void pmh7_trackpoint_enable(int onoff); #endif diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index d5f3dbf..7d65c97 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -113,6 +113,7 @@ entries 1063 1 e 1 wlan 1064 8 h 0 volume 1072 1 e 9 first_battery +1073 1 e 1 trackpoint # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index a6d8ed1..b04bb1c 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -10,3 +10,4 @@ bluetooth=Enable wwan=Enable wlan=Enable touchpad=Enable +trackpoint=Enable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index db58edf..2836403 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -91,7 +91,8 @@ entries 413 1 e 1 wwan 414 1 e 1 touchpad 415 1 e 1 wlan -#416 568 r 0 unused +416 1 e 1 trackpoint +#417 567 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 96d0922..33df716 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -13,4 +13,5 @@ tft_brightness=0xff first_battery=Primary bluetooth=Enable wlan=Enable -wwan=Enable \ No newline at end of file +wwan=Enable +trackpoint=Enable diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 13df7a5..69178a4 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -113,6 +113,7 @@ entries 1081 1 e 1 bluetooth 1082 1 e 1 wwan 1083 1 e 1 wlan +1084 1 e 1 trackpoint # ----------------------------------------------------------------- enumerations

1 0

Patch set updated for coreboot: 6f29a19 ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4651 -gerrit commit 6f29a19297583b8b4f02208e8965be668fdf58df Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:42:09 2014 +0100 ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree. wwan_enable was never used. wlan_enable isn't something for device tree but for CMOS config if at all. Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/chip.h | 2 -- src/ec/lenovo/h8/h8.c | 2 +- src/mainboard/lenovo/t60/devicetree.cb | 1 - src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/lenovo/x60/devicetree.cb | 1 - 5 files changed, 1 insertion(+), 6 deletions(-) diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 6cb2f9b..58313d4 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -48,7 +48,5 @@ struct ec_lenovo_h8_config { u8 eventf_enable; u8 trackpoint_enable; - u8 wlan_enable; - u8 wwan_enable; }; #endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 4f9d228..c25903a 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -174,7 +174,7 @@ static void h8_enable(device_t dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - h8_wlan_enable(conf->wlan_enable); + h8_wlan_enable(1); h8_trackpoint_enable(conf->trackpoint_enable); h8_usb_power_enable(1); diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 3973f3b..57b9df4 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -143,7 +143,6 @@ chip northbridge/intel/i945 register "eventd_enable" = "0xff" register "eventc_enable" = "0x3c" - register "wlan_enable" = "0x01" register "trackpoint_enable" = "0x03" end diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..c06056b 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -73,7 +73,6 @@ chip northbridge/intel/nehalem register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - register "wlan_enable" = "0x01" register "trackpoint_enable" = "0x03" end diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 91daf3a..d6e09bf 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -121,7 +121,6 @@ chip northbridge/intel/i945 register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - register "wlan_enable" = "0x01" register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382

1 0

Patch set updated for coreboot: 5914c4d ec/lenovo/h8: make wlan CMOS option
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4652 -gerrit commit 5914c4dda7ea286f6ee8f1455e50339fe3c13756 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:45:53 2014 +0100 ec/lenovo/h8: make wlan CMOS option To stay in line with wwan and bluetooth. Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/h8.c | 6 +++++- src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 3 ++- src/mainboard/lenovo/x60/cmos.default | 2 ++ src/mainboard/lenovo/x60/cmos.layout | 1 + 6 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index c25903a..8b0ca20 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -174,7 +174,11 @@ static void h8_enable(device_t dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - h8_wlan_enable(1); + + if (get_option(&val, "wlan") != CB_SUCCESS) + val = 1; + h8_wlan_enable(val); + h8_trackpoint_enable(conf->trackpoint_enable); h8_usb_power_enable(1); diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index a179752..d5f3dbf 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -110,6 +110,7 @@ entries 1060 1 e 1 touchpad 1061 1 e 1 bluetooth 1062 1 e 1 wwan +1063 1 e 1 wlan 1064 8 h 0 volume 1072 1 e 9 first_battery # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..a6d8ed1 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -8,4 +8,5 @@ volume=0x3 first_battery=Primary bluetooth=Enable wwan=Enable +wlan=Enable touchpad=Enable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..db58edf 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +415 1 e 1 wlan +#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 5d82ff0..96d0922 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -12,3 +12,5 @@ volume=0x3 tft_brightness=0xff first_battery=Primary bluetooth=Enable +wlan=Enable +wwan=Enable \ No newline at end of file diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 45bb95a..13df7a5 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -112,6 +112,7 @@ entries 1080 1 e 9 first_battery 1081 1 e 1 bluetooth 1082 1 e 1 wwan +1083 1 e 1 wlan # ----------------------------------------------------------------- enumerations

1 0

Patch set updated for coreboot: d64cca8 ec/lenovo/h8: Remove trackpoint_enable from device tree.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4653 -gerrit commit d64cca81ede9d34bdc2f406889603a8b8b51ba01 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 04:18:52 2014 +0100 ec/lenovo/h8: Remove trackpoint_enable from device tree. Change-Id: I6652e0ad4e0179950f775bbd0200484907bfc976 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/chip.h | 2 -- src/ec/lenovo/h8/h8.c | 2 +- src/mainboard/lenovo/t60/devicetree.cb | 2 -- src/mainboard/lenovo/x201/devicetree.cb | 2 -- src/mainboard/lenovo/x60/devicetree.cb | 2 -- 5 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 58313d4..3382b47 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -46,7 +46,5 @@ struct ec_lenovo_h8_config { u8 eventd_enable; u8 evente_enable; u8 eventf_enable; - - u8 trackpoint_enable; }; #endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 8b0ca20..090acf2 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -179,7 +179,7 @@ static void h8_enable(device_t dev) val = 1; h8_wlan_enable(val); - h8_trackpoint_enable(conf->trackpoint_enable); + h8_trackpoint_enable(1); h8_usb_power_enable(1); if (get_option(&val, "volume") == CB_SUCCESS) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 57b9df4..0b9992a 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -143,8 +143,6 @@ chip northbridge/intel/i945 register "eventd_enable" = "0xff" register "eventc_enable" = "0x3c" - register "trackpoint_enable" = "0x03" - end chip superio/nsc/pc87382 device pnp 164e.2 on # IR diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index c06056b..4e55961 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -72,8 +72,6 @@ chip northbridge/intel/nehalem register "eventb_enable" = "0xff" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - - register "trackpoint_enable" = "0x03" end device cpu_cluster 0 on diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index d6e09bf..886129f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -120,8 +120,6 @@ chip northbridge/intel/i945 register "eventb_enable" = "0xff" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - - register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR

1 0

New patch to review for coreboot: a04e9a8 sandybridge/nehalem: Determine mrc.cache size from CBFS rather than hardcoding
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4659 -gerrit commit a04e9a8b34f329271f915675b8c303c1e150b8de Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 07:52:17 2014 +0100 sandybridge/nehalem: Determine mrc.cache size from CBFS rather than hardcoding The hardcoded value was 0 on X201. There shouldn't be hardcoding at all, hence this patch. Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/mrccache.c | 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index b8120a8..7ea0a5b 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -66,16 +66,30 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; #if CONFIG_CHROMEOS - region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else - region_size = CONFIG_MRC_CACHE_SIZE; - *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", 0xac); -#endif + struct cbfs_file *file; + + *mrc_region_ptr = NULL; + file = cbfs_get_file(CBFS_DEFAULT_MEDIA, + "mrc.cache"); + + if (file == NULL) { + printk(BIOS_ERR, "Could not find file '%s'.\n", "mrc.cache"); + return 0; + } - return region_size; + if (ntohl(file->type) != 0xac) { + printk(BIOS_ERR, + "File '%s' is of type %x, but we requested %x.\n", + "mrc.cache", + ntohl(file->type), 0xac); + return 0; + } + *mrc_region_ptr = (void *)CBFS_SUBHEADER(file); + return ntohl(file->len); +#endif } /*

1 0

Patch set updated for coreboot: 3ac6467 ibexpeak: Fix timings for IDE mode.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4657 -gerrit commit 3ac6467b73cbf9494bd593310d93b2b9ec4369d0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:40:08 2014 +0100 ibexpeak: Fix timings for IDE mode. Change-Id: I3c89bb633c32a2c2db349cb4fcbe1ed1c8deb5af Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/sata.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 9f96d49..d30fae2 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -75,16 +75,14 @@ static void sata_init(struct device *dev) pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + pci_write_config16(dev, IDE_SDMA_CNT, 0); + pci_write_config16(dev, IDE_SDMA_TIM, 0); /* Set IDE I/O Configuration */ - reg32 = - SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ @@ -181,19 +179,16 @@ static void sata_init(struct device *dev) /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_SITRE | IDE_ISP_3_CLOCKS | - IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + pci_write_config16(dev, IDE_SDMA_CNT, 0); + pci_write_config16(dev, IDE_SDMA_TIM, 0); /* Set IDE I/O Configuration */ - reg32 = - SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + reg32 = SIG_MODE_PRI_NORMAL; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2014