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Patch set updated for coreboot: ca30b3e ibexpeak / bd82x6x: Make SATA mode user-visible option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4658 -gerrit commit ca30b3e9e11b28ced7987e94e1f784ba5f85b366 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 07:46:50 2014 +0100 ibexpeak / bd82x6x: Make SATA mode user-visible option. Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/cmos.layout | 3 ++ src/mainboard/google/link/cmos.layout | 3 ++ src/mainboard/google/link/devicetree.cb | 2 - src/mainboard/google/parrot/cmos.layout | 3 ++ src/mainboard/google/parrot/devicetree.cb | 2 - src/mainboard/google/stout/cmos.layout | 3 ++ src/mainboard/google/stout/devicetree.cb | 2 - src/mainboard/intel/cougar_canyon2/cmos.layout | 3 ++ src/mainboard/intel/cougar_canyon2/devicetree.cb | 2 - src/mainboard/intel/emeraldlake2/cmos.layout | 3 ++ src/mainboard/intel/emeraldlake2/devicetree.cb | 2 - src/mainboard/kontron/ktqm77/cmos.layout | 5 ++- src/mainboard/kontron/ktqm77/devicetree.cb | 2 - src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 5 ++- src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/samsung/lumpy/cmos.layout | 3 ++ src/mainboard/samsung/lumpy/devicetree.cb | 2 - src/mainboard/samsung/stumpy/cmos.layout | 3 ++ src/mainboard/samsung/stumpy/devicetree.cb | 2 - src/southbridge/intel/bd82x6x/chip.h | 2 - src/southbridge/intel/bd82x6x/sata.c | 51 ++++++------------------ src/southbridge/intel/ibexpeak/sata.c | 51 ++++++------------------ 23 files changed, 59 insertions(+), 97 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624..a40e66e 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -132,6 +133,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 15f420d..8f0ed3c 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi7_routing" = "2" register "gpi8_routing" = "1" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_port0_gen3_tx" = "0x00880a7f" diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf..59586cc 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge register "gpi8_routing" = "1" register "gpi15_routing" = "1" #lid switch gpe - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 6e02020..653d3fe 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi6_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s register "sata_interface_speed_support" = "0x2" diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index e66574e..c499a56 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/fsp_sandybridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" device pci 14.0 on end # XHCI diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0bb42d6..0d81502 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -50,8 +50,6 @@ chip northbridge/intel/sandybridge register "alt_gp_smi_en" = "0x0002" register "gpe0_en" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 47cd60f..5c17a59 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +410 1 e 11 sata_mode +#412 4 r 0 unused # coreboot config options: additional mainboard options 416 4 e 10 systemp_type @@ -162,6 +163,8 @@ enumerations 10 2 LM75@90 10 3 GPIO16 10 4 LM75@9e +11 0 AHCI +11 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 65c03c4..f6390ac 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -36,8 +36,6 @@ chip northbridge/intel/sandybridge register "pirqg_routing" = "0x8b" register "pirqh_routing" = "0x8b" - register "ide_legacy_combined" = "0x0" # TODO: Does nothing since generations, remove from sb code? - register "sata_ahci" = "0x1" # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..858f203 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -9,3 +9,4 @@ first_battery=Primary bluetooth=Enable wwan=Enable touchpad=Enable +sata_mode=AHCI diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..9e9942e 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +417 1 e 9 sata_mode +#418 566 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -129,6 +130,8 @@ enumerations 7 2 Keep 8 0 Secondary 8 1 Primary +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..5549327 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -107,7 +107,6 @@ chip northbridge/intel/nehalem register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x33" register "gpe0_en" = "0x20022046" diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9552021..a14a8de 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..69729d7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi7_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xa00-0xa3f diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index 6d2ac45..e506295 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -84,6 +84,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ee01e8a..ab03c79 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -49,8 +49,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "0" register "gpi14_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # SuperIO range is 0x700-0x73f diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 828466c..0f2f0e9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -64,8 +64,6 @@ struct southbridge_intel_bd82x6x_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..5d5fdbd 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -45,6 +46,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -53,48 +55,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + /* AHCI */ + if (sata_mode == 0) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -156,6 +126,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -244,15 +215,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d30fae2..bf884aa 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -46,6 +47,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -54,48 +56,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); - } else if (config->sata_ahci) { + if (sata_mode == 0) { + /* AHCI */ u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -158,6 +128,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -245,15 +216,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8;

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New patch to review for coreboot: 992eac2 ibexpeak / bd82x6x: Make SATA mode user-visible option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4658 -gerrit commit 992eac2c5d167754e78b9999eae98c553998e2f0 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 07:46:50 2014 +0100 ibexpeak / bd82x6x: Make SATA mode user-visible option. Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/cmos.layout | 3 ++ src/mainboard/google/link/cmos.layout | 3 ++ src/mainboard/google/link/devicetree.cb | 2 - src/mainboard/google/parrot/cmos.layout | 3 ++ src/mainboard/google/parrot/devicetree.cb | 2 - src/mainboard/google/stout/cmos.layout | 3 ++ src/mainboard/google/stout/devicetree.cb | 2 - src/mainboard/intel/cougar_canyon2/cmos.layout | 3 ++ src/mainboard/intel/cougar_canyon2/devicetree.cb | 2 - src/mainboard/intel/emeraldlake2/cmos.layout | 3 ++ src/mainboard/intel/emeraldlake2/devicetree.cb | 2 - src/mainboard/kontron/ktqm77/cmos.layout | 5 ++- src/mainboard/kontron/ktqm77/devicetree.cb | 2 - src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 5 ++- src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/samsung/lumpy/cmos.layout | 3 ++ src/mainboard/samsung/lumpy/devicetree.cb | 2 - src/mainboard/samsung/stumpy/cmos.layout | 3 ++ src/mainboard/samsung/stumpy/devicetree.cb | 2 - src/southbridge/intel/bd82x6x/chip.h | 2 - src/southbridge/intel/bd82x6x/sata.c | 51 ++++++------------------ src/southbridge/intel/ibexpeak/sata.c | 51 ++++++------------------ 23 files changed, 59 insertions(+), 97 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624..a40e66e 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -132,6 +133,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 15f420d..8f0ed3c 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi7_routing" = "2" register "gpi8_routing" = "1" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_port0_gen3_tx" = "0x00880a7f" diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf..59586cc 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge register "gpi8_routing" = "1" register "gpi15_routing" = "1" #lid switch gpe - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 6e02020..653d3fe 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi6_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s register "sata_interface_speed_support" = "0x2" diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index e66574e..c499a56 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/fsp_sandybridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" device pci 14.0 on end # XHCI diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index afdd3c6..17d205c 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0bb42d6..0d81502 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -50,8 +50,6 @@ chip northbridge/intel/sandybridge register "alt_gp_smi_en" = "0x0002" register "gpe0_en" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 47cd60f..5c17a59 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +410 1 e 11 sata_mode +#412 4 r 0 unused # coreboot config options: additional mainboard options 416 4 e 10 systemp_type @@ -162,6 +163,8 @@ enumerations 10 2 LM75@90 10 3 GPIO16 10 4 LM75@9e +11 0 AHCI +11 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 65c03c4..f6390ac 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -36,8 +36,6 @@ chip northbridge/intel/sandybridge register "pirqg_routing" = "0x8b" register "pirqh_routing" = "0x8b" - register "ide_legacy_combined" = "0x0" # TODO: Does nothing since generations, remove from sb code? - register "sata_ahci" = "0x1" # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..858f203 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -9,3 +9,4 @@ first_battery=Primary bluetooth=Enable wwan=Enable touchpad=Enable +sata_mode=AHCI diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..9e9942e 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +417 1 e 9 sata_mode +#418 566 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -129,6 +130,8 @@ enumerations 7 2 Keep 8 0 Secondary 8 1 Primary +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..5549327 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -107,7 +107,6 @@ chip northbridge/intel/nehalem register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x33" register "gpe0_en" = "0x20022046" diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9552021..a14a8de 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -85,6 +85,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..69729d7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi7_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xa00-0xa3f diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index 6d2ac45..e506295 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -84,6 +84,7 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail +410 1 e 8 sata_mode #411 5 r 0 unused # coreboot config options: bootloader @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ee01e8a..ab03c79 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -49,8 +49,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "0" register "gpi14_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # SuperIO range is 0x700-0x73f diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 828466c..0f2f0e9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -64,8 +64,6 @@ struct southbridge_intel_bd82x6x_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..5d5fdbd 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -45,6 +46,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -53,48 +55,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + /* AHCI */ + if (sata_mode == 0) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -156,6 +126,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -244,15 +215,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d30fae2..bf884aa 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -46,6 +47,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -54,48 +56,16 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); - } else if (config->sata_ahci) { + if (sata_mode == 0) { + /* AHCI */ u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -158,6 +128,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -245,15 +216,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8;

1 0

New patch to review for coreboot: e299369 X201: IDE
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4657 -gerrit commit e2993692f59b00d9a548ca60d4cf703b47287ee1 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:40:08 2014 +0100 X201: IDE Change-Id: I3c89bb633c32a2c2db349cb4fcbe1ed1c8deb5af Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/southbridge/intel/ibexpeak/sata.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index 9f96d49..d30fae2 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -75,16 +75,14 @@ static void sata_init(struct device *dev) pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); + pci_write_config16(dev, IDE_SDMA_CNT, 0); + pci_write_config16(dev, IDE_SDMA_TIM, 0); /* Set IDE I/O Configuration */ - reg32 = - SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */ @@ -181,19 +179,16 @@ static void sata_init(struct device *dev) /* Set timings */ pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_SITRE | IDE_ISP_3_CLOCKS | - IDE_RCT_1_CLOCKS | IDE_IE0 | IDE_TIME0); + IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0 | IDE_PSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0201); + pci_write_config16(dev, IDE_SDMA_CNT, 0); + pci_write_config16(dev, IDE_SDMA_TIM, 0); /* Set IDE I/O Configuration */ - reg32 = - SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; + reg32 = SIG_MODE_PRI_NORMAL; pci_write_config32(dev, IDE_CONFIG, reg32); /* Port enable */

1 0

Patch set updated for coreboot: d4dcdec cpu/allwinner/a10: Provide utility to make a bootable image
by Alexandru Gagniuc 11 Jan '14

11 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4656 -gerrit commit d4dcdec750899f1ec03e0e43f1033f3954f365e8 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 10 23:06:03 2014 -0600 cpu/allwinner/a10: Provide utility to make a bootable image Up until now, we relied on mksunxiboot to prepend the header which makes coreboot.rom bootable on Allwinner SoCs. If that tool was not present, the build silently failed. Integrate this tool into our util/ package, so that we do not have to rely on mksunxiboot being in PATH. Our version of mksunxiboot also eliminates some limitations of the original tool, so we no longer have to use 'dd' to limit the file size. Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 28 ++-- util/arm_boot_tools/mksunxiboot/mksunxiboot.c | 196 ++++++++++++++++++++++++++ 2 files changed, 214 insertions(+), 10 deletions(-) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 03bc612..b115b5f 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -30,16 +30,24 @@ get_bootblock_size= \ sed 's/[^0-9 ]//g')) \ $(shell echo $$(($(word 2, $(strip $(bb_s)))))) +# This tool is used to prepend a header to coreboot.rom to trick the SoC into +# loading out bootblock +# +MKSUNXIBOOT:=$(objutil)/mksunxiboot +$(MKSUNXIBOOT): $(top)/util/arm_boot_tools/mksunxiboot/mksunxiboot.c + @printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + # The boot ROM in the SoC will start loading code if a special BOOT0 header is # found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. This header is normally added by the 'mxsunxiboot' tool. The boot ROM -# will load at most 24KiB of data to SRAM, so limit the file size accordingly. -# The BOOT0 header takes 32 bytes, so limit our file to 24KiB - 32 bytes. -# FIXME: Figure out how to safely integrate in coreboot.rom. -# FIXME: The file passed to mksunxiboot should only include the bootblock due -# to size limitations. -$(obj)/BOOT0: $(obj)/coreboot.rom +# correct. This header is added by the 'mxsunxiboot' tool, which is provided +# under util/arm_boot_tools/mksunxiboot. The boot ROM will load at most 24KiB of +# data to SRAM. The BOOT0 header takes 32 bytes, so limit our bootblock is +# linited tp to 24KiB - 32 bytes. +# TODO: make mksunxiboot take the bootblock size as a parameter +# TODO: print an error if bootblock is too large (maybe place ROMSTAGE at the +# exact offset needed to collide with the bootblock) +# +$(obj)/BOOT0: $(obj)/coreboot.rom $(MKSUNXIBOOT) @printf " BOOT0 $(subst $(obj)/,,$(^))\n" - touch $@ - dd if=$^ of=$^.tmp bs=24544 count=1 - -mksunxiboot $^.tmp $@ + $(MKSUNXIBOOT) $(word 1, $^) $@ diff --git a/util/arm_boot_tools/mksunxiboot/mksunxiboot.c b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c new file mode 100644 index 0000000..6a38fa3 --- /dev/null +++ b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c @@ -0,0 +1,196 @@ +/* + * A simple tool to generate bootable image for sunxi platform. + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <errno.h> + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + uint32_t jump_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + uint32_t check_sum; /* generated by PC */ + uint32_t length; /* generated by PC */ + /* We use a simplified header, only filling in what is needed by the + * boot ROM. To be compatible with Allwinner tools the larger header + * below should be used, followed by a custom header if desired. */ + uint8_t pad[12]; /* align to 32 bytes */ +}; + +static const char *BOOT0_MAGIC = "eGON.BT0"; +static const uint32_t STAMP_VALUE = 0x5F0A6C39; +static const int HEADER_SIZE = 32; +/* Checksum at most 24 KiB */ +#define SRAM_LOAD_MAX_SIZE ((24 << 10) - sizeof(struct boot_file_head)) +static const int BLOCK_SIZE = 512; + +inline static uint32_t le32_to_h(const void *src) +{ + const uint8_t *b = src; + return ((b[3] << 24) | (b[2] << 16) | (b[1] << 8) | (b[0] << 0)); +} + +inline static void h_to_le32(uint32_t val32, void *dest) +{ + uint8_t *b = dest; + b[0] = (val32 >> 0) & 0xff; + b[1] = (val32 >> 8) & 0xff; + b[2] = (val32 >> 16) & 0xff; + b[3] = (val32 >> 24) & 0xff; +}; + +static void serialize_header(void *dest, const struct boot_file_head *hdr) +{ + /* Unused fields are zero */ + memset(dest, 0, HEADER_SIZE); + + h_to_le32(hdr->jump_instruction, dest + 0); + memcpy(dest + 4, BOOT0_MAGIC, 8); + h_to_le32(hdr->check_sum, dest + 12); + h_to_le32(hdr->length, dest + 16); +} + +/* check sum functon from sun4i boot code */ +static int fill_check_sum(struct boot_file_head *hdr, const void *boot_code) +{ + size_t i; + uint8_t raw_hdr[HEADER_SIZE]; + uint32_t chksum; + + if ((hdr->length & 0x3) != 0) { + fprintf(stderr, "BUG! Load size is not 4-byte aligned\n"); + return EXIT_FAILURE; + } + + /* Fill in checksum seed */ + hdr->check_sum = STAMP_VALUE; + + chksum = 0; + /* Checksum the header */ + serialize_header(raw_hdr, hdr); + for (i = 0; i < HEADER_SIZE; i += 4) + chksum += le32_to_h(raw_hdr + i); + + /* Checksum the boot code */ + for (i = 0; i < hdr->length - HEADER_SIZE; i += 4) + chksum += le32_to_h(boot_code + i); + + /* write back check sum */ + hdr->check_sum = chksum; + + return EXIT_SUCCESS; +} + +static uint32_t align(uint32_t size, uint32_t alignment) +{ + return ((size + alignment - 1) / alignment) * alignment; +} + +static void fill_header(struct boot_file_head *hdr, size_t load_size) +{ + /* b instruction */ + hdr->jump_instruction = 0xEA000000; + /* jump to the first instr after the header */ + hdr->jump_instruction |= (sizeof(*hdr) / sizeof(uint32_t) - 2); + /* no '0' termination in magic string */ + memcpy(&hdr->magic, BOOT0_MAGIC, 8); + + hdr->length = align(load_size + sizeof(hdr), BLOCK_SIZE); +} + +static long int fsize(FILE *file) +{ + long int size; + + fseek(file, 0L, SEEK_END); + size = ftell(file); + fseek(file, 0L, SEEK_SET); + return size; +} + +int main(int argc, char *argv[]) +{ + FILE *fd_in, *fd_out; + struct boot_file_head hdr; + long int file_size, load_size; + void *file_data; + uint8_t raw_hdr[HEADER_SIZE]; + int count; + + /* + * TODO: We could take an additional argument to see how much of the + * file to checksum. This way, the build system can tell us how large + * the bootblock is, and we can only checksum the BROM. + */ + if (argc < 2) { + printf("\tThis program makes an input bin file to sun4i " + "bootable image.\n" + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = fopen(argv[1], "r"); + if (!fd_in) { + fprintf(stderr, "Cannot open input %s", argv[1]); + return EXIT_FAILURE; + } + + /* get input file size */ + file_size = fsize(fd_in); + if ((file_data = malloc(file_size)) == NULL) { + fprintf(stderr, "Cannot allocate memory\n"); + return EXIT_FAILURE; + } + + printf("File size: 0x%x\n", file_size); + if (fread(file_data, file_size, 1, fd_in) != 1) { + fprintf(stderr, "Cannot read %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + load_size = align(file_size, sizeof(uint32_t)); + + if (load_size > SRAM_LOAD_MAX_SIZE) + load_size = SRAM_LOAD_MAX_SIZE; + + printf("Load size: 0x%x\n", load_size); + + fd_out = fopen(argv[2], "w"); + if (!fd_out) { + fprintf(stderr, "Cannot open output %s\n", argv[2]); + return EXIT_FAILURE; + } + + /* fill the header */ + fill_header(&hdr, load_size); + fill_check_sum(&hdr, file_data); + + /* Now write the header */ + serialize_header(raw_hdr, &hdr); + if (fwrite(raw_hdr, HEADER_SIZE, 1, fd_out) != 1) { + fprintf(stderr, "Cannot write header to %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + /* And finally, the boot code */ + if (fwrite(file_data, file_size, 1, fd_out) != 1) { + fprintf(stderr, "Cannot write to %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + fclose(fd_in); + fclose(fd_out); + + return EXIT_SUCCESS; +}

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New patch to review for coreboot: ff745a7 cpu/allwinner/a10: Provide utility to make a bootable image
by Alexandru Gagniuc 11 Jan '14

11 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4656 -gerrit commit ff745a7889cfac0c839ed26f4046a288cd98b573 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 10 23:06:03 2014 -0600 cpu/allwinner/a10: Provide utility to make a bootable image Up until now, we relied on mksunxiboot to prepend the header which makes coreboot.rom bootable on Allwinner SoCs. If that tool was not present, the build silently failed. Integrate this tool into our util/ package, so that we do not have to rely on mksunxiboot being in PATH. Our version of mksunxiboot also eliminates some limitations of the original tool, so we no longer have to use 'dd' to limit the file size. Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 32 +++-- util/arm_boot_tools/mksunxiboot/mksunxiboot.c | 196 ++++++++++++++++++++++++++ 2 files changed, 218 insertions(+), 10 deletions(-) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 03bc612..cc6c699 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,6 +1,7 @@ bootblock-y += bootblock_media.c bootblock-y += clock.c bootblock-y += gpio.c +bootblock-y += mmc.c bootblock-y += pinmux.c bootblock-y += raminit.c bootblock-y += timer.c @@ -9,6 +10,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c romstage-y += bootblock_media.c romstage-y += clock.c +romstage-y += mmc.c romstage-y += pinmux.c romstage-y += timer.c romstage-y += twi.c @@ -17,6 +19,8 @@ romstage-y += uart_console.c ramstage-y += bootblock_media.c ramstage-y += clock.c +ramstage-y += cpu.c +ramstage-y += mmc.c ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c @@ -30,16 +34,24 @@ get_bootblock_size= \ sed 's/[^0-9 ]//g')) \ $(shell echo $$(($(word 2, $(strip $(bb_s)))))) +# This tool is used to prepend a header to coreboot.rom to trick the SoC into +# loading out bootblock +# +MKSUNXIBOOT:=$(objutil)/mksunxiboot +$(MKSUNXIBOOT): $(top)/util/arm_boot_tools/mksunxiboot/mksunxiboot.c + @printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + # The boot ROM in the SoC will start loading code if a special BOOT0 header is # found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. This header is normally added by the 'mxsunxiboot' tool. The boot ROM -# will load at most 24KiB of data to SRAM, so limit the file size accordingly. -# The BOOT0 header takes 32 bytes, so limit our file to 24KiB - 32 bytes. -# FIXME: Figure out how to safely integrate in coreboot.rom. -# FIXME: The file passed to mksunxiboot should only include the bootblock due -# to size limitations. -$(obj)/BOOT0: $(obj)/coreboot.rom +# correct. This header is added by the 'mxsunxiboot' tool, which is provided +# under util/arm_boot_tools/mksunxiboot. The boot ROM will load at most 24KiB of +# data to SRAM. The BOOT0 header takes 32 bytes, so limit our bootblock is +# linited tp to 24KiB - 32 bytes. +# TODO: make mksunxiboot take the bootblock size as a parameter +# TODO: print an error if bootblock is too large (maybe place ROMSTAGE at the +# exact offset needed to collide with the bootblock) +# +$(obj)/BOOT0: $(obj)/coreboot.rom $(MKSUNXIBOOT) @printf " BOOT0 $(subst $(obj)/,,$(^))\n" - touch $@ - dd if=$^ of=$^.tmp bs=24544 count=1 - -mksunxiboot $^.tmp $@ + $(MKSUNXIBOOT) $(word 1, $^) $@ diff --git a/util/arm_boot_tools/mksunxiboot/mksunxiboot.c b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c new file mode 100644 index 0000000..6a38fa3 --- /dev/null +++ b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c @@ -0,0 +1,196 @@ +/* + * A simple tool to generate bootable image for sunxi platform. + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <errno.h> + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + uint32_t jump_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + uint32_t check_sum; /* generated by PC */ + uint32_t length; /* generated by PC */ + /* We use a simplified header, only filling in what is needed by the + * boot ROM. To be compatible with Allwinner tools the larger header + * below should be used, followed by a custom header if desired. */ + uint8_t pad[12]; /* align to 32 bytes */ +}; + +static const char *BOOT0_MAGIC = "eGON.BT0"; +static const uint32_t STAMP_VALUE = 0x5F0A6C39; +static const int HEADER_SIZE = 32; +/* Checksum at most 24 KiB */ +#define SRAM_LOAD_MAX_SIZE ((24 << 10) - sizeof(struct boot_file_head)) +static const int BLOCK_SIZE = 512; + +inline static uint32_t le32_to_h(const void *src) +{ + const uint8_t *b = src; + return ((b[3] << 24) | (b[2] << 16) | (b[1] << 8) | (b[0] << 0)); +} + +inline static void h_to_le32(uint32_t val32, void *dest) +{ + uint8_t *b = dest; + b[0] = (val32 >> 0) & 0xff; + b[1] = (val32 >> 8) & 0xff; + b[2] = (val32 >> 16) & 0xff; + b[3] = (val32 >> 24) & 0xff; +}; + +static void serialize_header(void *dest, const struct boot_file_head *hdr) +{ + /* Unused fields are zero */ + memset(dest, 0, HEADER_SIZE); + + h_to_le32(hdr->jump_instruction, dest + 0); + memcpy(dest + 4, BOOT0_MAGIC, 8); + h_to_le32(hdr->check_sum, dest + 12); + h_to_le32(hdr->length, dest + 16); +} + +/* check sum functon from sun4i boot code */ +static int fill_check_sum(struct boot_file_head *hdr, const void *boot_code) +{ + size_t i; + uint8_t raw_hdr[HEADER_SIZE]; + uint32_t chksum; + + if ((hdr->length & 0x3) != 0) { + fprintf(stderr, "BUG! Load size is not 4-byte aligned\n"); + return EXIT_FAILURE; + } + + /* Fill in checksum seed */ + hdr->check_sum = STAMP_VALUE; + + chksum = 0; + /* Checksum the header */ + serialize_header(raw_hdr, hdr); + for (i = 0; i < HEADER_SIZE; i += 4) + chksum += le32_to_h(raw_hdr + i); + + /* Checksum the boot code */ + for (i = 0; i < hdr->length - HEADER_SIZE; i += 4) + chksum += le32_to_h(boot_code + i); + + /* write back check sum */ + hdr->check_sum = chksum; + + return EXIT_SUCCESS; +} + +static uint32_t align(uint32_t size, uint32_t alignment) +{ + return ((size + alignment - 1) / alignment) * alignment; +} + +static void fill_header(struct boot_file_head *hdr, size_t load_size) +{ + /* b instruction */ + hdr->jump_instruction = 0xEA000000; + /* jump to the first instr after the header */ + hdr->jump_instruction |= (sizeof(*hdr) / sizeof(uint32_t) - 2); + /* no '0' termination in magic string */ + memcpy(&hdr->magic, BOOT0_MAGIC, 8); + + hdr->length = align(load_size + sizeof(hdr), BLOCK_SIZE); +} + +static long int fsize(FILE *file) +{ + long int size; + + fseek(file, 0L, SEEK_END); + size = ftell(file); + fseek(file, 0L, SEEK_SET); + return size; +} + +int main(int argc, char *argv[]) +{ + FILE *fd_in, *fd_out; + struct boot_file_head hdr; + long int file_size, load_size; + void *file_data; + uint8_t raw_hdr[HEADER_SIZE]; + int count; + + /* + * TODO: We could take an additional argument to see how much of the + * file to checksum. This way, the build system can tell us how large + * the bootblock is, and we can only checksum the BROM. + */ + if (argc < 2) { + printf("\tThis program makes an input bin file to sun4i " + "bootable image.\n" + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = fopen(argv[1], "r"); + if (!fd_in) { + fprintf(stderr, "Cannot open input %s", argv[1]); + return EXIT_FAILURE; + } + + /* get input file size */ + file_size = fsize(fd_in); + if ((file_data = malloc(file_size)) == NULL) { + fprintf(stderr, "Cannot allocate memory\n"); + return EXIT_FAILURE; + } + + printf("File size: 0x%x\n", file_size); + if (fread(file_data, file_size, 1, fd_in) != 1) { + fprintf(stderr, "Cannot read %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + load_size = align(file_size, sizeof(uint32_t)); + + if (load_size > SRAM_LOAD_MAX_SIZE) + load_size = SRAM_LOAD_MAX_SIZE; + + printf("Load size: 0x%x\n", load_size); + + fd_out = fopen(argv[2], "w"); + if (!fd_out) { + fprintf(stderr, "Cannot open output %s\n", argv[2]); + return EXIT_FAILURE; + } + + /* fill the header */ + fill_header(&hdr, load_size); + fill_check_sum(&hdr, file_data); + + /* Now write the header */ + serialize_header(raw_hdr, &hdr); + if (fwrite(raw_hdr, HEADER_SIZE, 1, fd_out) != 1) { + fprintf(stderr, "Cannot write header to %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + /* And finally, the boot code */ + if (fwrite(file_data, file_size, 1, fd_out) != 1) { + fprintf(stderr, "Cannot write to %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + fclose(fd_in); + fclose(fd_out); + + return EXIT_SUCCESS; +}

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New patch to review for coreboot: dbcb1ce X201: Add missing LPC registers
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4655 -gerrit commit dbcb1ce5de2c2ff203df3afd0f161128fa3ad095 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 05:48:17 2014 +0100 X201: Add missing LPC registers Without them PMH7 is inaccessible from running system. Change-Id: Ib5a524325040e253a9d914906f90263fc208c313 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..eb1c55f 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -112,6 +112,10 @@ chip northbridge/intel/nehalem register "gpe0_en" = "0x20022046" register "alt_gp_smi_en" = "0x0000" + register "gen1_dec" = "0x7c1601" + register "gen2_dec" = "0x0c15e1" + register "gen3_dec" = "0x1c1681" + register "gen4_dec" = "0x040069" device pci 16.2 on # IDE/SATA subsystemid 0x17aa 0x2161

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Patch set updated for coreboot: 3e1088a H8: Make trackpoint enable a CMOS option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4654 -gerrit commit 3e1088a1d526eacfa9624ea14fc57ce46cd3a1de Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 04:22:35 2014 +0100 H8: Make trackpoint enable a CMOS option. To be consistent with touchpad counterpart. Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/pmh7/pmh7.c | 12 ++++++++++++ src/ec/lenovo/pmh7/pmh7.h | 1 + src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 3 ++- src/mainboard/lenovo/x60/cmos.default | 3 ++- src/mainboard/lenovo/x60/cmos.layout | 1 + 7 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/pmh7/pmh7.c b/src/ec/lenovo/pmh7/pmh7.c index 9607c83..a4d0ccc 100644 --- a/src/ec/lenovo/pmh7/pmh7.c +++ b/src/ec/lenovo/pmh7/pmh7.c @@ -55,6 +55,14 @@ void pmh7_touchpad_enable(int onoff) pmh7_register_set_bit(0x51, 2); } +void pmh7_trackpoint_enable(int onoff) +{ + if (onoff) + pmh7_register_clear_bit(0x51, 0); + else + pmh7_register_set_bit(0x51, 0); +} + void pmh7_ultrabay_power_enable(int onoff) { if (onoff) @@ -116,6 +124,10 @@ static void enable_dev(device_t dev) if (get_option(&val, "touchpad") != CB_SUCCESS) val = 1; pmh7_touchpad_enable(val); + + if (get_option(&val, "trackpoint") != CB_SUCCESS) + val = 1; + pmh7_trackpoint_enable(val); } struct chip_operations ec_lenovo_pmh7_ops = { diff --git a/src/ec/lenovo/pmh7/pmh7.h b/src/ec/lenovo/pmh7/pmh7.h index 6e13b17..4cd9535 100644 --- a/src/ec/lenovo/pmh7/pmh7.h +++ b/src/ec/lenovo/pmh7/pmh7.h @@ -35,4 +35,5 @@ void pmh7_backlight_enable(int onoff); void pmh7_dock_event_enable(int onoff); void pmh7_touchpad_enable(int onoff); void pmh7_ultrabay_power_enable(int onoff); +void pmh7_trackpoint_enable(int onoff); #endif diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index d5f3dbf..7d65c97 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -113,6 +113,7 @@ entries 1063 1 e 1 wlan 1064 8 h 0 volume 1072 1 e 9 first_battery +1073 1 e 1 trackpoint # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index a6d8ed1..b04bb1c 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -10,3 +10,4 @@ bluetooth=Enable wwan=Enable wlan=Enable touchpad=Enable +trackpoint=Enable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index db58edf..2836403 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -91,7 +91,8 @@ entries 413 1 e 1 wwan 414 1 e 1 touchpad 415 1 e 1 wlan -#416 568 r 0 unused +416 1 e 1 trackpoint +#417 567 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 96d0922..33df716 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -13,4 +13,5 @@ tft_brightness=0xff first_battery=Primary bluetooth=Enable wlan=Enable -wwan=Enable \ No newline at end of file +wwan=Enable +trackpoint=Enable diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 13df7a5..69178a4 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -113,6 +113,7 @@ entries 1081 1 e 1 bluetooth 1082 1 e 1 wwan 1083 1 e 1 wlan +1084 1 e 1 trackpoint # ----------------------------------------------------------------- enumerations

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New patch to review for coreboot: 1f15270 H8: Make trackpoint enable a CMOS option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4654 -gerrit commit 1f152706fb3eca393ea9d96824e8c4a7c09bef87 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 04:22:35 2014 +0100 H8: Make trackpoint enable a CMOS option. To be consistent with touchpad counterpart. Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/h8.c | 5 ++++- src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 3 ++- src/mainboard/lenovo/x60/cmos.default | 3 ++- src/mainboard/lenovo/x60/cmos.layout | 1 + 6 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 090acf2..ece0d45 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -179,7 +179,10 @@ static void h8_enable(device_t dev) val = 1; h8_wlan_enable(val); - h8_trackpoint_enable(1); + if (get_option(&val, "trackpoint") != CB_SUCCESS) + val = 1; + h8_trackpoint_enable(val); + h8_usb_power_enable(1); if (get_option(&val, "volume") == CB_SUCCESS) diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index d5f3dbf..7d65c97 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -113,6 +113,7 @@ entries 1063 1 e 1 wlan 1064 8 h 0 volume 1072 1 e 9 first_battery +1073 1 e 1 trackpoint # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index a6d8ed1..b04bb1c 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -10,3 +10,4 @@ bluetooth=Enable wwan=Enable wlan=Enable touchpad=Enable +trackpoint=Enable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index db58edf..2836403 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -91,7 +91,8 @@ entries 413 1 e 1 wwan 414 1 e 1 touchpad 415 1 e 1 wlan -#416 568 r 0 unused +416 1 e 1 trackpoint +#417 567 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 96d0922..33df716 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -13,4 +13,5 @@ tft_brightness=0xff first_battery=Primary bluetooth=Enable wlan=Enable -wwan=Enable \ No newline at end of file +wwan=Enable +trackpoint=Enable diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 13df7a5..69178a4 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -113,6 +113,7 @@ entries 1081 1 e 1 bluetooth 1082 1 e 1 wwan 1083 1 e 1 wlan +1084 1 e 1 trackpoint # ----------------------------------------------------------------- enumerations

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New patch to review for coreboot: 156f67d H8: Remove trackpoint_enable from device tree.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4653 -gerrit commit 156f67d9dc18b445c50ae4cd798ed130b6a57266 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 04:18:52 2014 +0100 H8: Remove trackpoint_enable from device tree. Change-Id: I6652e0ad4e0179950f775bbd0200484907bfc976 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/chip.h | 2 -- src/ec/lenovo/h8/h8.c | 2 +- src/mainboard/lenovo/t60/devicetree.cb | 2 -- src/mainboard/lenovo/x201/devicetree.cb | 2 -- src/mainboard/lenovo/x60/devicetree.cb | 2 -- 5 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/ec/lenovo/h8/chip.h b/src/ec/lenovo/h8/chip.h index 58313d4..3382b47 100644 --- a/src/ec/lenovo/h8/chip.h +++ b/src/ec/lenovo/h8/chip.h @@ -46,7 +46,5 @@ struct ec_lenovo_h8_config { u8 eventd_enable; u8 evente_enable; u8 eventf_enable; - - u8 trackpoint_enable; }; #endif diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index 8b0ca20..090acf2 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -179,7 +179,7 @@ static void h8_enable(device_t dev) val = 1; h8_wlan_enable(val); - h8_trackpoint_enable(conf->trackpoint_enable); + h8_trackpoint_enable(1); h8_usb_power_enable(1); if (get_option(&val, "volume") == CB_SUCCESS) diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 57b9df4..0b9992a 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -143,8 +143,6 @@ chip northbridge/intel/i945 register "eventd_enable" = "0xff" register "eventc_enable" = "0x3c" - register "trackpoint_enable" = "0x03" - end chip superio/nsc/pc87382 device pnp 164e.2 on # IR diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index c06056b..4e55961 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -72,8 +72,6 @@ chip northbridge/intel/nehalem register "eventb_enable" = "0xff" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - - register "trackpoint_enable" = "0x03" end device cpu_cluster 0 on diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index d6e09bf..886129f 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -120,8 +120,6 @@ chip northbridge/intel/i945 register "eventb_enable" = "0xff" register "eventc_enable" = "0xff" register "eventd_enable" = "0xff" - - register "trackpoint_enable" = "0x03" end chip superio/nsc/pc87382 device pnp 164e.2 on # IR

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Patch set updated for coreboot: 51dd741 H8: make wlan CMOS option
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4652 -gerrit commit 51dd741106711f2f48fc7a7b21853f2a6d173505 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:45:53 2014 +0100 H8: make wlan CMOS option To stay in line with wwan and bluetooth. Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/h8.c | 6 +++++- src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 3 ++- src/mainboard/lenovo/x60/cmos.default | 2 ++ src/mainboard/lenovo/x60/cmos.layout | 1 + 6 files changed, 12 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index c25903a..8b0ca20 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -174,7 +174,11 @@ static void h8_enable(device_t dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - h8_wlan_enable(1); + + if (get_option(&val, "wlan") != CB_SUCCESS) + val = 1; + h8_wlan_enable(val); + h8_trackpoint_enable(conf->trackpoint_enable); h8_usb_power_enable(1); diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index a179752..d5f3dbf 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -110,6 +110,7 @@ entries 1060 1 e 1 touchpad 1061 1 e 1 bluetooth 1062 1 e 1 wwan +1063 1 e 1 wlan 1064 8 h 0 volume 1072 1 e 9 first_battery # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..a6d8ed1 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -8,4 +8,5 @@ volume=0x3 first_battery=Primary bluetooth=Enable wwan=Enable +wlan=Enable touchpad=Enable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..db58edf 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +415 1 e 1 wlan +#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 5d82ff0..96d0922 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -12,3 +12,5 @@ volume=0x3 tft_brightness=0xff first_battery=Primary bluetooth=Enable +wlan=Enable +wwan=Enable \ No newline at end of file diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 45bb95a..13df7a5 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -112,6 +112,7 @@ entries 1080 1 e 9 first_battery 1081 1 e 1 bluetooth 1082 1 e 1 wwan +1083 1 e 1 wlan # ----------------------------------------------------------------- enumerations

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coreboot-gerrit January 2014