coreboot-gerrit January 2014

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New patch to review for coreboot: bc0fc33 CBMEM: Rename cbmem_reinit()
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4669 -gerrit commit bc0fc33fc27d3b83f2dd0d0c59fd1b30facb257d Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 4 08:46:32 2014 +0200 CBMEM: Rename cbmem_reinit() This function does not really initialize anything, but only checks for the TOC. Change-Id: I9d100d1823a0b630f5d1175e42a6a15f45266de4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 2 -- src/lib/cbmem.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index eff1895..9e894a9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -145,8 +145,6 @@ void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif -int cbmem_reinit(void); - void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 704733f..5fe8216 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -119,7 +119,7 @@ static void cbmem_initialize_empty(void) }; } -int cbmem_reinit(void) +static int cbmem_check_toc(void) { uint64_t baseaddr, size; struct cbmem_entry *cbmem_toc; @@ -220,7 +220,7 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_recovery(int is_wakeup) { - int found = cbmem_reinit(); + int found = cbmem_check_toc(); int wipe = 0; #if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT

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New patch to review for coreboot: e506222 CBMEM: Replace cbmem_initialize() with cbmem_recovery()
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4668 -gerrit commit e506222624f43c5faa542ed214108ddbb5865d46 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 6 17:20:31 2014 +0200 CBMEM: Replace cbmem_initialize() with cbmem_recovery() The replacement function confirms CBMEM region is wiped clean on power cycles and resets. It also introduces compatibility interface to ease up transition to DYNAMIC_CBMEM. Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 9 ++++-- src/lib/cbmem.c | 40 +++++++++++++++------------ src/lib/dynamic_cbmem.c | 10 +++++++ src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/google/butterfly/romstage.c | 2 +- src/mainboard/google/link/romstage.c | 2 +- src/mainboard/google/parrot/romstage.c | 2 +- src/mainboard/google/stout/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 2 +- src/mainboard/kontron/ktqm77/romstage.c | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x201/romstage.c | 6 +++- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/samsung/stumpy/romstage.c | 2 +- src/mainboard/via/epia-m850/romstage.c | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- 22 files changed, 62 insertions(+), 39 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5f1ac3c..eff1895 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -90,6 +90,9 @@ struct cbmem_entry; #define DYN_CBMEM_ALIGN_SIZE (4096) +/* By default cbmem is attempted to be recovered. Returns 0 if cbmem was + * recovered or 1 if cbmem had to be reinitialized. */ +int cbmem_initialize(void); /* Initialize cbmem to be empty. */ void cbmem_initialize_empty(void); @@ -153,9 +156,9 @@ struct cbmem_entry *get_cbmem_toc(void); unsigned long get_top_of_ram(void); -/* By default cbmem is attempted to be recovered. Returns 0 if cbmem was - * recovered or 1 if cbmem had to be reinitialized. */ -int cbmem_initialize(void); +/* Returns 0 if old cbmem was recovered. Recovery is only attempted if + * s3resume is non-zero. */ +int cbmem_recovery(int s3resume); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6cdf772..704733f 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -95,8 +95,7 @@ void cbmem_late_set_table(uint64_t base, uint64_t size) * - suspend/resume backup memory */ -#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) -static void cbmem_init(void) +static void cbmem_initialize_empty(void) { uint64_t baseaddr, size; struct cbmem_entry *cbmem_toc; @@ -119,7 +118,6 @@ static void cbmem_init(void) .size = size - CBMEM_TOC_RESERVED }; } -#endif int cbmem_reinit(void) { @@ -219,32 +217,40 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) /* Returns True if it was not initialized before. */ -int cbmem_initialize(void) +int cbmem_recovery(int is_wakeup) { - int rv = 0; + int found = cbmem_reinit(); + int wipe = 0; + +#if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT + wipe = 1; +#endif +#if !defined(__PRE_RAM__) && !CONFIG_EARLY_CBMEM_INIT + wipe = 1; +#endif + + if (!is_wakeup && wipe) + cbmem_initialize_empty(); - /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit()) { - cbmem_init(); + if (is_wakeup && !found) { + cbmem_initialize_empty(); cbmem_fail_resume(); - rv = 1; } -#ifndef __PRE_RAM__ + cbmem_arch_init(); -#endif - /* Migrate cache-as-ram variables. */ car_migrate_variables(); - - return rv; + return !found; } -#endif #ifndef __PRE_RAM__ static void init_cbmem_post_device(void *unused) { - cbmem_initialize(); +#if CONFIG_HAVE_ACPI_RESUME + cbmem_recovery(acpi_is_wakeup()); +#else + cbmem_recovery(0); +#endif #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 0ab8f81..0cc6295 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -256,6 +256,16 @@ int cbmem_initialize(void) return 0; } +int cbmem_recovery(int is_wakeup) +{ + int rv = 0; + if (!is_wakeup) + cbmem_initialize_empty(); + else + rv = cbmem_initialize(); + return rv; +} + static void *cbmem_base(void) { struct cbmem_root *root; diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 87af8ca..a081a8a 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -357,7 +357,7 @@ void main(unsigned long bist) #endif MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index b9a2ae1..ae645ab 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -244,7 +244,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index dbaf04b..be4a446 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -286,7 +286,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 253e679..4bade16 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -244,7 +244,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 99aa93b..3535fdb 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -296,7 +296,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 222c376..0b9d408 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -311,7 +311,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 42b19e4..77f6a3e 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -322,7 +322,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { quick_ram_check(); post_code(0x4e); - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if(cbmem_was_initted) { reset_system(); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 166743f..69d4232 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -269,7 +269,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index d132642..9a8b420 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -296,7 +296,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 1875a10..549facd 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -410,7 +410,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 9f15401..f720ac2 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -295,7 +295,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 1b7e693..dae917c 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -321,7 +321,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 18645ac..90d31cc 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -331,7 +331,11 @@ void main(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } - cbmem_initted = !cbmem_initialize(); + /* FIXME: If not in s3resume, raminit() calls cbmem_recovery(0), + * clears all of CBMEM region and puts in MRC training results. + * Tell here were are doing resume to avoid wiping CBMEM region + * again. */ + cbmem_initted = !cbmem_recovery(1); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 26a7b9b..1198fb2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -323,7 +323,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e08c1c0..ad323f5 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -346,7 +346,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 8c5d5ac..0f0da0f 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -317,7 +317,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index a96b301..24d3c74 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -324,7 +324,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data) diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 39f4253..262bee7 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -95,7 +95,7 @@ void main(unsigned long bist) /* We got RAM working, now we can write the timestamps to RAM */ #if CONFIG_EARLY_CBMEM_INIT - cbmem_initialize(); + cbmem_recovery(0); #endif timestamp_add_now(TS_END_ROMSTAGE); /* FIXME: See if this is needed or take this out please */ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 19af3bb..c7acd47 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1699,7 +1699,7 @@ static void save_timings(struct raminfo *info) train.reg_10b = read_1d0(0x10b, 6); /* Save the MRC S3 restore data to cbmem */ - cbmem_initialize(); + cbmem_recovery(0); mrcdata = cbmem_add (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container));

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New patch to review for coreboot: 8663e27 lenovo/x201: Really do EARLY_CBMEM_INIT
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4667 -gerrit commit 8663e27a9c1e7491fcb8055b34a7b66f31bec96f Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 6 17:18:58 2014 +0200 lenovo/x201: Really do EARLY_CBMEM_INIT The board was missing cbmem_initialize() call in romstage. Selecting EARLY_CBMEM_INIT implies this is done in romstage. Change-Id: I9ec93f89fe4cbb9e729532be36db601b6e62bca6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8022d7b..18645ac 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -230,6 +230,7 @@ static inline u16 read_acpi16(u32 addr) void main(unsigned long bist) { u32 reg32; + int cbmem_initted; int s3resume = 0; timestamp_init(rdtsc ()); @@ -329,11 +330,14 @@ void main(unsigned long bist) reg32 = inl(DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } + + cbmem_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_reinit()) { + if (s3resume && cbmem_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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New patch to review for coreboot: beef001 Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4666 -gerrit commit beef00122b95f7ec5a5498631d63ea69fb6a9325 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 4 11:02:45 2014 +0200 Intel (sandy/ivy): Avoid calling cbmem_initialize() twice Delay the copying of MRC cache data from CAR to CBMEM until after sdram_initialize() returns and cbmem_initialize() completes. Calling cbmem_initialize() twice would complicate the decision logic of when CBMEM area needs to be wiped clean. Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/romstage.c | 2 ++ src/mainboard/google/link/romstage.c | 2 ++ src/mainboard/google/parrot/romstage.c | 2 ++ src/mainboard/google/stout/romstage.c | 2 ++ src/mainboard/intel/emeraldlake2/romstage.c | 2 ++ src/mainboard/kontron/ktqm77/romstage.c | 2 ++ src/mainboard/samsung/lumpy/romstage.c | 2 ++ src/mainboard/samsung/stumpy/romstage.c | 2 ++ src/northbridge/intel/sandybridge/raminit.c | 7 +------ src/northbridge/intel/sandybridge/raminit.h | 1 + 10 files changed, 18 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 67e509e..b9a2ae1 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -245,6 +245,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 27a22f7..dbaf04b 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -287,6 +287,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 2fe61d6..253e679 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -245,6 +245,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index a0700af..99aa93b 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -297,6 +297,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index f116668..d132642 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -297,6 +297,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 773079d..9f15401 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -296,6 +296,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 6c87f88..8c5d5ac 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -318,6 +318,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index ee715e7..a96b301 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -325,6 +325,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data) #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6dc7dbf..11e743b 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -54,7 +54,7 @@ #define CMOS_OFFSET_MRC_SEED_CHK 160 #endif -static void save_mrc_data(struct pei_data *pei_data) +void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; @@ -63,7 +63,6 @@ static void save_mrc_data(struct pei_data *pei_data) int output_len = ALIGN(pei_data->mrc_output_len, 16); /* Save the MRC S3 restore data to cbmem */ - cbmem_initialize(); mrcdata = cbmem_add (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container)); @@ -299,8 +298,4 @@ void sdram_initialize(struct pei_data *pei_data) post_system_agent_init(pei_data); report_memory_config(); - - /* S3 resume: don't save scrambler seed or MRC data */ - if (pei_data->boot_mode != 2) - save_mrc_data(pei_data); } diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 2e9b1f3..c3b1c2a 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -30,6 +30,7 @@ struct sys_info { } __attribute__ ((packed)); void sdram_initialize(struct pei_data *pei_data); +void save_mrc_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); #endif /* RAMINIT_H */

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New patch to review for coreboot: f18612f google/stout: Add EARLY_CBMEM_INIT
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4665 -gerrit commit f18612fef48b1e872520194f76d716f54e375a6a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 15 20:16:26 2013 +0300 google/stout: Add EARLY_CBMEM_INIT Required for MRC cache and for HAVE_ACPI_RESUME to work. Change-Id: I7d48b167bd581d7c14ca50bd46e74be0133cecfb Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/stout/Kconfig | 1 + src/mainboard/google/stout/romstage.c | 4 ---- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 7ee8fd4..fb81754 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -8,6 +8,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_C216 select EC_QUANTA_IT8518 select BOARD_ROMSIZE_KB_8192 + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index 8a961ea..a0700af 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -296,11 +296,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; -#if CONFIG_EARLY_CBMEM_INIT cbmem_was_initted = !cbmem_initialize(); -#else - cbmem_was_initted = cbmem_reinit(); -#endif #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so

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New patch to review for coreboot: 78e1348 roda/rk9: Add EARLY_CBMEM_INIT
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4664 -gerrit commit 78e13487a7fd6ccdc7ee3b736410bc9167bf77bd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 20:41:57 2013 +0300 roda/rk9: Add EARLY_CBMEM_INIT Change-Id: I450f78cce7172fd2dee66dc81b4f33e07c1aff09 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/roda/rk9/Kconfig | 2 +- src/mainboard/roda/rk9/romstage.c | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mainboard/roda/rk9/Kconfig b/src/mainboard/roda/rk9/Kconfig index 59ae455..83cc450 100644 --- a/src/mainboard/roda/rk9/Kconfig +++ b/src/mainboard/roda/rk9/Kconfig @@ -13,8 +13,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select CARDBUS_PLUGIN_SUPPORT select HAVE_ACPI_TABLES - #select HAVE_ACPI_RESUME select EC_ACPI + select EARLY_CBMEM_INIT select HAVE_OPTION_TABLE config MAINBOARD_DIR diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 075790d..e71e9c4 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -123,6 +123,7 @@ void main(unsigned long bist) { sysinfo_t sysinfo; int s3resume = 0; + int cbmem_initted; u16 reg16; /* basic northbridge setup, including MMCONF BAR */ @@ -183,11 +184,12 @@ void main(unsigned long bist) init_iommu(); + cbmem_initted = !cbmem_initialize(); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_reinit() { + if (s3resume && cbmem_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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Patch set updated for coreboot: 67fdc78 CBMEM intel: Define get_top_of_ram() once per chipset
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3993 -gerrit commit 67fdc78775cae877285dd2cf41097962ac801e68 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 15 17:19:41 2013 +0300 CBMEM intel: Define get_top_of_ram() once per chipset Only have one definition of get_top_of_ram() function and compile it using __SIMPLE_DEVICE__ for both romstage and ramstage. Implemented like this on intel/northbridge/gm45 already. This also adds get_top_of_ram() to i945 ramstage. Change-Id: Ia82cf6e47a4c929223ea3d8f233d606e6f5bf2f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/intel/haswell/Makefile.inc | 2 + src/northbridge/intel/haswell/northbridge.c | 10 ----- src/northbridge/intel/haswell/ram_calc.c | 35 +++++++++++++++ src/northbridge/intel/haswell/raminit.c | 10 ----- src/northbridge/intel/i945/Makefile.inc | 2 + src/northbridge/intel/i945/ram_calc.c | 57 +++++++++++++++++++++++++ src/northbridge/intel/i945/raminit.c | 33 -------------- src/northbridge/intel/sandybridge/Makefile.inc | 2 + src/northbridge/intel/sandybridge/northbridge.c | 7 --- src/northbridge/intel/sandybridge/ram_calc.c | 31 ++++++++++++++ src/northbridge/intel/sandybridge/raminit.c | 7 --- 11 files changed, 129 insertions(+), 67 deletions(-) diff --git a/src/northbridge/intel/haswell/Makefile.inc b/src/northbridge/intel/haswell/Makefile.inc index 04b0d2f..bf7daa7 100644 --- a/src/northbridge/intel/haswell/Makefile.inc +++ b/src/northbridge/intel/haswell/Makefile.inc @@ -17,6 +17,7 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c @@ -24,6 +25,7 @@ ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c ramstage-y += minihd.c +romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += mrccache.c romstage-y += early_init.c diff --git a/src/northbridge/intel/haswell/northbridge.c b/src/northbridge/intel/haswell/northbridge.c index bdf87b1..8d57c03 100644 --- a/src/northbridge/intel/haswell/northbridge.c +++ b/src/northbridge/intel/haswell/northbridge.c @@ -449,16 +449,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -unsigned long get_top_of_ram(void) -{ - u32 reg; - - /* The top the reserve regions fall just below the TSEG region. */ - reg = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), TSEG); - - return (reg & ~((1 << 20) - 1)); -} - static void northbridge_enable(device_t dev) { #if CONFIG_HAVE_ACPI_RESUME diff --git a/src/northbridge/intel/haswell/ram_calc.c b/src/northbridge/intel/haswell/ram_calc.c new file mode 100644 index 0000000..99e7d67 --- /dev/null +++ b/src/northbridge/intel/haswell/ram_calc.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "haswell.h" + +unsigned long get_top_of_ram(void) +{ + /* + * Base of TSEG is top of usable DRAM below 4GiB. The register has + * 1 MiB alignement. + */ + u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return (unsigned long) tom & ~((1 << 20) - 1); +} diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index e916c5e..623336a 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -203,13 +203,3 @@ void sdram_initialize(struct pei_data *pei_data) report_memory_config(); } - -unsigned long get_top_of_ram(void) -{ - /* - * Base of TSEG is top of usable DRAM below 4GiB. The register has - * 1 MiB alignement. - */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom & ~((1 << 20) - 1); -} diff --git a/src/northbridge/intel/i945/Makefile.inc b/src/northbridge/intel/i945/Makefile.inc index 92a8849..67643eb 100644 --- a/src/northbridge/intel/i945/Makefile.inc +++ b/src/northbridge/intel/i945/Makefile.inc @@ -17,10 +17,12 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c +romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += early_init.c romstage-y += errata.c diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c new file mode 100644 index 0000000..4ece540 --- /dev/null +++ b/src/northbridge/intel/i945/ram_calc.c @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "i945.h" + +unsigned long get_top_of_ram(void) +{ + u32 tom; + + if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { + /* IGD enabled, get top of Memory from BSM register */ + tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); + } else { + tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; + } + + /* if TSEG enabled subtract size */ + switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { + case 0x01: + /* 1MB TSEG */ + tom -= 0x10000; + break; + case 0x03: + /* 2MB TSEG */ + tom -= 0x20000; + break; + case 0x05: + /* 8MB TSEG */ + tom -= 0x80000; + break; + default: + /* TSEG either disabled or invalid */ + break; + } + return (unsigned long) tom; +} diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 512d8e9..4576478 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -3182,36 +3182,3 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) sdram_setup_processor_side(); } - -unsigned long get_top_of_ram(void) -{ - u32 tom; - - if (pci_read_config8(PCI_DEV(0, 0x0, 0), DEVEN) & ((1 << 4) | (1 << 3))) { - /* IGD enabled, get top of Memory from BSM register */ - tom = pci_read_config32(PCI_DEV(0,2,0), 0x5c); - } else { - tom = (pci_read_config8(PCI_DEV(0,0,0), TOLUD) & 0xf7) << 24; - } - - /* if TSEG enabled subtract size */ - switch(pci_read_config8(PCI_DEV(0, 0, 0), ESMRAM)) { - case 0x01: - /* 1MB TSEG */ - tom -= 0x10000; - break; - case 0x03: - /* 2MB TSEG */ - tom -= 0x20000; - break; - case 0x05: - /* 8MB TSEG */ - tom -= 0x80000; - break; - default: - /* TSEG either disabled or invalid */ - break; - } - return (unsigned long) tom; -} - diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index be07e93..2c2e05a 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -17,12 +17,14 @@ # Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA # +ramstage-y += ram_calc.c ramstage-y += northbridge.c ramstage-y += gma.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.c ramstage-y += mrccache.c +romstage-y += ram_calc.c romstage-y += raminit.c romstage-y += mrccache.c romstage-y += early_init.c diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index a03b8a6..7db9301 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -51,13 +51,6 @@ int bridge_silicon_revision(void) return bridge_revision_id; } -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(dev_find_slot(0, PCI_DEVFN(0,0)), TSEG); - return (unsigned long) tom; -} - /* Reserve everything between A segment and 1MB: * * 0xa0000 - 0xbffff: legacy VGA diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c new file mode 100644 index 0000000..3693a07 --- /dev/null +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <cbmem.h> +#include "sandybridge.h" + +unsigned long get_top_of_ram(void) +{ + /* Base of TSEG is top of usable DRAM */ + u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); + return (unsigned long) tom; +} diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 333a6b5..6dc7dbf 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -304,10 +304,3 @@ void sdram_initialize(struct pei_data *pei_data) if (pei_data->boot_mode != 2) save_mrc_data(pei_data); } - -unsigned long get_top_of_ram(void) -{ - /* Base of TSEG is top of usable DRAM */ - u32 tom = pci_read_config32(PCI_DEV(0,0,0), TSEG); - return (unsigned long) tom; -}

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Patch set updated for coreboot: 4057c54 intel/i945 boards: Add EARLY_CBMEM_INIT
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3994 -gerrit commit 4057c54c31d1a3b53d54567ab91b0bef470ad4f7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 13 20:41:57 2013 +0300 intel/i945 boards: Add EARLY_CBMEM_INIT Inspired by commits ac6ea04b and 4560ca50 that enabled this feature for lenovo/x60 and lenovo/t60 with i945 chipset. Change-Id: Ia04f58b8c3769b5734708c6a338bb80c13c5aeba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/getac/p470/Kconfig | 1 + src/mainboard/getac/p470/romstage.c | 8 +++++--- src/mainboard/ibase/mb899/Kconfig | 1 + src/mainboard/ibase/mb899/romstage.c | 8 +++++--- src/mainboard/intel/d945gclf/Kconfig | 1 + src/mainboard/intel/d945gclf/romstage.c | 8 +++++--- src/mainboard/kontron/986lcd-m/Kconfig | 1 + src/mainboard/kontron/986lcd-m/romstage.c | 8 +++++--- src/mainboard/roda/rk886ex/Kconfig | 1 + src/mainboard/roda/rk886ex/romstage.c | 8 +++++--- 10 files changed, 30 insertions(+), 15 deletions(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index 3fdf6f7..db42233 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SUPERIO_SMSC_FDC37N972 select SUPERIO_SMSC_SIO10N268 select EC_ACPI + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index f4e43e5..87af8ca 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -263,12 +264,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -357,11 +357,13 @@ void main(unsigned long bist) #endif MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 36353b3..72b916f 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627EHG + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index b059a57..222c376 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include "superio/winbond/w83627ehg/w83627ehg.h" #include <pc80/mc146818rtc.h> #include <console/console.h> @@ -221,12 +222,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -311,11 +311,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index 0a9de1a..b676eb6 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_512 diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 248aa3b..166743f 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -26,6 +26,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include "superio/smsc/lpc47m15x/lpc47m15x.h" #include <pc80/mc146818rtc.h> #include <console/console.h> @@ -182,12 +183,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -269,11 +269,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index e8b7225..29d4da4 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -9,6 +9,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CHECK_SLFRCS_ON_RESUME select SOUTHBRIDGE_INTEL_I82801GX select SUPERIO_WINBOND_W83627THG + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 324f442..1875a10 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <string.h> #include <lib.h> +#include <cbmem.h> #include <arch/io.h> #include <device/pci_def.h> #include <device/pnp_def.h> @@ -314,12 +315,11 @@ static void early_ich7_init(void) RCBA32(0x2034) = reg32; } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -410,11 +410,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 2113deb..365980e 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -14,6 +14,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE + select EARLY_CBMEM_INIT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index cb141f9..e08c1c0 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -28,6 +28,7 @@ #include <device/pnp_def.h> #include <cpu/x86/lapic.h> #include <lib.h> +#include <cbmem.h> #include <pc80/mc146818rtc.h> #include <console/console.h> #include <cpu/x86/bist.h> @@ -249,12 +250,11 @@ static void init_artec_dongle(void) outb(0xf4, 0x88); } -#include <cbmem.h> - void main(unsigned long bist) { u32 reg32; int boot_mode = 0; + int cbmem_was_initted; if (bist == 0) enable_lapic(); @@ -346,11 +346,13 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; + cbmem_was_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if ((boot_mode == 2) && cbmem_reinit()) { + if ((boot_mode == 2) && cbmem_was_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

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Patch set updated for coreboot: 8f24480 arch/x86/acpi/globutil.asl: Make control method `S2BF` serialized
by Ronald G. Minnich 11 Jan '14

11 Jan '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4093 -gerrit commit 8f2448018fb5ed850e06cc7d5dff9aa616405053 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Nov 18 11:57:45 2013 +0100 arch/x86/acpi/globutil.asl: Make control method `S2BF` serialized This changes eliminates a warning from the ASL compiler. Change-Id: I502cca731b6b4cd3e17c57fc191f1eed10a5a1fe Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/arch/x86/acpi/globutil.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi/globutil.asl b/src/arch/x86/acpi/globutil.asl index b39113f..a39d6ed 100644 --- a/src/arch/x86/acpi/globutil.asl +++ b/src/arch/x86/acpi/globutil.asl @@ -39,7 +39,7 @@ Method(SLEN, 1) Return(Sizeof(Local0)) } -Method(S2BF, 1) +Method(S2BF, 1, Serialized) { Add(SLEN(Arg0), One, Local0) Name(BUFF, Buffer(Local0) {})

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Patch set updated for coreboot: 21f4dac cpu/samsung/exynos5250/cpu.c: Remove unused variable `ret`
by Ronald G. Minnich 11 Jan '14

11 Jan '14

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4594 -gerrit commit 21f4dac39896ff71679650bb405646ae20d831b8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Wed Jan 1 14:37:33 2014 +0100 cpu/samsung/exynos5250/cpu.c: Remove unused variable `ret` Change-Id: I72a5a802aef0a75b0277eaac6ca6c24793812d98 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/samsung/exynos5250/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/cpu/samsung/exynos5250/cpu.c b/src/cpu/samsung/exynos5250/cpu.c index 61f937b..c663d38 100644 --- a/src/cpu/samsung/exynos5250/cpu.c +++ b/src/cpu/samsung/exynos5250/cpu.c @@ -64,7 +64,6 @@ static void set_cpu_id(void) */ static void exynos_displayport_init(device_t dev) { - int ret; struct cpu_samsung_exynos5250_config *conf = dev->chip_info; /* put these on the stack. If, at some point, we want to move * this code to a pre-ram stage, it will be much easier. @@ -117,7 +116,7 @@ static void exynos_displayport_init(device_t dev) mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB); printk(BIOS_DEBUG, "Initializing Exynos VGA, base %p\n", (void *)lcdbase); - ret = lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); + lcd_ctrl_init(fb_size, &panel, (void *)lcdbase); } static void cpu_enable(device_t dev)

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coreboot-gerrit January 2014