coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

1 participants
1801 discussions

Patch merged into coreboot/master: 6f29a19 ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree.
by gerrit＠coreboot.org 12 Jan '14

12 Jan '14

the following patch was just integrated into master: commit 6f29a19297583b8b4f02208e8965be668fdf58df Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:42:09 2014 +0100 ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree. wwan_enable was never used. wlan_enable isn't something for device tree but for CMOS config if at all. Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4651 for details. -gerrit

1 0

Patch set updated for coreboot: c1ff596 ec/lenovo/h8: make wlan config a CMOS option
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4652 -gerrit commit c1ff596145104d4f8d69ff5f8cb99f249247e548 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 03:45:53 2014 +0100 ec/lenovo/h8: make wlan config a CMOS option To stay in line with wwan and bluetooth. Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/ec/lenovo/h8/h8.c | 6 +++++- src/mainboard/lenovo/t60/cmos.layout | 1 + src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 3 ++- src/mainboard/lenovo/x60/cmos.default | 1 + src/mainboard/lenovo/x60/cmos.layout | 1 + 6 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/ec/lenovo/h8/h8.c b/src/ec/lenovo/h8/h8.c index c25903a..8b0ca20 100644 --- a/src/ec/lenovo/h8/h8.c +++ b/src/ec/lenovo/h8/h8.c @@ -174,7 +174,11 @@ static void h8_enable(device_t dev) ec_write(0x1f, conf->eventf_enable); ec_write(H8_FAN_CONTROL, H8_FAN_CONTROL_AUTO); - h8_wlan_enable(1); + + if (get_option(&val, "wlan") != CB_SUCCESS) + val = 1; + h8_wlan_enable(val); + h8_trackpoint_enable(conf->trackpoint_enable); h8_usb_power_enable(1); diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index a179752..d5f3dbf 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -110,6 +110,7 @@ entries 1060 1 e 1 touchpad 1061 1 e 1 bluetooth 1062 1 e 1 wwan +1063 1 e 1 wlan 1064 8 h 0 volume 1072 1 e 9 first_battery # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..a6d8ed1 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -8,4 +8,5 @@ volume=0x3 first_battery=Primary bluetooth=Enable wwan=Enable +wlan=Enable touchpad=Enable diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..db58edf 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +415 1 e 1 wlan +#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 5d82ff0..bb8088f 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -12,3 +12,4 @@ volume=0x3 tft_brightness=0xff first_battery=Primary bluetooth=Enable +wlan=Enable diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 45bb95a..13df7a5 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -112,6 +112,7 @@ entries 1080 1 e 9 first_battery 1081 1 e 1 bluetooth 1082 1 e 1 wwan +1083 1 e 1 wlan # ----------------------------------------------------------------- enumerations

1 0

Patch set updated for coreboot: f4a8dd5 CBMEM: Replace cbmem_initialize() with cbmem_recovery()
by Kyösti Mälkki 12 Jan '14

12 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4668 -gerrit commit f4a8dd5e470c5355408ad855f10eaeaf7ecf69f2 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 6 17:20:31 2014 +0200 CBMEM: Replace cbmem_initialize() with cbmem_recovery() The replacement function confirms CBMEM region is wiped clean on power cycles and resets. It also introduces compatibility interface to ease up transition to DYNAMIC_CBMEM. Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 9 ++++-- src/lib/cbmem.c | 40 +++++++++++++++----------- src/lib/dynamic_cbmem.c | 10 +++++++ src/mainboard/emulation/qemu-i440fx/romstage.c | 2 +- src/mainboard/emulation/qemu-q35/romstage.c | 2 +- src/mainboard/getac/p470/romstage.c | 2 +- src/mainboard/google/butterfly/romstage.c | 2 +- src/mainboard/google/link/romstage.c | 2 +- src/mainboard/google/parrot/romstage.c | 2 +- src/mainboard/google/stout/romstage.c | 2 +- src/mainboard/ibase/mb899/romstage.c | 2 +- src/mainboard/intel/cougar_canyon2/romstage.c | 2 +- src/mainboard/intel/d945gclf/romstage.c | 2 +- src/mainboard/intel/emeraldlake2/romstage.c | 2 +- src/mainboard/kontron/986lcd-m/romstage.c | 2 +- src/mainboard/kontron/ktqm77/romstage.c | 2 +- src/mainboard/lenovo/t60/romstage.c | 2 +- src/mainboard/lenovo/x201/romstage.c | 6 +++- src/mainboard/lenovo/x60/romstage.c | 2 +- src/mainboard/roda/rk886ex/romstage.c | 2 +- src/mainboard/roda/rk9/romstage.c | 2 +- src/mainboard/samsung/lumpy/romstage.c | 2 +- src/mainboard/samsung/stumpy/romstage.c | 2 +- src/mainboard/via/epia-m850/romstage.c | 2 +- src/northbridge/intel/nehalem/raminit.c | 2 +- 25 files changed, 65 insertions(+), 42 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index 5f1ac3c..eff1895 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -90,6 +90,9 @@ struct cbmem_entry; #define DYN_CBMEM_ALIGN_SIZE (4096) +/* By default cbmem is attempted to be recovered. Returns 0 if cbmem was + * recovered or 1 if cbmem had to be reinitialized. */ +int cbmem_initialize(void); /* Initialize cbmem to be empty. */ void cbmem_initialize_empty(void); @@ -153,9 +156,9 @@ struct cbmem_entry *get_cbmem_toc(void); unsigned long get_top_of_ram(void); -/* By default cbmem is attempted to be recovered. Returns 0 if cbmem was - * recovered or 1 if cbmem had to be reinitialized. */ -int cbmem_initialize(void); +/* Returns 0 if old cbmem was recovered. Recovery is only attempted if + * s3resume is non-zero. */ +int cbmem_recovery(int s3resume); /* Add a cbmem entry of a given size and id. These return NULL on failure. The * add function performs a find first and do not check against the original * size. */ diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 6cdf772..704733f 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -95,8 +95,7 @@ void cbmem_late_set_table(uint64_t base, uint64_t size) * - suspend/resume backup memory */ -#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) -static void cbmem_init(void) +static void cbmem_initialize_empty(void) { uint64_t baseaddr, size; struct cbmem_entry *cbmem_toc; @@ -119,7 +118,6 @@ static void cbmem_init(void) .size = size - CBMEM_TOC_RESERVED }; } -#endif int cbmem_reinit(void) { @@ -219,32 +217,40 @@ void *cbmem_find(u32 id) return (void *)NULL; } -#if CONFIG_EARLY_CBMEM_INIT || !defined(__PRE_RAM__) /* Returns True if it was not initialized before. */ -int cbmem_initialize(void) +int cbmem_recovery(int is_wakeup) { - int rv = 0; + int found = cbmem_reinit(); + int wipe = 0; + +#if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT + wipe = 1; +#endif +#if !defined(__PRE_RAM__) && !CONFIG_EARLY_CBMEM_INIT + wipe = 1; +#endif + + if (!is_wakeup && wipe) + cbmem_initialize_empty(); - /* We expect the romstage to always initialize it. */ - if (!cbmem_reinit()) { - cbmem_init(); + if (is_wakeup && !found) { + cbmem_initialize_empty(); cbmem_fail_resume(); - rv = 1; } -#ifndef __PRE_RAM__ + cbmem_arch_init(); -#endif - /* Migrate cache-as-ram variables. */ car_migrate_variables(); - - return rv; + return !found; } -#endif #ifndef __PRE_RAM__ static void init_cbmem_post_device(void *unused) { - cbmem_initialize(); +#if CONFIG_HAVE_ACPI_RESUME + cbmem_recovery(acpi_is_wakeup()); +#else + cbmem_recovery(0); +#endif #if CONFIG_CONSOLE_CBMEM cbmemc_reinit(); #endif diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index 0ab8f81..0cc6295 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -256,6 +256,16 @@ int cbmem_initialize(void) return 0; } +int cbmem_recovery(int is_wakeup) +{ + int rv = 0; + if (!is_wakeup) + cbmem_initialize_empty(); + else + rv = cbmem_initialize(); + return rv; +} + static void *cbmem_base(void) { struct cbmem_root *root; diff --git a/src/mainboard/emulation/qemu-i440fx/romstage.c b/src/mainboard/emulation/qemu-i440fx/romstage.c index db8891e..0613d82 100644 --- a/src/mainboard/emulation/qemu-i440fx/romstage.c +++ b/src/mainboard/emulation/qemu-i440fx/romstage.c @@ -48,7 +48,7 @@ void main(unsigned long bist) //print_pci_devices(); //dump_pci_devices(); - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(0); timestamp_init(rdtsc()); timestamp_add_now(TS_START_ROMSTAGE); diff --git a/src/mainboard/emulation/qemu-q35/romstage.c b/src/mainboard/emulation/qemu-q35/romstage.c index fae5095..190c775 100644 --- a/src/mainboard/emulation/qemu-q35/romstage.c +++ b/src/mainboard/emulation/qemu-q35/romstage.c @@ -50,7 +50,7 @@ void main(unsigned long bist) //print_pci_devices(); //dump_pci_devices(); - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(0); timestamp_init(rdtsc()); timestamp_add_now(TS_START_ROMSTAGE); diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c index 87af8ca..a081a8a 100644 --- a/src/mainboard/getac/p470/romstage.c +++ b/src/mainboard/getac/p470/romstage.c @@ -357,7 +357,7 @@ void main(unsigned long bist) #endif MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index b7ec011..d32f3f0 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -244,7 +244,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 6074f85..4b3fe1f 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -286,7 +286,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index b6bacae..361c19b 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -244,7 +244,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index a775e69..0ea53e7 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -296,7 +296,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c index 222c376..0b9d408 100644 --- a/src/mainboard/ibase/mb899/romstage.c +++ b/src/mainboard/ibase/mb899/romstage.c @@ -311,7 +311,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/intel/cougar_canyon2/romstage.c b/src/mainboard/intel/cougar_canyon2/romstage.c index 42b19e4..afd7e25 100644 --- a/src/mainboard/intel/cougar_canyon2/romstage.c +++ b/src/mainboard/intel/cougar_canyon2/romstage.c @@ -322,7 +322,7 @@ void romstage_main_continue(EFI_STATUS status, VOID *HobListPtr) { quick_ram_check(); post_code(0x4e); - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(0); if(cbmem_was_initted) { reset_system(); diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c index 166743f..69d4232 100644 --- a/src/mainboard/intel/d945gclf/romstage.c +++ b/src/mainboard/intel/d945gclf/romstage.c @@ -269,7 +269,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 3534700..9308e96 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -296,7 +296,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c index 1875a10..549facd 100644 --- a/src/mainboard/kontron/986lcd-m/romstage.c +++ b/src/mainboard/kontron/986lcd-m/romstage.c @@ -410,7 +410,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 15c10b2..b5959b1 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -295,7 +295,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/lenovo/t60/romstage.c b/src/mainboard/lenovo/t60/romstage.c index 1b7e693..dae917c 100644 --- a/src/mainboard/lenovo/t60/romstage.c +++ b/src/mainboard/lenovo/t60/romstage.c @@ -321,7 +321,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 18645ac..7935e56 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -331,7 +331,11 @@ void main(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } - cbmem_initted = !cbmem_initialize(); + /* FIXME: If not in s3resume, raminit() calls cbmem_recovery(0), + * clears all of CBMEM region and puts in MRC training results. + * Tell here we are doing resume to avoid wiping CBMEM region + * again. */ + cbmem_initted = !cbmem_recovery(1); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c index 26a7b9b..1198fb2 100644 --- a/src/mainboard/lenovo/x60/romstage.c +++ b/src/mainboard/lenovo/x60/romstage.c @@ -323,7 +323,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c index e08c1c0..ad323f5 100644 --- a/src/mainboard/roda/rk886ex/romstage.c +++ b/src/mainboard/roda/rk886ex/romstage.c @@ -346,7 +346,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index e71e9c4..90392b9 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -184,7 +184,7 @@ void main(unsigned long bist) init_iommu(); - cbmem_initted = !cbmem_initialize(); + cbmem_initted = !cbmem_recovery(0); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index fd3c19b..c240e44 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -317,7 +317,7 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index 7630c05..e5b55b5 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -324,7 +324,7 @@ void main(unsigned long bist) post_code(0x3e); MCHBAR16(SSKPD) = 0xCAFE; - cbmem_was_initted = !cbmem_initialize(); + cbmem_was_initted = !cbmem_recovery(boot_mode==2); if (boot_mode!=2) save_mrc_data(&pei_data); diff --git a/src/mainboard/via/epia-m850/romstage.c b/src/mainboard/via/epia-m850/romstage.c index 39f4253..262bee7 100644 --- a/src/mainboard/via/epia-m850/romstage.c +++ b/src/mainboard/via/epia-m850/romstage.c @@ -95,7 +95,7 @@ void main(unsigned long bist) /* We got RAM working, now we can write the timestamps to RAM */ #if CONFIG_EARLY_CBMEM_INIT - cbmem_initialize(); + cbmem_recovery(0); #endif timestamp_add_now(TS_END_ROMSTAGE); /* FIXME: See if this is needed or take this out please */ diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 19af3bb..c7acd47 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1699,7 +1699,7 @@ static void save_timings(struct raminfo *info) train.reg_10b = read_1d0(0x10b, 6); /* Save the MRC S3 restore data to cbmem */ - cbmem_initialize(); + cbmem_recovery(0); mrcdata = cbmem_add (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container));

1 0

Patch merged into coreboot/master: 8f24480 arch/x86/acpi/globutil.asl: Make control method `S2BF` serialized
by gerrit＠coreboot.org 12 Jan '14

12 Jan '14

the following patch was just integrated into master: commit 8f2448018fb5ed850e06cc7d5dff9aa616405053 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Nov 18 11:57:45 2013 +0100 arch/x86/acpi/globutil.asl: Make control method `S2BF` serialized This changes eliminates a warning from the ASL compiler. Change-Id: I502cca731b6b4cd3e17c57fc191f1eed10a5a1fe Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See http://review.coreboot.org/4093 for details. -gerrit

1 0

Patch set updated for coreboot: b108141 AGESA f15tn: Fix GPP ports resume
by Rudolf Marek 12 Jan '14

12 Jan '14

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4671 -gerrit commit b108141c09961aa35ccb2a266856a20bb583a447 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Jan 12 00:23:30 2014 +0100 AGESA f15tn: Fix GPP ports resume The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(), which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink() looks into CMOS to figure out what ports to just force to Gen1 or Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP init is executed. There is a problem that nobody sets properly the PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving() thinks the GPP port is not enabled and shut downs it. The best fix would be also to remove the CMOS dependency which might be some left over, because AGESA does not use CMOS much for anything else. There could be also some way how to pass the GPP state structure from romstage to ramstage possibly via hudson/resume.c but I don't know how to do that. Similar problem is that the "late" stage of init again "forgets" the PortDetected state. This fix fixes the resume issue on Asus F2A85-M. With this patch applied both GPP ports (used as PCIe x1 and internal ethernet) are working again after resume. Change-Id: Idaf609043abb09441c6790504d66d23e0637588f Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c | 16 ++++++++++++++++ src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c | 5 ++++- 2 files changed, 20 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c index e4db032..678ddaa 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c @@ -65,10 +65,26 @@ FchInitEnvGpp ( { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; + UINT8 GppS3Data; + UINT8 PortId; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; + /* + * The romstage will force link, but re-read the GPP params from CMOS, + * otherwise the late init will powerdown all ports including + * those which were just taken out of S3 + */ + if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data); + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + if ( GppS3Data & (1 << (PortId + 4))) { + LocalCfgPtr->Gpp.PortCfg[PortId].PortDetected = TRUE; + } + } + } + if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) { ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader); FchStall (5000, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c index d4c9fe9..4c77358 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppLate.c @@ -281,6 +281,9 @@ FchInitLateGpp ( RwAlink (0x310 | (UINT32) (ABCFG << 29), 0xFFFFFFFF, BIT7, StdHeader); RwAlink (FCH_RCINDXC_REGC0, 0xFFFFFFFF, BIT9, StdHeader); } - RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data); + + if (ReadFchSleepType (StdHeader) != ACPI_SLPTYP_S3) { + RwMem (ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, 0, GppS3Data); + } }

1 0

New patch to review for coreboot: 2b850ea AGESA f15tn: Fix GPP ports resume
by Rudolf Marek 12 Jan '14

12 Jan '14

Rudolf Marek (r.marek(a)assembler.cz) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4671 -gerrit commit 2b850eaf03649bef12dbe8098bf0382a34058739 Author: Rudolf Marek <r.marek(a)assembler.cz> Date: Sun Jan 12 00:23:30 2014 +0100 AGESA f15tn: Fix GPP ports resume The AGESA resumes the GPP ports in the romstage using FchInitResetGpp(), which does FchGppPortInitS3Phase() for S3 resume. The PreInitGppLink() looks into CMOS to figure out what ports to just force to Gen1 or Gen2 PCIe. Then boot continues and in the ramstage the rest of GPP init is executed. There is a problem that nobody sets properly the PortDetected flags in the S3 path. As the consequence FchGppDynamicPowerSaving() thinks the GPP port is not enabled and shut downs it. The best fix would be also to remove the CMOS dependency which might be some left over, because AGESA does not use CMOS much for anything else. There could be also some way how to pass the GPP state structure from romstage to ramstage possibly via hudson/resume.c but I don't know how to do that. This fix fixes the resume issue on Asus F2A85-M. With this patch applied both GPP ports (used as PCIe x1 and internal ethernet) are working again after resume. Change-Id: Idaf609043abb09441c6790504d66d23e0637588f Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> --- src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c index e4db032..678ddaa 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcie/GppEnv.c @@ -65,10 +65,26 @@ FchInitEnvGpp ( { FCH_DATA_BLOCK *LocalCfgPtr; AMD_CONFIG_PARAMS *StdHeader; + UINT8 GppS3Data; + UINT8 PortId; LocalCfgPtr = (FCH_DATA_BLOCK *) FchDataPtr; StdHeader = LocalCfgPtr->StdHeader; + /* + * The romstage will force link, but re-read the GPP params from CMOS, + * otherwise the late init will powerdown all ports including + * those which were just taken out of S3 + */ + if (ReadFchSleepType (StdHeader) == ACPI_SLPTYP_S3) { + ReadMem ( ACPI_MMIO_BASE + CMOS_RAM_BASE + 0x0D, AccessWidth8, &GppS3Data); + for ( PortId = 0; PortId < MAX_GPP_PORTS; PortId++ ) { + if ( GppS3Data & (1 << (PortId + 4))) { + LocalCfgPtr->Gpp.PortCfg[PortId].PortDetected = TRUE; + } + } + } + if ( !LocalCfgPtr->Gpp.NewGppAlgorithm) { ProgramFchGppInitReset (&LocalCfgPtr->Gpp, StdHeader); FchStall (5000, StdHeader);

1 0

Patch set updated for coreboot: 89cd903 cpu/allwinner/a10: Provide utility to make a bootable image
by Alexandru Gagniuc 11 Jan '14

11 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4656 -gerrit commit 89cd903714b61684236d48833988aab8de036baf Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Fri Jan 10 23:06:03 2014 -0600 cpu/allwinner/a10: Provide utility to make a bootable image Up until now, we relied on mksunxiboot to prepend the header which makes coreboot.rom bootable on Allwinner SoCs. If that tool was not present, the build silently failed. Integrate this tool into our util/ package, so that we do not have to rely on mksunxiboot being in PATH. Our version of mksunxiboot also eliminates some limitations of the original tool, so we no longer have to use 'dd' to limit the file size. Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 29 ++-- util/arm_boot_tools/mksunxiboot/mksunxiboot.c | 196 ++++++++++++++++++++++++++ 2 files changed, 215 insertions(+), 10 deletions(-) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 03bc612..1b720bf 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -30,16 +30,25 @@ get_bootblock_size= \ sed 's/[^0-9 ]//g')) \ $(shell echo $$(($(word 2, $(strip $(bb_s)))))) +# This tool is used to prepend a header to coreboot.rom to trick the SoC into +# loading out bootblock +# +MKSUNXIBOOT:=$(objutil)/mksunxiboot +$(MKSUNXIBOOT): $(top)/util/arm_boot_tools/mksunxiboot/mksunxiboot.c + @printf " HOSTCC $(subst $(obj)/,,$(@))\n" + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< + # The boot ROM in the SoC will start loading code if a special BOOT0 header is # found (at an offset of 8KiB in either NAND or SD), and the checksum is -# correct. This header is normally added by the 'mxsunxiboot' tool. The boot ROM -# will load at most 24KiB of data to SRAM, so limit the file size accordingly. -# The BOOT0 header takes 32 bytes, so limit our file to 24KiB - 32 bytes. -# FIXME: Figure out how to safely integrate in coreboot.rom. -# FIXME: The file passed to mksunxiboot should only include the bootblock due -# to size limitations. -$(obj)/BOOT0: $(obj)/coreboot.rom +# correct. This header is added by the 'mxsunxiboot' tool, which is provided +# under util/arm_boot_tools/mksunxiboot. The boot ROM will load at most 24KiB of +# data to SRAM. The BOOT0 header takes 32 bytes, so bootblock is limited to +# 24KiB - 32 bytes. +# TODO: make mksunxiboot take the bootblock size as a parameter +# TODO: print an error if bootblock is too large (maybe place ROMSTAGE at the +# exact offset needed to collide with the bootblock) +# FIXME: A10 loads 24KiB. According to Oliver other chips load a little more +# +$(obj)/BOOT0: $(obj)/coreboot.rom $(MKSUNXIBOOT) @printf " BOOT0 $(subst $(obj)/,,$(^))\n" - touch $@ - dd if=$^ of=$^.tmp bs=24544 count=1 - -mksunxiboot $^.tmp $@ + $(MKSUNXIBOOT) $(word 1, $^) $@ diff --git a/util/arm_boot_tools/mksunxiboot/mksunxiboot.c b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c new file mode 100644 index 0000000..af8450c --- /dev/null +++ b/util/arm_boot_tools/mksunxiboot/mksunxiboot.c @@ -0,0 +1,196 @@ +/* + * A simple tool to generate bootable image for sunxi platform. + * + * Copyright (C) 2007-2011 Allwinner Technology Co., Ltd. + * Tom Cubie <tangliang(a)allwinnertech.com> + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <stdio.h> +#include <stdlib.h> +#include <stdint.h> +#include <string.h> +#include <errno.h> + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + uint32_t jump_instruction; /* one intruction jumping to real code */ + uint8_t magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + uint32_t check_sum; /* generated by PC */ + uint32_t length; /* generated by PC */ + /* We use a simplified header, only filling in what is needed by the + * boot ROM. To be compatible with Allwinner tools the larger header + * below should be used, followed by a custom header if desired. */ + uint8_t pad[12]; /* align to 32 bytes */ +}; + +static const char *BOOT0_MAGIC = "eGON.BT0"; +static const uint32_t STAMP_VALUE = 0x5F0A6C39; +static const int HEADER_SIZE = 32; +/* Checksum at most 24 KiB */ +#define SRAM_LOAD_MAX_SIZE ((24 << 10) - sizeof(struct boot_file_head)) +static const int BLOCK_SIZE = 512; + +inline static uint32_t le32_to_h(const void *src) +{ + const uint8_t *b = src; + return ((b[3] << 24) | (b[2] << 16) | (b[1] << 8) | (b[0] << 0)); +} + +inline static void h_to_le32(uint32_t val32, void *dest) +{ + uint8_t *b = dest; + b[0] = (val32 >> 0) & 0xff; + b[1] = (val32 >> 8) & 0xff; + b[2] = (val32 >> 16) & 0xff; + b[3] = (val32 >> 24) & 0xff; +}; + +static void serialize_header(void *dest, const struct boot_file_head *hdr) +{ + /* Unused fields are zero */ + memset(dest, 0, HEADER_SIZE); + + h_to_le32(hdr->jump_instruction, dest + 0); + memcpy(dest + 4, BOOT0_MAGIC, 8); + h_to_le32(hdr->check_sum, dest + 12); + h_to_le32(hdr->length, dest + 16); +} + +/* Check sum function from sun4i boot code */ +static int fill_check_sum(struct boot_file_head *hdr, const void *boot_code) +{ + size_t i; + uint8_t raw_hdr[HEADER_SIZE]; + uint32_t chksum; + + if ((hdr->length & 0x3) != 0) { + fprintf(stderr, "BUG! Load size is not 4-byte aligned\n"); + return EXIT_FAILURE; + } + + /* Fill in checksum seed */ + hdr->check_sum = STAMP_VALUE; + + chksum = 0; + /* Checksum the header */ + serialize_header(raw_hdr, hdr); + for (i = 0; i < HEADER_SIZE; i += 4) + chksum += le32_to_h(raw_hdr + i); + + /* Checksum the boot code */ + for (i = 0; i < hdr->length - HEADER_SIZE; i += 4) + chksum += le32_to_h(boot_code + i); + + /* write back check sum */ + hdr->check_sum = chksum; + + return EXIT_SUCCESS; +} + +static uint32_t align(uint32_t size, uint32_t alignment) +{ + return ((size + alignment - 1) / alignment) * alignment; +} + +static void fill_header(struct boot_file_head *hdr, size_t load_size) +{ + /* B instruction */ + hdr->jump_instruction = 0xEA000000; + /* Jump to the first instr after the header */ + hdr->jump_instruction |= (sizeof(*hdr) / sizeof(uint32_t) - 2); + /* No '0' termination in magic string */ + memcpy(&hdr->magic, BOOT0_MAGIC, 8); + + hdr->length = align(load_size + sizeof(hdr), BLOCK_SIZE); +} + +static long int fsize(FILE *file) +{ + long int size; + + fseek(file, 0L, SEEK_END); + size = ftell(file); + fseek(file, 0L, SEEK_SET); + return size; +} + +int main(int argc, char *argv[]) +{ + FILE *fd_in, *fd_out; + struct boot_file_head hdr; + long int file_size, load_size; + void *file_data; + uint8_t raw_hdr[HEADER_SIZE]; + int count; + + /* + * TODO: We could take an additional argument to see how much of the + * file to checksum. This way, the build system can tell us how large + * the bootblock is, so we can tell the BROM to load only the bootblock. + */ + if (argc < 2) { + printf("\tThis program makes an input bin file to sun4i " + "bootable image.\n" + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = fopen(argv[1], "r"); + if (!fd_in) { + fprintf(stderr, "Cannot open input %s", argv[1]); + return EXIT_FAILURE; + } + + /* Get input file size */ + file_size = fsize(fd_in); + if ((file_data = malloc(file_size)) == NULL) { + fprintf(stderr, "Cannot allocate memory\n"); + return EXIT_FAILURE; + } + + printf("File size: 0x%x\n", file_size); + if (fread(file_data, file_size, 1, fd_in) != 1) { + fprintf(stderr, "Cannot read %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + load_size = align(file_size, sizeof(uint32_t)); + + if (load_size > SRAM_LOAD_MAX_SIZE) + load_size = SRAM_LOAD_MAX_SIZE; + + printf("Load size: 0x%x\n", load_size); + + fd_out = fopen(argv[2], "w"); + if (!fd_out) { + fprintf(stderr, "Cannot open output %s\n", argv[2]); + return EXIT_FAILURE; + } + + /* Fill the header */ + fill_header(&hdr, load_size); + fill_check_sum(&hdr, file_data); + + /* Now write the header */ + serialize_header(raw_hdr, &hdr); + if (fwrite(raw_hdr, HEADER_SIZE, 1, fd_out) != 1) { + fprintf(stderr, "Cannot write header to %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + /* And finally, the boot code */ + if (fwrite(file_data, file_size, 1, fd_out) != 1) { + fprintf(stderr, "Cannot write to %s: %s\n", argv[1], + strerror(errno)); + return EXIT_FAILURE; + } + + fclose(fd_in); + fclose(fd_out); + + return EXIT_SUCCESS; +}

1 0

Patch set updated for coreboot: 36acbdd ibexpeak / bd82x6x: Make SATA mode user-visible option.
by Vladimir Serbinenko 11 Jan '14

11 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4658 -gerrit commit 36acbdd9a49fe67e664568abda334f3777a7605e Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 07:46:50 2014 +0100 ibexpeak / bd82x6x: Make SATA mode user-visible option. Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/google/butterfly/cmos.layout | 5 ++- src/mainboard/google/butterfly/devicetree.cb | 2 - src/mainboard/google/link/cmos.layout | 5 ++- src/mainboard/google/link/devicetree.cb | 2 - src/mainboard/google/parrot/cmos.layout | 5 ++- src/mainboard/google/parrot/devicetree.cb | 2 - src/mainboard/google/stout/cmos.layout | 5 ++- src/mainboard/google/stout/devicetree.cb | 2 - src/mainboard/intel/cougar_canyon2/cmos.layout | 5 ++- src/mainboard/intel/cougar_canyon2/devicetree.cb | 2 - src/mainboard/intel/emeraldlake2/cmos.layout | 5 ++- src/mainboard/intel/emeraldlake2/devicetree.cb | 2 - src/mainboard/kontron/ktqm77/cmos.layout | 5 ++- src/mainboard/kontron/ktqm77/devicetree.cb | 2 - src/mainboard/lenovo/x201/cmos.default | 1 + src/mainboard/lenovo/x201/cmos.layout | 5 ++- src/mainboard/lenovo/x201/devicetree.cb | 1 - src/mainboard/samsung/lumpy/cmos.layout | 5 ++- src/mainboard/samsung/lumpy/devicetree.cb | 2 - src/mainboard/samsung/stumpy/cmos.layout | 5 ++- src/mainboard/samsung/stumpy/devicetree.cb | 2 - src/southbridge/intel/bd82x6x/chip.h | 2 - src/southbridge/intel/bd82x6x/sata.c | 52 +++++++----------------- src/southbridge/intel/ibexpeak/sata.c | 52 +++++++----------------- 24 files changed, 69 insertions(+), 107 deletions(-) diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 05de624..ee5ee25 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -132,6 +133,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/butterfly/devicetree.cb b/src/mainboard/google/butterfly/devicetree.cb index e7a50c0..9a7a1d5 100644 --- a/src/mainboard/google/butterfly/devicetree.cb +++ b/src/mainboard/google/butterfly/devicetree.cb @@ -56,8 +56,6 @@ chip northbridge/intel/sandybridge #register "gpi1_routing" = "1" #SMI from EC register "gpi13_routing" = "2" #SCI from EC - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" # Enable SATA ports 0 & 1 register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/devicetree.cb b/src/mainboard/google/link/devicetree.cb index 15f420d..8f0ed3c 100644 --- a/src/mainboard/google/link/devicetree.cb +++ b/src/mainboard/google/link/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi7_routing" = "2" register "gpi8_routing" = "1" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" register "sata_port0_gen3_tx" = "0x00880a7f" diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/devicetree.cb b/src/mainboard/google/parrot/devicetree.cb index cd65fbf..59586cc 100644 --- a/src/mainboard/google/parrot/devicetree.cb +++ b/src/mainboard/google/parrot/devicetree.cb @@ -61,8 +61,6 @@ chip northbridge/intel/sandybridge register "gpi8_routing" = "1" register "gpi15_routing" = "1" #lid switch gpe - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xFD60 (EC_IO) and 0x68/0x6C diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/devicetree.cb b/src/mainboard/google/stout/devicetree.cb index 6e02020..653d3fe 100644 --- a/src/mainboard/google/stout/devicetree.cb +++ b/src/mainboard/google/stout/devicetree.cb @@ -57,8 +57,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi6_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # Set max SATA speed to 3.0 Gb/s register "sata_interface_speed_support" = "0x2" diff --git a/src/mainboard/intel/cougar_canyon2/cmos.layout b/src/mainboard/intel/cougar_canyon2/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/intel/cougar_canyon2/cmos.layout +++ b/src/mainboard/intel/cougar_canyon2/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/cougar_canyon2/devicetree.cb b/src/mainboard/intel/cougar_canyon2/devicetree.cb index e66574e..c499a56 100644 --- a/src/mainboard/intel/cougar_canyon2/devicetree.cb +++ b/src/mainboard/intel/cougar_canyon2/devicetree.cb @@ -41,8 +41,6 @@ chip northbridge/intel/fsp_sandybridge register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" device pci 14.0 on end # XHCI diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index afdd3c6..b7320b5 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 0bb42d6..0d81502 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -50,8 +50,6 @@ chip northbridge/intel/sandybridge register "alt_gp_smi_en" = "0x0002" register "gpe0_en" = "0x4000" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3f" # SuperIO range is 0x700-0x73f diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index 47cd60f..dc6a44b 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 11 sata_mode +#412 4 r 0 unused # coreboot config options: additional mainboard options 416 4 e 10 systemp_type @@ -162,6 +163,8 @@ enumerations 10 2 LM75@90 10 3 GPIO16 10 4 LM75@9e +11 0 AHCI +11 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/devicetree.cb b/src/mainboard/kontron/ktqm77/devicetree.cb index 65c03c4..f6390ac 100644 --- a/src/mainboard/kontron/ktqm77/devicetree.cb +++ b/src/mainboard/kontron/ktqm77/devicetree.cb @@ -36,8 +36,6 @@ chip northbridge/intel/sandybridge register "pirqg_routing" = "0x8b" register "pirqh_routing" = "0x8b" - register "ide_legacy_combined" = "0x0" # TODO: Does nothing since generations, remove from sb code? - register "sata_ahci" = "0x1" # Enable all SATA ports 0-5 register "sata_port_map" = "0x3f" # Set max SATA speed to 6.0 Gb/s (should be the default, anyway) diff --git a/src/mainboard/lenovo/x201/cmos.default b/src/mainboard/lenovo/x201/cmos.default index 4577e70..858f203 100644 --- a/src/mainboard/lenovo/x201/cmos.default +++ b/src/mainboard/lenovo/x201/cmos.default @@ -9,3 +9,4 @@ first_battery=Primary bluetooth=Enable wwan=Enable touchpad=Enable +sata_mode=AHCI diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 3959178..b08ec28 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -90,7 +90,8 @@ entries 412 1 e 1 bluetooth 413 1 e 1 wwan 414 1 e 1 touchpad -#415 569 r 0 unused +421 1 e 9 sata_mode +#422 562 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -129,6 +130,8 @@ enumerations 7 2 Keep 8 0 Secondary 8 1 Primary +9 0 AHCI +9 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/devicetree.cb b/src/mainboard/lenovo/x201/devicetree.cb index f800f9a..5549327 100644 --- a/src/mainboard/lenovo/x201/devicetree.cb +++ b/src/mainboard/lenovo/x201/devicetree.cb @@ -107,7 +107,6 @@ chip northbridge/intel/nehalem register "gpi1_routing" = "2" register "gpi13_routing" = "2" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x33" register "gpe0_en" = "0x20022046" diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 9552021..208e8ee 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -85,7 +85,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/lumpy/devicetree.cb b/src/mainboard/samsung/lumpy/devicetree.cb index cdd7a5c..69729d7 100644 --- a/src/mainboard/samsung/lumpy/devicetree.cb +++ b/src/mainboard/samsung/lumpy/devicetree.cb @@ -59,8 +59,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "1" register "gpi7_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x1" # EC range is 0xa00-0xa3f diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index 6d2ac45..ec393a5 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -84,7 +84,8 @@ entries # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused +411 1 e 8 sata_mode +#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -131,6 +132,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep +8 0 AHCI +8 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/samsung/stumpy/devicetree.cb b/src/mainboard/samsung/stumpy/devicetree.cb index ee01e8a..ab03c79 100644 --- a/src/mainboard/samsung/stumpy/devicetree.cb +++ b/src/mainboard/samsung/stumpy/devicetree.cb @@ -49,8 +49,6 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "0" register "gpi14_routing" = "2" - register "ide_legacy_combined" = "0x0" - register "sata_ahci" = "0x1" register "sata_port_map" = "0x3" # SuperIO range is 0x700-0x73f diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h index 828466c..0f2f0e9 100644 --- a/src/southbridge/intel/bd82x6x/chip.h +++ b/src/southbridge/intel/bd82x6x/chip.h @@ -64,8 +64,6 @@ struct southbridge_intel_bd82x6x_config { uint16_t alt_gp_smi_en; /* IDE configuration */ - uint32_t ide_legacy_combined; - uint32_t sata_ahci; uint8_t sata_port_map; uint32_t sata_port0_gen3_tx; uint32_t sata_port1_gen3_tx; diff --git a/src/southbridge/intel/bd82x6x/sata.c b/src/southbridge/intel/bd82x6x/sata.c index 594b09d..133ebee 100644 --- a/src/southbridge/intel/bd82x6x/sata.c +++ b/src/southbridge/intel/bd82x6x/sata.c @@ -24,6 +24,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_bd82x6x_config config_t; @@ -45,6 +46,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -53,48 +55,17 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_3_CLOCKS | IDE_RCT_1_CLOCKS | - IDE_PPE0 | IDE_IE0 | IDE_TIME0); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, IDE_SSDE0); - pci_write_config16(dev, IDE_SDMA_TIM, 0x0200); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config->sata_port_map ^ 0x3f) << 24) | 0x183); - } else if(config->sata_ahci) { + /* AHCI */ + if (sata_mode == 0) { u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -156,6 +127,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -244,15 +216,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8; diff --git a/src/southbridge/intel/ibexpeak/sata.c b/src/southbridge/intel/ibexpeak/sata.c index d30fae2..078dc8e 100644 --- a/src/southbridge/intel/ibexpeak/sata.c +++ b/src/southbridge/intel/ibexpeak/sata.c @@ -25,6 +25,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "pch.h" +#include <pc80/mc146818rtc.h> typedef struct southbridge_intel_ibexpeak_config config_t; @@ -46,6 +47,7 @@ static void sata_init(struct device *dev) u16 reg16; /* Get the chip configuration */ config_t *config = dev->chip_info; + u8 sata_mode; printk(BIOS_DEBUG, "SATA: Initializing...\n"); @@ -54,48 +56,17 @@ static void sata_init(struct device *dev) return; } + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + /* Default to AHCI */ + sata_mode = 0; + /* SATA configuration */ /* Enable BARs */ pci_write_config16(dev, PCI_COMMAND, 0x0007); - if (config->ide_legacy_combined) { - printk(BIOS_DEBUG, "SATA: Controller in combined mode.\n"); - - /* No AHCI: clear AHCI base */ - pci_write_config32(dev, 0x24, 0x00000000); - /* And without AHCI BAR no memory decoding */ - reg16 = pci_read_config16(dev, PCI_COMMAND); - reg16 &= ~PCI_COMMAND_MEMORY; - pci_write_config16(dev, PCI_COMMAND, reg16); - - pci_write_config8(dev, 0x09, 0x80); - - /* Set timings */ - pci_write_config16(dev, IDE_TIM_PRI, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE | - IDE_ISP_5_CLOCKS | IDE_RCT_4_CLOCKS); - - /* Sync DMA */ - pci_write_config16(dev, IDE_SDMA_CNT, 0); - pci_write_config16(dev, IDE_SDMA_TIM, 0); - - /* Set IDE I/O Configuration */ - reg32 = SIG_MODE_PRI_NORMAL | FAST_PCB1 | FAST_PCB0 | PCB1 | PCB0; - pci_write_config32(dev, IDE_CONFIG, reg32); - - /* Port enable */ - reg16 = pci_read_config16(dev, 0x92); - reg16 &= ~0x3f; - reg16 |= config->sata_port_map; - pci_write_config16(dev, 0x92, reg16); - - /* SATA Initialization register */ - pci_write_config32(dev, 0x94, - ((config-> - sata_port_map ^ 0x3f) << 24) | 0x183); - } else if (config->sata_ahci) { + if (sata_mode == 0) { + /* AHCI */ u32 abar; printk(BIOS_DEBUG, "SATA: Controller in AHCI mode.\n"); @@ -158,6 +129,7 @@ static void sata_init(struct device *dev) reg32 &= ~0x00000005; write32(abar + 0xa0, reg32); } else { + /* IDE */ printk(BIOS_DEBUG, "SATA: Controller in plain mode.\n"); /* No AHCI: clear AHCI base */ @@ -245,15 +217,19 @@ static void sata_enable(device_t dev) /* Get the chip configuration */ config_t *config = dev->chip_info; u16 map = 0; + u8 sata_mode; if (!config) return; + if (get_option(&sata_mode, "sata_mode") != CB_SUCCESS) + sata_mode = 0; + /* * Set SATA controller mode early so the resource allocator can * properly assign IO/Memory resources for the controller. */ - if (config->sata_ahci) + if (sata_mode == 0) map = 0x0060; map |= (config->sata_port_map ^ 0x3f) << 8;

1 0

Patch set updated for coreboot: a7edccc lenovo/x201: Really do EARLY_CBMEM_INIT
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4667 -gerrit commit a7edcccf66cc79bd2417637653e94cef011a3d74 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Jan 6 17:18:58 2014 +0200 lenovo/x201: Really do EARLY_CBMEM_INIT The board was missing cbmem_initialize() call in romstage. Selecting EARLY_CBMEM_INIT implies this is done in romstage. Change-Id: I9ec93f89fe4cbb9e729532be36db601b6e62bca6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8022d7b..18645ac 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -230,6 +230,7 @@ static inline u16 read_acpi16(u32 addr) void main(unsigned long bist) { u32 reg32; + int cbmem_initted; int s3resume = 0; timestamp_init(rdtsc ()); @@ -329,11 +330,14 @@ void main(unsigned long bist) reg32 = inl(DEFAULT_PMBASE + 0x04); outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } + + cbmem_initted = !cbmem_initialize(); + #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so * this is not a resume. In that case we just create the cbmem toc. */ - if (s3resume && cbmem_reinit()) { + if (s3resume && cbmem_initted) { void *resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); /* copy 1MB - 64K to high tables ram_base to prevent memory corruption

1 0

Patch set updated for coreboot: 3003dac Intel (sandy/ivy): Avoid calling cbmem_initialize() twice
by Kyösti Mälkki 11 Jan '14

11 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4666 -gerrit commit 3003dac92009ead3c00f5eb60e2e09ea361301d3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 4 11:02:45 2014 +0200 Intel (sandy/ivy): Avoid calling cbmem_initialize() twice Delay the copying of MRC cache data from CAR to CBMEM until after sdram_initialize() returns and cbmem_initialize() completes. Calling cbmem_initialize() twice would complicate the decision logic of when CBMEM area needs to be wiped clean. Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/google/butterfly/romstage.c | 2 ++ src/mainboard/google/link/romstage.c | 2 ++ src/mainboard/google/parrot/romstage.c | 2 ++ src/mainboard/google/stout/romstage.c | 2 ++ src/mainboard/intel/emeraldlake2/romstage.c | 2 ++ src/mainboard/kontron/ktqm77/romstage.c | 2 ++ src/mainboard/samsung/lumpy/romstage.c | 2 ++ src/mainboard/samsung/stumpy/romstage.c | 2 ++ src/northbridge/intel/sandybridge/raminit.c | 7 +------ src/northbridge/intel/sandybridge/raminit.h | 1 + 10 files changed, 18 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/butterfly/romstage.c b/src/mainboard/google/butterfly/romstage.c index 67e509e..b7ec011 100644 --- a/src/mainboard/google/butterfly/romstage.c +++ b/src/mainboard/google/butterfly/romstage.c @@ -245,6 +245,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 27a22f7..6074f85 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -287,6 +287,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/parrot/romstage.c b/src/mainboard/google/parrot/romstage.c index 2fe61d6..b6bacae 100644 --- a/src/mainboard/google/parrot/romstage.c +++ b/src/mainboard/google/parrot/romstage.c @@ -245,6 +245,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/google/stout/romstage.c b/src/mainboard/google/stout/romstage.c index a0700af..a775e69 100644 --- a/src/mainboard/google/stout/romstage.c +++ b/src/mainboard/google/stout/romstage.c @@ -297,6 +297,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index f116668..3534700 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -297,6 +297,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/kontron/ktqm77/romstage.c b/src/mainboard/kontron/ktqm77/romstage.c index 773079d..15c10b2 100644 --- a/src/mainboard/kontron/ktqm77/romstage.c +++ b/src/mainboard/kontron/ktqm77/romstage.c @@ -296,6 +296,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 6c87f88..fd3c19b 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -318,6 +318,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/mainboard/samsung/stumpy/romstage.c b/src/mainboard/samsung/stumpy/romstage.c index ee715e7..7630c05 100644 --- a/src/mainboard/samsung/stumpy/romstage.c +++ b/src/mainboard/samsung/stumpy/romstage.c @@ -325,6 +325,8 @@ void main(unsigned long bist) MCHBAR16(SSKPD) = 0xCAFE; cbmem_was_initted = !cbmem_initialize(); + if (boot_mode!=2) + save_mrc_data(&pei_data); #if CONFIG_HAVE_ACPI_RESUME /* If there is no high memory area, we didn't boot before, so diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6dc7dbf..11e743b 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -54,7 +54,7 @@ #define CMOS_OFFSET_MRC_SEED_CHK 160 #endif -static void save_mrc_data(struct pei_data *pei_data) +void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; @@ -63,7 +63,6 @@ static void save_mrc_data(struct pei_data *pei_data) int output_len = ALIGN(pei_data->mrc_output_len, 16); /* Save the MRC S3 restore data to cbmem */ - cbmem_initialize(); mrcdata = cbmem_add (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container)); @@ -299,8 +298,4 @@ void sdram_initialize(struct pei_data *pei_data) post_system_agent_init(pei_data); report_memory_config(); - - /* S3 resume: don't save scrambler seed or MRC data */ - if (pei_data->boot_mode != 2) - save_mrc_data(pei_data); } diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 2e9b1f3..c3b1c2a 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -30,6 +30,7 @@ struct sys_info { } __attribute__ ((packed)); void sdram_initialize(struct pei_data *pei_data); +void save_mrc_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); #endif /* RAMINIT_H */

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2014