coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: a4db825 sandybridge: Use calls rather than asm to call to MRC.
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4675 -gerrit commit a4db82528910345dc190b023203517a3c24da114 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 12 14:28:56 2014 +0100 sandybridge: Use calls rather than asm to call to MRC. Using asm as it's done currently is unsafe because caller-saved registers are not declared as clobbered. Using real call is nicer. regparm((1)) ensures that argument is passed in %eax as expected. Change-Id: I7449182582eaa53d4e473bc834b472edd8ee0d30 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/raminit.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 333a6b5..07172fc 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -219,7 +219,7 @@ static void post_system_agent_init(struct pei_data *pei_data) void sdram_initialize(struct pei_data *pei_data) { struct sys_info sysinfo; - unsigned long entry; + int (*entry) (struct pei_data *pei_data) __attribute__ ((regparm(1))); report_platform_info(); @@ -252,13 +252,11 @@ void sdram_initialize(struct pei_data *pei_data) /* Locate and call UEFI System Agent binary. */ /* TODO make MRC blob (0xab?) defined in cbfs_core.h. */ - entry = (unsigned long)cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab); + entry = cbfs_get_file_content( + CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL); if (entry) { int rv; - asm volatile ( - "call *%%ecx\n\t" - :"=a" (rv) : "c" (entry), "a" (pei_data)); + rv = entry (pei_data); if (rv) { switch (rv) { case -1:

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Patch set updated for coreboot: ecbf4db CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4674 -gerrit commit ecbf4dbe6b00550419778936986c851cf7affdfa Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 12 14:12:15 2014 +0100 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file Number one reason to use cbfs_get_file was to get file length. With prvious patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/via/nano/update_ucode.c | 19 +++++++++---------- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 10 ++++++---- src/mainboard/google/bolt/romstage.c | 12 +++++++----- src/mainboard/google/butterfly/mainboard.c | 10 ++++++---- src/mainboard/google/falco/romstage.c | 12 +++++++----- src/mainboard/google/link/romstage.c | 12 +++++++----- src/mainboard/google/peppy/romstage.c | 12 +++++++----- src/mainboard/google/slippy/romstage.c | 12 +++++++----- src/mainboard/samsung/lumpy/romstage.c | 10 +++++----- src/northbridge/intel/i82830/vga.c | 18 +++--------------- src/southbridge/intel/lynxpoint/spi_loading.c | 16 ++++------------ src/vendorcode/google/chromeos/chromeos.c | 2 +- src/vendorcode/google/chromeos/chromeos.h | 2 +- 13 files changed, 70 insertions(+), 77 deletions(-) diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 7471928..981cc36 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -102,24 +102,23 @@ unsigned int nano_update_ucode(void) { size_t i; unsigned int n_updates = 0; - const struct cbfs_file *cbfs_ucode; u32 fms = cpuid_eax(0x1); + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + u32 *ucode_data; + size_t ucode_len; - cbfs_ucode = cbfs_get_file(CBFS_DEFAULT_MEDIA, "cpu_microcode_blob.bin"); + ucode_data = cbfs_get_file(CBFS_DEFAULT_MEDIA, "cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, &ucode_len); /* Oops, did you forget to include the microcode ? */ - if(cbfs_ucode == NULL) { + if(ucode_data == NULL) { printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " "Aborting microcode updates\n"); return 0; } - /* Considering we are running with eXecute-In-Place (XIP), there's no - * need to worry that accessing data from ROM will slow us down. - * Microcode data should be aligned to a 4-byte boundary, but CBFS - * already does that for us (Do you, CBFS?) */ - const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); - const u32 ucode_len = ntohl(cbfs_ucode->len); - /* We might do a lot of loops searching for the microcode updates, but * keep in mind, nano_ucode_is_valid searches for the signature before * doing anything else. */ diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index bd593d8..ada7853 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -444,16 +444,18 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) if (info->DimmId != 0) return AGESA_UNSUPPORTED; - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("file [spd.bin] not found in CBFS"); - if (spd_file->len < SPD_SIZE) + if (spd_file_len < SPD_SIZE) die("Missing SPD data."); - memcpy((char*)info->Buffer, (char*)CBFS_SUBHEADER(spd_file), SPD_SIZE); + memcpy((char*)info->Buffer, spd_file, SPD_SIZE); u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE); diff --git a/src/mainboard/google/bolt/romstage.c b/src/mainboard/google/bolt/romstage.c index a74f10c..b698ec3 100644 --- a/src/mainboard/google/bolt/romstage.c +++ b/src/mainboard/google/bolt/romstage.c @@ -73,25 +73,27 @@ const struct rcba_config_instruction rcba_config[] = { /* Copy SPD data for on-board memory */ static void copy_spd(struct pei_data *peid) { - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; int spd_index = 0; /* No GPIO selection, force index 0 for now */ printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 1623fe0..f65d14c 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -299,7 +299,7 @@ static void verb_setup(void) static void mainboard_init(device_t dev) { u32 search_address = 0x0; - u32 search_length = -1; + size_t search_length = -1; u16 io_base = 0; struct device *ethernet_dev = NULL; #if CONFIG_CHROMEOS @@ -307,10 +307,12 @@ static void mainboard_init(device_t dev) search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); search_address = (unsigned long)(*vpd_region_ptr); #else - struct cbfs_file *vpd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "vpd.bin"); + void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin", &search_length); if (vpd_file) { - search_length = ntohl(vpd_file->len); - search_address = (unsigned long)CBFS_SUBHEADER(vpd_file); + search_address = (unsigned long)vpd_file; + } else { + search_length = -1; + search_address = 0; } #endif diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 0ad4b97..ca843e8 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -75,20 +75,22 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); /* Index 0-2 are 4GB config with both CH0 and CH1 @@ -98,7 +100,7 @@ static void copy_spd(struct pei_data *peid) peid->dimm_channel1_disabled = 3; memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 27a22f7..1aa309a 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -125,24 +125,26 @@ static void rcba_config(void) static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {41, 42, 43, 10, -1}; - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index c6696c0..4e72326 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -78,10 +78,12 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); @@ -101,17 +103,17 @@ static void copy_spd(struct pei_data *peid) break; } - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fdbac97..e2fa011 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -76,24 +76,26 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 6c87f88..a4f0c42 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -182,8 +182,8 @@ void main(unsigned long bist) }; typedef const uint8_t spd_blob[256]; - struct cbfs_file *spd_file; spd_blob *spd_data; + size_t spd_file_len; timestamp_init(get_initial_timestamp()); @@ -289,12 +289,12 @@ void main(unsigned long bist) break; } - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); - if (!spd_file) + spd_data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); + if (!spd_data) die("SPD data not found."); - if (spd_file->len < (spd_index + 1) * 256) + if (spd_file_len < (spd_index + 1) * 256) die("Missing SPD data."); - spd_data = (spd_blob *)CBFS_SUBHEADER(spd_file); // leave onboard dimm address at f0, and copy spd data there. memcpy(pei_data.spd_data[0], spd_data[spd_index], 256); diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index 49bfa34..40f23cc 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -32,21 +32,9 @@ static void vga_init(device_t dev) { printk(BIOS_INFO, "Starting Graphics Initialization\n"); - struct cbfs_file *file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "mbi.bin"); - void *mbi = NULL; - unsigned int mbi_len = 0; - - if (file) { - if (ntohl(file->type) != CBFS_TYPE_MBI) { - printk(BIOS_INFO, "CBFS: MBI binary is of type %x instead of" - "type %x\n", file->type, CBFS_TYPE_MBI); - } else { - mbi = (void *) CBFS_SUBHEADER(file); - mbi_len = ntohl(file->len); - } - } else { - printk(BIOS_INFO, "Could not find MBI.\n"); - } + size_t mbi_len; + void *mbi = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "mbi.bin", + CBFS_TYPE_MBI, &mbi_len); if (mbi && mbi_len) { /* The GDT or coreboot table is going to live here. But diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c index 1ae7a26..57e3af8 100644 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ b/src/southbridge/intel/lynxpoint/spi_loading.c @@ -28,7 +28,7 @@ #if CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> #else -static inline void *vboot_get_payload(int *len) { return NULL; } +static inline void *vboot_get_payload(size_t *len) { return NULL; } #endif #define CACHELINE_SIZE 64 @@ -73,26 +73,18 @@ static inline void *spi_mirror(void *file_start, int file_len) void *cbfs_load_payload(struct cbfs_media *media, const char *name) { - int file_len; + size_t file_len; void *file_start; - struct cbfs_file *file; file_start = vboot_get_payload(&file_len); if (file_start != NULL) return spi_mirror(file_start, file_len); - file = cbfs_get_file(media, name); + file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len); - if (file == NULL) + if (file_start == NULL) return NULL; - if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) - return NULL; - - file_len = ntohl(file->len); - - file_start = CBFS_SUBHEADER(file); - return spi_mirror(file_start, file_len); } diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 828cfd2..54fe8db 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -82,7 +82,7 @@ int recovery_mode_enabled(void) } #if CONFIG_VBOOT_VERIFY_FIRMWARE -void *vboot_get_payload(int *len) +void *vboot_get_payload(size_t *len) { struct vboot_handoff *vboot_handoff; struct firmware_component *fwc; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index d241085..ae715dc 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -48,7 +48,7 @@ void init_chromeos(int bootmode); #if CONFIG_VBOOT_VERIFY_FIRMWARE struct romstage_handoff; void vboot_verify_firmware(struct romstage_handoff *handoff); -void *vboot_get_payload(int *len); +void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); #endif

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Patch set updated for coreboot: 6f72df2 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4674 -gerrit commit 6f72df247d4895810c1ab8a6322487e139093ffe Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 12 14:12:15 2014 +0100 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file Number one reason to use cbfs_get_file was to get file length. With prvious patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/via/nano/update_ucode.c | 19 +++++++++---------- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 10 ++++++---- src/mainboard/google/bolt/romstage.c | 12 +++++++----- src/mainboard/google/butterfly/mainboard.c | 10 ++++++---- src/mainboard/google/falco/romstage.c | 12 +++++++----- src/mainboard/google/link/romstage.c | 12 +++++++----- src/mainboard/google/peppy/romstage.c | 12 +++++++----- src/mainboard/google/slippy/romstage.c | 12 +++++++----- src/mainboard/samsung/lumpy/romstage.c | 10 +++++----- src/northbridge/intel/i82830/vga.c | 18 +++--------------- src/southbridge/intel/lynxpoint/spi_loading.c | 16 ++++------------ src/vendorcode/google/chromeos/chromeos.c | 2 +- src/vendorcode/google/chromeos/chromeos.h | 2 +- 13 files changed, 70 insertions(+), 77 deletions(-) diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 7471928..981cc36 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -102,24 +102,23 @@ unsigned int nano_update_ucode(void) { size_t i; unsigned int n_updates = 0; - const struct cbfs_file *cbfs_ucode; u32 fms = cpuid_eax(0x1); + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + u32 *ucode_data; + size_t ucode_len; - cbfs_ucode = cbfs_get_file(CBFS_DEFAULT_MEDIA, "cpu_microcode_blob.bin"); + ucode_data = cbfs_get_file(CBFS_DEFAULT_MEDIA, "cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, &ucode_len); /* Oops, did you forget to include the microcode ? */ - if(cbfs_ucode == NULL) { + if(ucode_data == NULL) { printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " "Aborting microcode updates\n"); return 0; } - /* Considering we are running with eXecute-In-Place (XIP), there's no - * need to worry that accessing data from ROM will slow us down. - * Microcode data should be aligned to a 4-byte boundary, but CBFS - * already does that for us (Do you, CBFS?) */ - const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); - const u32 ucode_len = ntohl(cbfs_ucode->len); - /* We might do a lot of loops searching for the microcode updates, but * keep in mind, nano_ucode_is_valid searches for the signature before * doing anything else. */ diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index bd593d8..ada7853 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -444,16 +444,18 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) if (info->DimmId != 0) return AGESA_UNSUPPORTED; - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("file [spd.bin] not found in CBFS"); - if (spd_file->len < SPD_SIZE) + if (spd_file_len < SPD_SIZE) die("Missing SPD data."); - memcpy((char*)info->Buffer, (char*)CBFS_SUBHEADER(spd_file), SPD_SIZE); + memcpy((char*)info->Buffer, spd_file, SPD_SIZE); u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE); diff --git a/src/mainboard/google/bolt/romstage.c b/src/mainboard/google/bolt/romstage.c index a74f10c..b698ec3 100644 --- a/src/mainboard/google/bolt/romstage.c +++ b/src/mainboard/google/bolt/romstage.c @@ -73,25 +73,27 @@ const struct rcba_config_instruction rcba_config[] = { /* Copy SPD data for on-board memory */ static void copy_spd(struct pei_data *peid) { - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; int spd_index = 0; /* No GPIO selection, force index 0 for now */ printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 1623fe0..f65d14c 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -299,7 +299,7 @@ static void verb_setup(void) static void mainboard_init(device_t dev) { u32 search_address = 0x0; - u32 search_length = -1; + size_t search_length = -1; u16 io_base = 0; struct device *ethernet_dev = NULL; #if CONFIG_CHROMEOS @@ -307,10 +307,12 @@ static void mainboard_init(device_t dev) search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); search_address = (unsigned long)(*vpd_region_ptr); #else - struct cbfs_file *vpd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "vpd.bin"); + void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin", &search_length); if (vpd_file) { - search_length = ntohl(vpd_file->len); - search_address = (unsigned long)CBFS_SUBHEADER(vpd_file); + search_address = (unsigned long)vpd_file; + } else { + search_length = -1; + search_address = 0; } #endif diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 0ad4b97..ca843e8 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -75,20 +75,22 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); /* Index 0-2 are 4GB config with both CH0 and CH1 @@ -98,7 +100,7 @@ static void copy_spd(struct pei_data *peid) peid->dimm_channel1_disabled = 3; memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 27a22f7..1aa309a 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -125,24 +125,26 @@ static void rcba_config(void) static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {41, 42, 43, 10, -1}; - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index c6696c0..4e72326 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -78,10 +78,12 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); @@ -101,17 +103,17 @@ static void copy_spd(struct pei_data *peid) break; } - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fdbac97..e2fa011 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -76,24 +76,26 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 6c87f88..a4f0c42 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -182,8 +182,8 @@ void main(unsigned long bist) }; typedef const uint8_t spd_blob[256]; - struct cbfs_file *spd_file; spd_blob *spd_data; + size_t spd_file_len; timestamp_init(get_initial_timestamp()); @@ -289,12 +289,12 @@ void main(unsigned long bist) break; } - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); - if (!spd_file) + spd_data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); + if (!spd_data) die("SPD data not found."); - if (spd_file->len < (spd_index + 1) * 256) + if (spd_file_len < (spd_index + 1) * 256) die("Missing SPD data."); - spd_data = (spd_blob *)CBFS_SUBHEADER(spd_file); // leave onboard dimm address at f0, and copy spd data there. memcpy(pei_data.spd_data[0], spd_data[spd_index], 256); diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index 49bfa34..61bb010 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -32,21 +32,9 @@ static void vga_init(device_t dev) { printk(BIOS_INFO, "Starting Graphics Initialization\n"); - struct cbfs_file *file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "mbi.bin"); - void *mbi = NULL; - unsigned int mbi_len = 0; - - if (file) { - if (ntohl(file->type) != CBFS_TYPE_MBI) { - printk(BIOS_INFO, "CBFS: MBI binary is of type %x instead of" - "type %x\n", file->type, CBFS_TYPE_MBI); - } else { - mbi = (void *) CBFS_SUBHEADER(file); - mbi_len = ntohl(file->len); - } - } else { - printk(BIOS_INFO, "Could not find MBI.\n"); - } + size_t mbi_len; + void *mbi = cbfs_get_file(CBFS_DEFAULT_MEDIA, "mbi.bin", + CBFS_TYPE_MBI, &mbi_len); if (mbi && mbi_len) { /* The GDT or coreboot table is going to live here. But diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c index 1ae7a26..57e3af8 100644 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ b/src/southbridge/intel/lynxpoint/spi_loading.c @@ -28,7 +28,7 @@ #if CONFIG_VBOOT_VERIFY_FIRMWARE #include <vendorcode/google/chromeos/chromeos.h> #else -static inline void *vboot_get_payload(int *len) { return NULL; } +static inline void *vboot_get_payload(size_t *len) { return NULL; } #endif #define CACHELINE_SIZE 64 @@ -73,26 +73,18 @@ static inline void *spi_mirror(void *file_start, int file_len) void *cbfs_load_payload(struct cbfs_media *media, const char *name) { - int file_len; + size_t file_len; void *file_start; - struct cbfs_file *file; file_start = vboot_get_payload(&file_len); if (file_start != NULL) return spi_mirror(file_start, file_len); - file = cbfs_get_file(media, name); + file_start = cbfs_get_file_content(media, name, CBFS_TYPE_PAYLOAD, &file_len); - if (file == NULL) + if (file_start == NULL) return NULL; - if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) - return NULL; - - file_len = ntohl(file->len); - - file_start = CBFS_SUBHEADER(file); - return spi_mirror(file_start, file_len); } diff --git a/src/vendorcode/google/chromeos/chromeos.c b/src/vendorcode/google/chromeos/chromeos.c index 828cfd2..54fe8db 100644 --- a/src/vendorcode/google/chromeos/chromeos.c +++ b/src/vendorcode/google/chromeos/chromeos.c @@ -82,7 +82,7 @@ int recovery_mode_enabled(void) } #if CONFIG_VBOOT_VERIFY_FIRMWARE -void *vboot_get_payload(int *len) +void *vboot_get_payload(size_t *len) { struct vboot_handoff *vboot_handoff; struct firmware_component *fwc; diff --git a/src/vendorcode/google/chromeos/chromeos.h b/src/vendorcode/google/chromeos/chromeos.h index d241085..ae715dc 100644 --- a/src/vendorcode/google/chromeos/chromeos.h +++ b/src/vendorcode/google/chromeos/chromeos.h @@ -48,7 +48,7 @@ void init_chromeos(int bootmode); #if CONFIG_VBOOT_VERIFY_FIRMWARE struct romstage_handoff; void vboot_verify_firmware(struct romstage_handoff *handoff); -void *vboot_get_payload(int *len); +void *vboot_get_payload(size_t *len); /* Returns 0 on success < 0 on error. */ int vboot_get_handoff_info(void **addr, uint32_t *size); #endif

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New patch to review for coreboot: 387c859 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4674 -gerrit commit 387c859a854187daac9b151f97302d24ae16afc2 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 12 14:12:15 2014 +0100 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file Number one reason to use cbfs_get_file was to get file length. With prvious patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/cpu/via/nano/update_ucode.c | 19 +++++++++---------- src/mainboard/gizmosphere/gizmo/BiosCallOuts.c | 10 ++++++---- src/mainboard/google/bolt/romstage.c | 12 +++++++----- src/mainboard/google/butterfly/mainboard.c | 10 ++++++---- src/mainboard/google/falco/romstage.c | 12 +++++++----- src/mainboard/google/link/romstage.c | 12 +++++++----- src/mainboard/google/peppy/romstage.c | 12 +++++++----- src/mainboard/google/slippy/romstage.c | 12 +++++++----- src/mainboard/samsung/lumpy/romstage.c | 10 +++++----- src/northbridge/intel/i82830/vga.c | 18 +++--------------- src/southbridge/intel/lynxpoint/spi_loading.c | 14 +++----------- 11 files changed, 67 insertions(+), 74 deletions(-) diff --git a/src/cpu/via/nano/update_ucode.c b/src/cpu/via/nano/update_ucode.c index 7471928..981cc36 100644 --- a/src/cpu/via/nano/update_ucode.c +++ b/src/cpu/via/nano/update_ucode.c @@ -102,24 +102,23 @@ unsigned int nano_update_ucode(void) { size_t i; unsigned int n_updates = 0; - const struct cbfs_file *cbfs_ucode; u32 fms = cpuid_eax(0x1); + /* Considering we are running with eXecute-In-Place (XIP), there's no + * need to worry that accessing data from ROM will slow us down. + * Microcode data should be aligned to a 4-byte boundary, but CBFS + * already does that for us (Do you, CBFS?) */ + u32 *ucode_data; + size_t ucode_len; - cbfs_ucode = cbfs_get_file(CBFS_DEFAULT_MEDIA, "cpu_microcode_blob.bin"); + ucode_data = cbfs_get_file(CBFS_DEFAULT_MEDIA, "cpu_microcode_blob.bin", + CBFS_TYPE_MICROCODE, &ucode_len); /* Oops, did you forget to include the microcode ? */ - if(cbfs_ucode == NULL) { + if(ucode_data == NULL) { printk(BIOS_ALERT, "WARNING: No microcode file found in CBFS. " "Aborting microcode updates\n"); return 0; } - /* Considering we are running with eXecute-In-Place (XIP), there's no - * need to worry that accessing data from ROM will slow us down. - * Microcode data should be aligned to a 4-byte boundary, but CBFS - * already does that for us (Do you, CBFS?) */ - const u32 *ucode_data = CBFS_SUBHEADER(cbfs_ucode); - const u32 ucode_len = ntohl(cbfs_ucode->len); - /* We might do a lot of loops searching for the microcode updates, but * keep in mind, nano_ucode_is_valid searches for the signature before * doing anything else. */ diff --git a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c index bd593d8..5d666aa 100755 --- a/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c +++ b/src/mainboard/gizmosphere/gizmo/BiosCallOuts.c @@ -444,16 +444,18 @@ AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr) if (info->DimmId != 0) return AGESA_UNSUPPORTED; - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "read SPD\n"); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("file [spd.bin] not found in CBFS"); - if (spd_file->len < SPD_SIZE) + if (spd_file_len < SPD_SIZE) die("Missing SPD data."); - memcpy((char*)info->Buffer, (char*)CBFS_SUBHEADER(spd_file), SPD_SIZE); + memcpy((char*)info->Buffer, spd_file, SPD_SIZE); u16 crc = spd_ddr3_calc_crc(info->Buffer, SPD_SIZE); diff --git a/src/mainboard/google/bolt/romstage.c b/src/mainboard/google/bolt/romstage.c index a74f10c..b698ec3 100644 --- a/src/mainboard/google/bolt/romstage.c +++ b/src/mainboard/google/bolt/romstage.c @@ -73,25 +73,27 @@ const struct rcba_config_instruction rcba_config[] = { /* Copy SPD data for on-board memory */ static void copy_spd(struct pei_data *peid) { - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; int spd_index = 0; /* No GPIO selection, force index 0 for now */ printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/butterfly/mainboard.c b/src/mainboard/google/butterfly/mainboard.c index 1623fe0..f65d14c 100644 --- a/src/mainboard/google/butterfly/mainboard.c +++ b/src/mainboard/google/butterfly/mainboard.c @@ -299,7 +299,7 @@ static void verb_setup(void) static void mainboard_init(device_t dev) { u32 search_address = 0x0; - u32 search_length = -1; + size_t search_length = -1; u16 io_base = 0; struct device *ethernet_dev = NULL; #if CONFIG_CHROMEOS @@ -307,10 +307,12 @@ static void mainboard_init(device_t dev) search_length = find_fmap_entry("RO_VPD", (void **)vpd_region_ptr); search_address = (unsigned long)(*vpd_region_ptr); #else - struct cbfs_file *vpd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "vpd.bin"); + void *vpd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "vpd.bin", &search_length); if (vpd_file) { - search_length = ntohl(vpd_file->len); - search_address = (unsigned long)CBFS_SUBHEADER(vpd_file); + search_address = (unsigned long)vpd_file; + } else { + search_length = -1; + search_address = 0; } #endif diff --git a/src/mainboard/google/falco/romstage.c b/src/mainboard/google/falco/romstage.c index 0ad4b97..673ceb5 100644 --- a/src/mainboard/google/falco/romstage.c +++ b/src/mainboard/google/falco/romstage.c @@ -75,20 +75,22 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_size); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); /* Index 0-2 are 4GB config with both CH0 and CH1 @@ -98,7 +100,7 @@ static void copy_spd(struct pei_data *peid) peid->dimm_channel1_disabled = 3; memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c index 27a22f7..9178eb1 100644 --- a/src/mainboard/google/link/romstage.c +++ b/src/mainboard/google/link/romstage.c @@ -125,24 +125,26 @@ static void rcba_config(void) static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {41, 42, 43, 10, -1}; - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; int spd_index = get_gpios(gpio_vector); printk(BIOS_DEBUG, "spd index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_size); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "spd index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/peppy/romstage.c b/src/mainboard/google/peppy/romstage.c index c6696c0..4e72326 100644 --- a/src/mainboard/google/peppy/romstage.c +++ b/src/mainboard/google/peppy/romstage.c @@ -78,10 +78,12 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); @@ -101,17 +103,17 @@ static void copy_spd(struct pei_data *peid) break; } - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fdbac97..e2fa011 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -76,24 +76,26 @@ static void copy_spd(struct pei_data *peid) { const int gpio_vector[] = {13, 9, 47, -1}; int spd_index = get_gpios(gpio_vector); - struct cbfs_file *spd_file; + char *spd_file; + size_t spd_file_len; printk(BIOS_DEBUG, "SPD index %d\n", spd_index); - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); + spd_file = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); if (!spd_file) die("SPD data not found."); - if (ntohl(spd_file->len) < + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file->len < sizeof(peid->spd_data[0])) + if (spd_file_len < sizeof(peid->spd_data[0])) die("Missing SPD data."); memcpy(peid->spd_data[0], - ((char*)CBFS_SUBHEADER(spd_file)) + + spd_file + spd_index * sizeof(peid->spd_data[0]), sizeof(peid->spd_data[0])); } diff --git a/src/mainboard/samsung/lumpy/romstage.c b/src/mainboard/samsung/lumpy/romstage.c index 6c87f88..a4f0c42 100644 --- a/src/mainboard/samsung/lumpy/romstage.c +++ b/src/mainboard/samsung/lumpy/romstage.c @@ -182,8 +182,8 @@ void main(unsigned long bist) }; typedef const uint8_t spd_blob[256]; - struct cbfs_file *spd_file; spd_blob *spd_data; + size_t spd_file_len; timestamp_init(get_initial_timestamp()); @@ -289,12 +289,12 @@ void main(unsigned long bist) break; } - spd_file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "spd.bin"); - if (!spd_file) + spd_data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "spd.bin", 0xab, + &spd_file_len); + if (!spd_data) die("SPD data not found."); - if (spd_file->len < (spd_index + 1) * 256) + if (spd_file_len < (spd_index + 1) * 256) die("Missing SPD data."); - spd_data = (spd_blob *)CBFS_SUBHEADER(spd_file); // leave onboard dimm address at f0, and copy spd data there. memcpy(pei_data.spd_data[0], spd_data[spd_index], 256); diff --git a/src/northbridge/intel/i82830/vga.c b/src/northbridge/intel/i82830/vga.c index 49bfa34..61bb010 100644 --- a/src/northbridge/intel/i82830/vga.c +++ b/src/northbridge/intel/i82830/vga.c @@ -32,21 +32,9 @@ static void vga_init(device_t dev) { printk(BIOS_INFO, "Starting Graphics Initialization\n"); - struct cbfs_file *file = cbfs_get_file(CBFS_DEFAULT_MEDIA, "mbi.bin"); - void *mbi = NULL; - unsigned int mbi_len = 0; - - if (file) { - if (ntohl(file->type) != CBFS_TYPE_MBI) { - printk(BIOS_INFO, "CBFS: MBI binary is of type %x instead of" - "type %x\n", file->type, CBFS_TYPE_MBI); - } else { - mbi = (void *) CBFS_SUBHEADER(file); - mbi_len = ntohl(file->len); - } - } else { - printk(BIOS_INFO, "Could not find MBI.\n"); - } + size_t mbi_len; + void *mbi = cbfs_get_file(CBFS_DEFAULT_MEDIA, "mbi.bin", + CBFS_TYPE_MBI, &mbi_len); if (mbi && mbi_len) { /* The GDT or coreboot table is going to live here. But diff --git a/src/southbridge/intel/lynxpoint/spi_loading.c b/src/southbridge/intel/lynxpoint/spi_loading.c index 1ae7a26..06dd9ac 100644 --- a/src/southbridge/intel/lynxpoint/spi_loading.c +++ b/src/southbridge/intel/lynxpoint/spi_loading.c @@ -73,26 +73,18 @@ static inline void *spi_mirror(void *file_start, int file_len) void *cbfs_load_payload(struct cbfs_media *media, const char *name) { - int file_len; + size_t file_len; void *file_start; - struct cbfs_file *file; file_start = vboot_get_payload(&file_len); if (file_start != NULL) return spi_mirror(file_start, file_len); - file = cbfs_get_file(media, name); + file_start = cbfs_get_file(media, name, CBFS_TYPE_PAYLOAD, &file_len); - if (file == NULL) + if (file_start == NULL) return NULL; - if (ntohl(file->type) != CBFS_TYPE_PAYLOAD) - return NULL; - - file_len = ntohl(file->len); - - file_start = CBFS_SUBHEADER(file); - return spi_mirror(file_start, file_len); }

1 0

New patch to review for coreboot: 17c0cd1 AMD K8/fam10: Fix CBMEM on S3 resume
by Kyösti Mälkki 12 Jan '14

12 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4673 -gerrit commit 17c0cd1583f64b84f401baea4e2290e0dc7e5774 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jan 12 14:38:33 2014 +0200 AMD K8/fam10: Fix CBMEM on S3 resume Change to use cbmem_recovery() to wipe CBMEM region and reset ACPI wakeup if CBMEM TOC was not found. Change-Id: Ic362253eaa00bd442d4cc0514632f9096e20bfa6 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/post_cache_as_ram.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c index 81175da..f74f915 100644 --- a/src/cpu/amd/car/post_cache_as_ram.c +++ b/src/cpu/amd/car/post_cache_as_ram.c @@ -38,7 +38,7 @@ static inline void *backup_resume(void) { if (!suspend) return NULL; - if (!cbmem_reinit()) + if (cbmem_recovery(1)) return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);

1 0

New patch to review for coreboot: f8eee39 AMD AGESA: Fix CBMEM on S3 resume
by Kyösti Mälkki 12 Jan '14

12 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4672 -gerrit commit f8eee39292078febb98863c60078cf2b0617d338 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Jan 12 14:38:24 2014 +0200 AMD AGESA: Fix CBMEM on S3 resume Change to use cbmem_recovery() to wipe CBMEM region and reset ACPI wakeup if CBMEM TOC was not found. Change-Id: I6648570d76b5c137f50addcc5bce9c126d179c65 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/s3_resume.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/amd/agesa/s3_resume.c b/src/cpu/amd/agesa/s3_resume.c index ef19b53..558fc75 100644 --- a/src/cpu/amd/agesa/s3_resume.c +++ b/src/cpu/amd/agesa/s3_resume.c @@ -111,7 +111,7 @@ inline void *backup_resume(void) { void *resume_backup_memory; - if (!cbmem_reinit()) + if (cbmem_recovery(1)) return NULL; resume_backup_memory = cbmem_find(CBMEM_ID_RESUME);

1 0

Patch set updated for coreboot: 75659dc CBMEM: Rename cbmem_reinit()
by Kyösti Mälkki 12 Jan '14

12 Jan '14

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4669 -gerrit commit 75659dcb846a8de7da984d83a84ef7c6d8d33e5b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jan 4 08:46:32 2014 +0200 CBMEM: Rename cbmem_reinit() This function does not really initialize anything, but only checks for the TOC. Change-Id: I9d100d1823a0b630f5d1175e42a6a15f45266de4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/cbmem.h | 2 -- src/lib/cbmem.c | 4 ++-- 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/include/cbmem.h b/src/include/cbmem.h index eff1895..9e894a9 100644 --- a/src/include/cbmem.h +++ b/src/include/cbmem.h @@ -145,8 +145,6 @@ void backup_top_of_ram(uint64_t ramtop); void cbmem_late_set_table(uint64_t base, uint64_t size); #endif -int cbmem_reinit(void); - void get_cbmem_table(uint64_t *base, uint64_t *size); struct cbmem_entry *get_cbmem_toc(void); diff --git a/src/lib/cbmem.c b/src/lib/cbmem.c index 704733f..5fe8216 100644 --- a/src/lib/cbmem.c +++ b/src/lib/cbmem.c @@ -119,7 +119,7 @@ static void cbmem_initialize_empty(void) }; } -int cbmem_reinit(void) +static int cbmem_check_toc(void) { uint64_t baseaddr, size; struct cbmem_entry *cbmem_toc; @@ -220,7 +220,7 @@ void *cbmem_find(u32 id) /* Returns True if it was not initialized before. */ int cbmem_recovery(int is_wakeup) { - int found = cbmem_reinit(); + int found = cbmem_check_toc(); int wipe = 0; #if defined(__PRE_RAM__) && CONFIG_EARLY_CBMEM_INIT

1 0

Patch set updated for coreboot: 14cdec5 lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4659 -gerrit commit 14cdec5490597e0933bf67cbd4c63d203989206d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 12 13:45:52 2014 +0100 lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/oprom/realmode/x86.c | 3 ++- src/device/oprom/yabel/vbe.c | 3 ++- src/drivers/pc80/mc146818rtc.c | 4 ++-- src/include/cbfs_core.h | 2 +- src/lib/cbfs.c | 8 ++++---- src/lib/cbfs_core.c | 9 ++++++++- src/lib/coreboot_table.c | 2 +- src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c | 2 +- src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c | 2 +- src/northbridge/intel/fsp_sandybridge/mrccache.c | 6 +++--- src/northbridge/intel/haswell/raminit.c | 2 +- src/northbridge/intel/sandybridge/mrccache.c | 9 ++++----- src/northbridge/intel/sandybridge/raminit.c | 2 +- src/vendorcode/google/chromeos/vboot_loader.c | 2 +- 14 files changed, 32 insertions(+), 24 deletions(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 4385c03..e57f1c0 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -273,7 +273,8 @@ void vbe_set_graphics(void) decdata = malloc(sizeof(*decdata)); unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH); + CBFS_TYPE_BOOTSPLASH, + NULL); if (!jpeg) { printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); return; diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 8658b77..333bdb4 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -727,7 +727,8 @@ void vbe_set_graphics(void) unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH); + CBFS_TYPE_BOOTSPLASH, + NULL); if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index bd94bd2..51cd6c3 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -193,7 +193,7 @@ enum cb_err get_option(void *dest, const char *name) /* find the requested entry record */ ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); @@ -272,7 +272,7 @@ enum cb_err set_option(const char *name, void *value) /* find the requested entry record */ ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n"); return CB_CMOS_LAYOUT_NOT_FOUND; diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 04b5dd7..a1d8127 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -222,7 +222,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); /* returns pointer to file content inside CBFS after if type is correct */ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type); + int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 1f44695..e38f856 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -96,7 +96,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, tohex16(device, name+8); orom = (struct cbfs_optionrom *) - cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM); + cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); if (orom == NULL) return NULL; @@ -187,7 +187,7 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, const struct cbmem_entry *ramstage_entry; stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); + cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); if (stage == NULL) return (void *) -1; @@ -257,7 +257,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); + cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uint32_t entry; @@ -302,7 +302,7 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) return payload; payload = (struct cbfs_payload *)cbfs_get_file_content( - media, name, CBFS_TYPE_PAYLOAD); + media, name, CBFS_TYPE_PAYLOAD, NULL); return payload; } #endif diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 612fef2..839b994 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -173,10 +173,14 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) return NULL; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type) +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, + int type, size_t *sz) { struct cbfs_file *file = cbfs_get_file(media, name); + if (sz) + *sz = 0; + if (file == NULL) { ERROR("Could not find file '%s'.\n", name); return NULL; @@ -188,6 +192,9 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type return NULL; } + if (sz) + *sz = ntohl(file->len); + return (void *)CBFS_SUBHEADER(file); } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 772729a..f433e86 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -505,7 +505,7 @@ unsigned long write_coreboot_table( { struct cmos_option_table *option_table = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a lb_record... */ diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index 38bf975..cf84b39 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -428,7 +428,7 @@ AGESA_STATUS fam15tn_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *Con GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; pVbiosImageInfo->ImagePtr = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM); + CBFS_TYPE_OPTIONROM, NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c b/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c index eed8d40..b290931 100644 --- a/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c +++ b/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c @@ -401,7 +401,7 @@ AGESA_STATUS fam16kb_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *Con GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; pVbiosImageInfo->ImagePtr = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM); + CBFS_TYPE_OPTIONROM, NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/northbridge/intel/fsp_sandybridge/mrccache.c b/src/northbridge/intel/fsp_sandybridge/mrccache.c index a793880..b8893ae 100644 --- a/src/northbridge/intel/fsp_sandybridge/mrccache.c +++ b/src/northbridge/intel/fsp_sandybridge/mrccache.c @@ -58,10 +58,10 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; - region_size = CONFIG_MRC_CACHE_SIZE; + size_t region_size; *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", 0xac); + "mrc.cache", 0xac, + &region_size); return region_size; } diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index e916c5e..5944eeb 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -170,7 +170,7 @@ void sdram_initialize(struct pei_data *pei_data) /* Locate and call UEFI System Agent binary. */ entry = (unsigned long)cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab); + CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL); if (entry) { int rv; asm volatile ( diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index b8120a8..5d7c49b 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -66,16 +66,15 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; #if CONFIG_CHROMEOS - region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else - region_size = CONFIG_MRC_CACHE_SIZE; + size_t region_size; *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", 0xac); + "mrc.cache", 0xac, &region_size); + return region_size; #endif - return region_size; } /* diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 333a6b5..6e52965 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -253,7 +253,7 @@ void sdram_initialize(struct pei_data *pei_data) /* Locate and call UEFI System Agent binary. */ /* TODO make MRC blob (0xab?) defined in cbfs_core.h. */ entry = (unsigned long)cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab); + CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL); if (entry) { int rv; asm volatile ( diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 4a0c36c..91f6237 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -48,7 +48,7 @@ static void vboot_run_stub(struct vboot_context *context) stage = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/vboot", - CBFS_TYPE_STAGE); + CBFS_TYPE_STAGE, NULL); if (stage == NULL) return;

1 0

Patch set updated for coreboot: cb4ffbc lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4659 -gerrit commit cb4ffbca2356fbabaccad1e9efd6abc7099b6573 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 12 13:45:52 2014 +0100 lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/device/oprom/realmode/x86.c | 3 ++- src/device/oprom/yabel/vbe.c | 3 ++- src/drivers/pc80/mc146818rtc.c | 4 ++-- src/include/cbfs_core.h | 2 +- src/lib/cbfs.c | 8 ++++---- src/lib/cbfs_core.c | 9 ++++++++- src/lib/coreboot_table.c | 2 +- src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c | 2 +- src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c | 2 +- src/northbridge/intel/fsp_sandybridge/mrccache.c | 6 +++--- src/northbridge/intel/haswell/raminit.c | 2 +- src/northbridge/intel/sandybridge/mrccache.c | 9 ++++----- src/vendorcode/google/chromeos/vboot_loader.c | 2 +- 13 files changed, 31 insertions(+), 23 deletions(-) diff --git a/src/device/oprom/realmode/x86.c b/src/device/oprom/realmode/x86.c index 4385c03..e57f1c0 100644 --- a/src/device/oprom/realmode/x86.c +++ b/src/device/oprom/realmode/x86.c @@ -273,7 +273,8 @@ void vbe_set_graphics(void) decdata = malloc(sizeof(*decdata)); unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH); + CBFS_TYPE_BOOTSPLASH, + NULL); if (!jpeg) { printk(BIOS_DEBUG, "VBE: No bootsplash found.\n"); return; diff --git a/src/device/oprom/yabel/vbe.c b/src/device/oprom/yabel/vbe.c index 8658b77..333bdb4 100644 --- a/src/device/oprom/yabel/vbe.c +++ b/src/device/oprom/yabel/vbe.c @@ -727,7 +727,8 @@ void vbe_set_graphics(void) unsigned char *jpeg = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "bootsplash.jpg", - CBFS_TYPE_BOOTSPLASH); + CBFS_TYPE_BOOTSPLASH, + NULL); if (!jpeg) { DEBUG_PRINTF_VBE("Could not find bootsplash.jpg\n"); return; diff --git a/src/drivers/pc80/mc146818rtc.c b/src/drivers/pc80/mc146818rtc.c index bd94bd2..51cd6c3 100644 --- a/src/drivers/pc80/mc146818rtc.c +++ b/src/drivers/pc80/mc146818rtc.c @@ -193,7 +193,7 @@ enum cb_err get_option(void *dest, const char *name) /* find the requested entry record */ ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "RTC: cmos_layout.bin could not be found. " "Options are disabled\n"); @@ -272,7 +272,7 @@ enum cb_err set_option(const char *name, void *value) /* find the requested entry record */ ct = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (!ct) { printk(BIOS_ERR, "cmos_layout.bin could not be found. Options are disabled\n"); return CB_CMOS_LAYOUT_NOT_FOUND; diff --git a/src/include/cbfs_core.h b/src/include/cbfs_core.h index 04b5dd7..a1d8127 100644 --- a/src/include/cbfs_core.h +++ b/src/include/cbfs_core.h @@ -222,7 +222,7 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name); /* returns pointer to file content inside CBFS after if type is correct */ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, - int type); + int type, size_t *sz); /* returns decompressed size on success, 0 on failure */ int cbfs_decompress(int algo, void *src, void *dst, int len); diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 1f44695..e38f856 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -96,7 +96,7 @@ void *cbfs_load_optionrom(struct cbfs_media *media, uint16_t vendor, tohex16(device, name+8); orom = (struct cbfs_optionrom *) - cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM); + cbfs_get_file_content(media, name, CBFS_TYPE_OPTIONROM, NULL); if (orom == NULL) return NULL; @@ -187,7 +187,7 @@ static void *load_stage_from_cbfs(struct cbfs_media *media, const char *name, const struct cbmem_entry *ramstage_entry; stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); + cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); if (stage == NULL) return (void *) -1; @@ -257,7 +257,7 @@ void * cbfs_load_stage(struct cbfs_media *media, const char *name) void * cbfs_load_stage(struct cbfs_media *media, const char *name) { struct cbfs_stage *stage = (struct cbfs_stage *) - cbfs_get_file_content(media, name, CBFS_TYPE_STAGE); + cbfs_get_file_content(media, name, CBFS_TYPE_STAGE, NULL); /* this is a mess. There is no ntohll. */ /* for now, assume compatible byte order until we solve this. */ uint32_t entry; @@ -302,7 +302,7 @@ void *cbfs_load_payload(struct cbfs_media *media, const char *name) return payload; payload = (struct cbfs_payload *)cbfs_get_file_content( - media, name, CBFS_TYPE_PAYLOAD); + media, name, CBFS_TYPE_PAYLOAD, NULL); return payload; } #endif diff --git a/src/lib/cbfs_core.c b/src/lib/cbfs_core.c index 612fef2..839b994 100644 --- a/src/lib/cbfs_core.c +++ b/src/lib/cbfs_core.c @@ -173,10 +173,14 @@ struct cbfs_file *cbfs_get_file(struct cbfs_media *media, const char *name) return NULL; } -void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type) +void *cbfs_get_file_content(struct cbfs_media *media, const char *name, + int type, size_t *sz) { struct cbfs_file *file = cbfs_get_file(media, name); + if (sz) + *sz = 0; + if (file == NULL) { ERROR("Could not find file '%s'.\n", name); return NULL; @@ -188,6 +192,9 @@ void *cbfs_get_file_content(struct cbfs_media *media, const char *name, int type return NULL; } + if (sz) + *sz = ntohl(file->len); + return (void *)CBFS_SUBHEADER(file); } diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 772729a..f433e86 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -505,7 +505,7 @@ unsigned long write_coreboot_table( { struct cmos_option_table *option_table = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "cmos_layout.bin", - CBFS_COMPONENT_CMOS_LAYOUT); + CBFS_COMPONENT_CMOS_LAYOUT, NULL); if (option_table) { struct lb_record *rec_dest = lb_new_record(head); /* Copy the option config table, it's already a lb_record... */ diff --git a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c index 38bf975..cf84b39 100644 --- a/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c +++ b/src/northbridge/amd/agesa/family15tn/fam15tn_callouts.c @@ -428,7 +428,7 @@ AGESA_STATUS fam15tn_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *Con GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; pVbiosImageInfo->ImagePtr = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM); + CBFS_TYPE_OPTIONROM, NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c b/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c index eed8d40..b290931 100644 --- a/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c +++ b/src/northbridge/amd/agesa/family16kb/fam16kb_callouts.c @@ -401,7 +401,7 @@ AGESA_STATUS fam16kb_HookGfxGetVbiosImage(UINT32 Func, UINT32 FchData, VOID *Con GFX_VBIOS_IMAGE_INFO *pVbiosImageInfo = (GFX_VBIOS_IMAGE_INFO *)ConfigPrt; pVbiosImageInfo->ImagePtr = cbfs_get_file_content( CBFS_DEFAULT_MEDIA, "pci"CONFIG_VGA_BIOS_ID".rom", - CBFS_TYPE_OPTIONROM); + CBFS_TYPE_OPTIONROM, NULL); /* printk(BIOS_DEBUG, "IMGptr=%x\n", pVbiosImageInfo->ImagePtr); */ return pVbiosImageInfo->ImagePtr == NULL ? AGESA_WARNING : AGESA_SUCCESS; } diff --git a/src/northbridge/intel/fsp_sandybridge/mrccache.c b/src/northbridge/intel/fsp_sandybridge/mrccache.c index a793880..b8893ae 100644 --- a/src/northbridge/intel/fsp_sandybridge/mrccache.c +++ b/src/northbridge/intel/fsp_sandybridge/mrccache.c @@ -58,10 +58,10 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; - region_size = CONFIG_MRC_CACHE_SIZE; + size_t region_size; *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", 0xac); + "mrc.cache", 0xac, + &region_size); return region_size; } diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index e916c5e..5944eeb 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -170,7 +170,7 @@ void sdram_initialize(struct pei_data *pei_data) /* Locate and call UEFI System Agent binary. */ entry = (unsigned long)cbfs_get_file_content( - CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab); + CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL); if (entry) { int rv; asm volatile ( diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index b8120a8..5d7c49b 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -66,16 +66,15 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; #if CONFIG_CHROMEOS - region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else - region_size = CONFIG_MRC_CACHE_SIZE; + size_t region_size; *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", 0xac); + "mrc.cache", 0xac, &region_size); + return region_size; #endif - return region_size; } /* diff --git a/src/vendorcode/google/chromeos/vboot_loader.c b/src/vendorcode/google/chromeos/vboot_loader.c index 4a0c36c..91f6237 100644 --- a/src/vendorcode/google/chromeos/vboot_loader.c +++ b/src/vendorcode/google/chromeos/vboot_loader.c @@ -48,7 +48,7 @@ static void vboot_run_stub(struct vboot_context *context) stage = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/vboot", - CBFS_TYPE_STAGE); + CBFS_TYPE_STAGE, NULL); if (stage == NULL) return;

1 0

Patch set updated for coreboot: fec5757 sandybridge/nehalem: Determine mrc.cache size from CBFS rather than hardcoding
by Vladimir Serbinenko 12 Jan '14

12 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4659 -gerrit commit fec5757807cbc3cdf8fd34018aee3f4aefd9c1fa Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sat Jan 11 07:52:17 2014 +0100 sandybridge/nehalem: Determine mrc.cache size from CBFS rather than hardcoding The hardcoded value was 0 on X201. There shouldn't be hardcoding at all, hence this patch. Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/sandybridge/mrccache.c | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index b8120a8..a37a5ea 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -66,16 +66,29 @@ static int is_mrc_cache(struct mrc_data_container *mrc_cache) */ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr) { - u32 region_size; #if CONFIG_CHROMEOS - region_size = find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); + return find_fmap_entry("RW_MRC_CACHE", (void **)mrc_region_ptr); #else - region_size = CONFIG_MRC_CACHE_SIZE; - *mrc_region_ptr = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, - "mrc.cache", 0xac); -#endif + struct cbfs_file *file; + const char *cache_name = "mrc.cache"; + + *mrc_region_ptr = NULL; + file = cbfs_get_file(CBFS_DEFAULT_MEDIA, cache_name); + + if (file == NULL) { + printk(BIOS_ERR, "Could not find file '%s'.\n", cache_name); + return 0; + } - return region_size; + if (ntohl(file->type) != 0xac) { + printk(BIOS_ERR, + "File '%s' is of type %x, but we requested %x.\n", + cache_name, ntohl(file->type), 0xac); + return 0; + } + *mrc_region_ptr = (void *)CBFS_SUBHEADER(file); + return ntohl(file->len); +#endif } /*

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coreboot-gerrit January 2014