coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

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1801 discussions

Patch set updated for coreboot: 4688df6 xpowers/axp209: Allow voltages to be sepecified in devicetree.cb
by Alexandru Gagniuc 10 Jan '14

10 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4637 -gerrit commit 4688df68f90204a6d80ea8abce94db0d99e85ed0 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 9 20:07:10 2014 -0600 xpowers/axp209: Allow voltages to be sepecified in devicetree.cb This allows system voltages to be specified uniformly, rather than hardcoding them for each board. This will be used by cubieboard in an upcoming patch. Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/xpowers/axp209/axp209.c | 13 +++++++++++++ src/drivers/xpowers/axp209/chip.h | 21 +++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c index 68ab8a5..9f77cf6 100644 --- a/src/drivers/xpowers/axp209/axp209.c +++ b/src/drivers/xpowers/axp209/axp209.c @@ -9,7 +9,9 @@ */ #include "axp209.h" +#include "chip.h" +#include <device/device.h> #include <device/i2c.h> /* Hide these definitions from the rest of the source, so keep them here */ @@ -228,3 +230,14 @@ enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts) return CB_SUCCESS; } + +/* + * Usually, the AXP209 is enabled and configured in romstage, so there is no + * need for a full ramstage driver. Hence .enable_dev is NULL. + */ +#ifndef __PRE_RAM__ +struct chip_operations drivers_xpowers_axp209_config = { + CHIP_NAME("X-Powers AXP 209 Power Management Unit") + .enable_dev = NULL, +}; +#endif /* __PRE_RAM__ */ diff --git a/src/drivers/xpowers/axp209/chip.h b/src/drivers/xpowers/axp209/chip.h new file mode 100644 index 0000000..c19253d --- /dev/null +++ b/src/drivers/xpowers/axp209/chip.h @@ -0,0 +1,21 @@ +/* + * X-Powers AXP 209 devicetree.cb interface + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef AXP209_CHIP_H +#define AXP209_CHIP_H + +#include <types.h> + +struct drivers_xpowers_axp209_config { + u16 dcdc2_voltage_mv; /**< DCDC2 converter voltage output */ + u16 dcdc3_voltage_mv; /**< DCDC3 converter voltage output */ + u16 ldo2_voltage_mv; /**< LDO2 regulator voltage output */ + u16 ldo3_voltage_mv; /**< LDO3 regulator voltage output */ + u16 ldo4_voltage_mv; /**< LDO4 regulator voltage output */ +}; + +#endif /* AXP209_CHIP_H */

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Patch set updated for coreboot: fd1a70a cubieboard: Configure system voltages from devicetree
by Alexandru Gagniuc 10 Jan '14

10 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4640 -gerrit commit fd1a70a933ec4cdd61ab5b831f9d4f356e60f847 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 9 20:45:21 2014 -0600 cubieboard: Configure system voltages from devicetree Change-Id: I93bac9bf94f5bafcd3ff0c3d5763b31d3ee9959b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/cubietech/cubieboard/Kconfig | 1 + src/mainboard/cubietech/cubieboard/devicetree.cb | 9 ++++ src/mainboard/cubietech/cubieboard/romstage.c | 58 ++++++++++++++++++++++++ 3 files changed, 68 insertions(+) diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig index 72b797e..6cb84cf 100644 --- a/src/mainboard/cubietech/cubieboard/Kconfig +++ b/src/mainboard/cubietech/cubieboard/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_ALLWINNER_A10 select BOARD_ROMSIZE_KB_4096 + select DRIVER_XPOWERS_AXP209 config MAINBOARD_DIR string diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb index 1358777..65ea5ff 100644 --- a/src/mainboard/cubietech/cubieboard/devicetree.cb +++ b/src/mainboard/cubietech/cubieboard/devicetree.cb @@ -1,3 +1,12 @@ chip cpu/allwinner/a10 device cpu_cluster 0 on end + + chip drivers/xpowers/axp209 # AXP209 is on I²C 0 + device i2c 0x34 on end + register "dcdc2_voltage_mv" = "1400" # Vcore + register "dcdc3_voltage_mv" = "1250" # DLL Vdd + register "ldo2_voltage_mv" = "3000" # AVCC + register "ldo3_voltage_mv" = "2800" # NC? + register "ldo4_voltage_mv" = "2800" # CSI1-IO-2V8 + end end diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c index 19192cd..6d422d6 100644 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -6,9 +6,67 @@ */ #include <console/console.h> +#include <cpu/allwinner/a10/clock.h> +#include <cpu/allwinner/a10/gpio.h> +#include <cpu/allwinner/a10/twi.h> +#define __SIMPLE_DEVICE__ +#include <device/device.h> +#include <drivers/xpowers/axp209/axp209.h> +#include <drivers/xpowers/axp209/chip.h> + + +#define GPB_TWI0_FUNC 2 +#define GPB_TWI0_PINS ((1 << 0) | (1 << 1)) + +#define AXP209_BUS 0 + +static enum cb_err cubieboard_setup_power(void) +{ + enum cb_err err; + const struct device * pmu; + const struct drivers_xpowers_axp209_config *cfg; + + /* Find the AXP209 in devicetree */ + pmu = dev_find_slot_on_smbus(AXP209_BUS, AXP209_I2C_ADDR); + if (!pmu) { + printk(BIOS_ERR, "AXP209 not found in devicetree.cb\n"); + return CB_ERR; + } + + cfg = pmu->chip_info; + + /* Mux TWI0 pins */ + gpio_set_multipin_func(GPB, GPB_TWI0_PINS, GPB_TWI0_FUNC); + /* Enable TWI0 */ + a1x_periph_clock_enable(A1X_CLKEN_TWI0); + a1x_twi_init(AXP209_BUS, 400000); + + if ((err = axp209_init(AXP209_BUS)) != CB_SUCCESS) { + printk(BIOS_ERR, "PMU initialization failed\n"); + return err; + } + + if ((err = axp209_set_voltages(AXP209_BUS, cfg)) != CB_SUCCESS) { + printk(BIOS_WARNING, "Power setup incomplete: " + "CPU may hang when increasing clock\n"); + return err; + } + + printk(BIOS_SPEW, "DCDC2 %i\n", cfg->dcdc2_voltage_mv); + printk(BIOS_SPEW, "DCDC3 %i\n", cfg->dcdc3_voltage_mv); + printk(BIOS_SPEW, "LDO2 %i\n", cfg->ldo2_voltage_mv); + printk(BIOS_SPEW, "LDO3 %i\n", cfg->ldo3_voltage_mv); + printk(BIOS_SPEW, "LDO4 %i\n", cfg->ldo4_voltage_mv); + + return CB_SUCCESS; +} void main(void) { console_init(); printk(BIOS_INFO, "You have managed to succesfully load romstage.\n"); + + /* Configure power rails */ + cubieboard_setup_power(); + }

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New patch to review for coreboot: 28adef6 cubieboard: Configure system voltages from devicetree
by Alexandru Gagniuc 10 Jan '14

10 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4640 -gerrit commit 28adef663422b8218e3267113eb59fce9ded5866 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 9 20:45:21 2014 -0600 cubieboard: Configure system voltages from devicetree Change-Id: I93bac9bf94f5bafcd3ff0c3d5763b31d3ee9959b Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/mainboard/cubietech/cubieboard/Kconfig | 1 + src/mainboard/cubietech/cubieboard/devicetree.cb | 9 ++++ src/mainboard/cubietech/cubieboard/romstage.c | 66 ++++++++++++++++++++++++ 3 files changed, 76 insertions(+) diff --git a/src/mainboard/cubietech/cubieboard/Kconfig b/src/mainboard/cubietech/cubieboard/Kconfig index 72b797e..6cb84cf 100644 --- a/src/mainboard/cubietech/cubieboard/Kconfig +++ b/src/mainboard/cubietech/cubieboard/Kconfig @@ -5,6 +5,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_ALLWINNER_A10 select BOARD_ROMSIZE_KB_4096 + select DRIVER_XPOWERS_AXP209 config MAINBOARD_DIR string diff --git a/src/mainboard/cubietech/cubieboard/devicetree.cb b/src/mainboard/cubietech/cubieboard/devicetree.cb index 1358777..65ea5ff 100644 --- a/src/mainboard/cubietech/cubieboard/devicetree.cb +++ b/src/mainboard/cubietech/cubieboard/devicetree.cb @@ -1,3 +1,12 @@ chip cpu/allwinner/a10 device cpu_cluster 0 on end + + chip drivers/xpowers/axp209 # AXP209 is on I²C 0 + device i2c 0x34 on end + register "dcdc2_voltage_mv" = "1400" # Vcore + register "dcdc3_voltage_mv" = "1250" # DLL Vdd + register "ldo2_voltage_mv" = "3000" # AVCC + register "ldo3_voltage_mv" = "2800" # NC? + register "ldo4_voltage_mv" = "2800" # CSI1-IO-2V8 + end end diff --git a/src/mainboard/cubietech/cubieboard/romstage.c b/src/mainboard/cubietech/cubieboard/romstage.c index 19192cd..744752b 100644 --- a/src/mainboard/cubietech/cubieboard/romstage.c +++ b/src/mainboard/cubietech/cubieboard/romstage.c @@ -6,9 +6,75 @@ */ #include <console/console.h> +#include <types.h> +#define __SIMPLE_DEVICE__ +#include <device/device.h> +#include <cbfs.h> +#include <cpu/allwinner/a10/clock.h> +#include <cpu/allwinner/a10/gpio.h> +#include <cpu/allwinner/a10/twi.h> +#include <arch/stages.h> +#include <drivers/xpowers/axp209/axp209.h> +#include <drivers/xpowers/axp209/chip.h> + + +#define GPB_TWI0_FUNC 2 +#define GPB_TWI0_PINS ((1 << 0) | (1 << 1)) + +#define AXP209_BUS 0 + +static enum cb_err cubieboard_setup_power(void) +{ + enum cb_err err; + const struct device * pmu; + const struct drivers_xpowers_axp209_config *cfg; + + /* Find the AXP209 in devicetree */ + pmu = dev_find_slot_on_smbus(AXP209_BUS, AXP209_I2C_ADDR); + if (!pmu) { + printk(BIOS_ERR, "AXP209 not found in devicetree.cb\n"); + return CB_ERR; + } + + cfg = pmu->chip_info; + + /* Mux TWI0 pins */ + gpio_set_multipin_func(GPB, GPB_TWI0_PINS, GPB_TWI0_FUNC); + /* Enable TWI0 */ + a1x_periph_clock_enable(A1X_CLKEN_TWI0); + a1x_twi_init(AXP209_BUS, 400000); + + if ((err = axp209_init(AXP209_BUS)) != CB_SUCCESS) { + printk(BIOS_ERR, "PMU initialization failed\n"); + return err; + } + + if ((err = axp209_set_voltages(AXP209_BUS, cfg)) != CB_SUCCESS) { + printk(BIOS_WARNING, "Power setup incomplete: " + "CPU may hang when increasing clock\n"); + return err; + } + + printk(BIOS_SPEW, "DCDC2 %i\n", cfg->dcdc2_voltage_mv); + printk(BIOS_SPEW, "DCDC3 %i\n", cfg->dcdc3_voltage_mv); + printk(BIOS_SPEW, "LDO2 %i\n", cfg->ldo2_voltage_mv); + printk(BIOS_SPEW, "LDO3 %i\n", cfg->ldo3_voltage_mv); + printk(BIOS_SPEW, "LDO4 %i\n", cfg->ldo4_voltage_mv); + + return CB_SUCCESS; +} void main(void) { + void *entry; console_init(); printk(BIOS_INFO, "You have managed to succesfully load romstage.\n"); + + /* Configure power rails */ + cubieboard_setup_power(); + + entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram"); + printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry); + + stage_exit(entry); }

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New patch to review for coreboot: cb2dc43 cpu/allwinner/a10: Clean up include order in Makefile.inc
by Alexandru Gagniuc 10 Jan '14

10 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4639 -gerrit commit cb2dc43abdad95f81b9c46c57c5408c2b9624a2b Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 9 20:42:13 2014 -0600 cpu/allwinner/a10: Clean up include order in Makefile.inc Alphabetize the sources for each stage (bootblock, rom, ram), and include twi.c in both romstage and ramstage. Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/cpu/allwinner/a10/Makefile.inc | 20 ++++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-) diff --git a/src/cpu/allwinner/a10/Makefile.inc b/src/cpu/allwinner/a10/Makefile.inc index 3e7b535..240986e 100644 --- a/src/cpu/allwinner/a10/Makefile.inc +++ b/src/cpu/allwinner/a10/Makefile.inc @@ -1,23 +1,27 @@ +bootblock-y += bootblock_media.c bootblock-y += clock.c -bootblock-y += raminit.c bootblock-y += gpio.c bootblock-y += pinmux.c +bootblock-y += raminit.c bootblock-y += timer.c -bootblock-y += bootblock_media.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart_console.c +romstage-y += clock.c +romstage-y += bootblock_media.c +romstage-y += pinmux.c +romstage-y += timer.c +romstage-y += twi.c romstage-y += uart.c romstage-y += uart_console.c -romstage-y += bootblock_media.c -ramstage-y += uart.c -ramstage-y += uart_console.c +ramstage-y += bootblock_media.c +ramstage-y += clock.c +ramstage-y += monotonic_timer.c ramstage-y += timer.c ramstage-y += twi.c -ramstage-y += monotonic_timer.c -ramstage-y += bootblock_media.c - +ramstage-y += uart.c +ramstage-y += uart_console.c real-target: $(obj)/BOOT0

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New patch to review for coreboot: d900b32 xpowers/axp209: Add helper to set voltages from devicetree config
by Alexandru Gagniuc 10 Jan '14

10 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4638 -gerrit commit d900b32fc3c3d4e9ff99b095634be1cab5a8ef9e Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 9 20:17:18 2014 -0600 xpowers/axp209: Add helper to set voltages from devicetree config Change-Id: I3ffe225b78f88c3c2d3a15292c43009e69413afb Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/xpowers/axp209/axp209.c | 77 ++++++++++++++++++++++++++++++++++++- src/drivers/xpowers/axp209/axp209.h | 3 ++ 2 files changed, 78 insertions(+), 2 deletions(-) diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c index 647f10e..cde4546 100644 --- a/src/drivers/xpowers/axp209/axp209.c +++ b/src/drivers/xpowers/axp209/axp209.c @@ -11,9 +11,13 @@ #include "axp209.h" #include "chip.h" +#include <console/console.h> #include <device/device.h> #include <device/i2c.h> +#define ERROR(x...) printk(BIOS_ERR, "[axp209] " x) +#define DEBUG(x...) printk(BIOS_DEBUG, "[axp209] " x) + /* Hide these definitions from the rest of the source, so keep them here */ enum registers { REG_POWER_STATUS = 0x00, @@ -226,11 +230,80 @@ enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts) reg8 |= REG_LDO24_VOLTAGE_LDO4_VAL(val); if (axp209_write(bus, REG_LDO24_VOLTAGE, reg8) != 1) - return CB_ERR; + return CB_ERR; return CB_SUCCESS; } - + +static const struct { + enum cb_err (*set_voltage) (u8 bus, u16 mv); + const char *name; +} vtable[] = { { + .set_voltage = axp209_set_dcdc2_voltage, + .name = "DCDC2", + }, { + .set_voltage = axp209_set_dcdc3_voltage, + .name = "DCDC3", + }, { + .set_voltage = axp209_set_ldo2_voltage, + .name = "LDO2", + }, { + .set_voltage = axp209_set_ldo3_voltage, + .name = "LDO3", + }, { + .set_voltage = axp209_set_ldo4_voltage, + .name = "LDO4", + } +}; + +static enum cb_err set_rail(u8 bus, int idx, u16 mv) +{ + enum cb_err err; + const char *name = vtable[idx].name; + + /* If voltage isn't specified, don't touch the rail */ + if (mv == 0) { + DEBUG("Skipping %s configuration\n", name); + return CB_SUCCESS; + } + + if ((err = vtable[idx].set_voltage(bus, mv) != CB_SUCCESS)) { + ERROR("Failed to set %s to %u mv\n", name, mv); + return err; + } + + return CB_SUCCESS; +} + +/** + * \brief Configure all voltage rails + * + * Configure all converters and regulators from devicetree config. If any of the + * voltages are not declared (i.e. are zero), the respective rail will not be + * reconfigured, and retain its powerup voltage. + * + * @param[in] cfg pointer to @ref drivers_xpowers_axp209_config structure + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, or an error code otherwise. + */ +enum cb_err axp209_set_voltages(u8 bus, const struct + drivers_xpowers_axp209_config *cfg) +{ + enum cb_err err; + + /* Don't worry about what the error is. Console prints that */ + err = set_rail(bus, 0, cfg->dcdc2_voltage_mv); + err |= set_rail(bus, 1, cfg->dcdc3_voltage_mv); + err |= set_rail(bus, 2, cfg->ldo2_voltage_mv); + err |= set_rail(bus, 3, cfg->ldo3_voltage_mv); + err |= set_rail(bus, 4, cfg->ldo4_voltage_mv); + + if (err != CB_SUCCESS) + return CB_ERR; + + return CB_SUCCESS; +} + /* * Usually, the AXP209 is enabled and configured in romstage, so there is no * need for a full ramstage driver. Hence .enable_dev is NULL. diff --git a/src/drivers/xpowers/axp209/axp209.h b/src/drivers/xpowers/axp209/axp209.h index 1d369f5..c9cdd7e 100644 --- a/src/drivers/xpowers/axp209/axp209.h +++ b/src/drivers/xpowers/axp209/axp209.h @@ -6,6 +6,7 @@ */ #include <types.h> +#include "chip.h" #define AXP209_I2C_ADDR (0x68 >> 1) @@ -15,3 +16,5 @@ enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts); enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts); enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts); enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_voltages(u8 bus, const struct + drivers_xpowers_axp209_config *cfg);

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New patch to review for coreboot: 7a61556 xpowers/axp209: Allow voltages to be sepecified in devicetree.cb
by Alexandru Gagniuc 10 Jan '14

10 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4637 -gerrit commit 7a61556729ad014554e45fcc5fe7adf855225ebc Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Thu Jan 9 20:07:10 2014 -0600 xpowers/axp209: Allow voltages to be sepecified in devicetree.cb This allows system voltages to be specified uniformly, rather than hardcoding them for each board. This will be used by cubieboard in an upcoming patch. Change-Id: I9dc2d3281d076c359c3fad13688649f7d36c0001 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/xpowers/axp209/axp209.c | 13 +++++++++++++ src/drivers/xpowers/axp209/chip.h | 21 +++++++++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c index 68ab8a5..647f10e 100644 --- a/src/drivers/xpowers/axp209/axp209.c +++ b/src/drivers/xpowers/axp209/axp209.c @@ -9,7 +9,9 @@ */ #include "axp209.h" +#include "chip.h" +#include <device/device.h> #include <device/i2c.h> /* Hide these definitions from the rest of the source, so keep them here */ @@ -228,3 +230,14 @@ enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts) return CB_SUCCESS; } + +/* + * Usually, the AXP209 is enabled and configured in romstage, so there is no + * need for a full ramstage driver. Hence .enable_dev is NULL. + */ +#ifndef __PRE_RAM__ +struct chip_operations drivers_xpowers_axp209_config = { + CHIP_NAME("X-Powers AXP 209 Power Management Unit") + .enable_dev = NULL, +}; +#endif /* __PRE_RAM__ */ diff --git a/src/drivers/xpowers/axp209/chip.h b/src/drivers/xpowers/axp209/chip.h new file mode 100644 index 0000000..a9023d8 --- /dev/null +++ b/src/drivers/xpowers/axp209/chip.h @@ -0,0 +1,21 @@ +/* + * Definitions for X-Powers AXP 209 Power Management Unit + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef AXP209_CHIP_H +#define AXP209_CHIP_H + +#include <types.h> + +struct drivers_xpowers_axp209_config { + u16 dcdc2_voltage_mv; /**< DCDC2 converter voltage output */ + u16 dcdc3_voltage_mv; /**< DCDC3 converter voltage output */ + u16 ldo2_voltage_mv; /**< LDO2 regulator voltage output */ + u16 ldo3_voltage_mv; /**< LDO3 regulator voltage output */ + u16 ldo4_voltage_mv; /**< LDO4 regulator voltage output */ +}; + +#endif /* AXP209_CHIP_H */

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Patch set updated for coreboot: 4297b82 drivers: Add support for X-Powers AXP209 PMU
by Alexandru Gagniuc 10 Jan '14

10 Jan '14

Alexandru Gagniuc (mr.nuke.me(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4591 -gerrit commit 4297b8239f46b3654b7a9f3cba28e1b778f025b4 Author: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> Date: Mon Dec 30 01:21:55 2013 -0500 drivers: Add support for X-Powers AXP209 PMU Change-Id: I1de0e656a38527b172af1d0b5bcd97acbfc03bf0 Signed-off-by: Alexandru Gagniuc <mr.nuke.me(a)gmail.com> --- src/drivers/Kconfig | 1 + src/drivers/Makefile.inc | 1 + src/drivers/xpowers/Kconfig | 1 + src/drivers/xpowers/Makefile.inc | 1 + src/drivers/xpowers/axp209/Kconfig | 15 +++ src/drivers/xpowers/axp209/Makefile.inc | 3 + src/drivers/xpowers/axp209/axp209.c | 230 ++++++++++++++++++++++++++++++++ src/drivers/xpowers/axp209/axp209.h | 17 +++ 8 files changed, 269 insertions(+) diff --git a/src/drivers/Kconfig b/src/drivers/Kconfig index b187419..8da7b05 100644 --- a/src/drivers/Kconfig +++ b/src/drivers/Kconfig @@ -37,3 +37,4 @@ source src/drivers/sil/Kconfig source src/drivers/spi/Kconfig source src/drivers/ti/Kconfig source src/drivers/trident/Kconfig +source src/drivers/xpowers/Kconfig diff --git a/src/drivers/Makefile.inc b/src/drivers/Makefile.inc index 7b1e4ca..34ae62e 100644 --- a/src/drivers/Makefile.inc +++ b/src/drivers/Makefile.inc @@ -34,4 +34,5 @@ subdirs-y += spi subdirs-y += ti subdirs-y += ipmi subdirs-y += elog +subdirs-y += xpowers subdirs-$(CONFIG_ARCH_X86) += pc80 diff --git a/src/drivers/xpowers/Kconfig b/src/drivers/xpowers/Kconfig new file mode 100644 index 0000000..3ac2748 --- /dev/null +++ b/src/drivers/xpowers/Kconfig @@ -0,0 +1 @@ +source src/drivers/xpowers/axp209/Kconfig diff --git a/src/drivers/xpowers/Makefile.inc b/src/drivers/xpowers/Makefile.inc new file mode 100644 index 0000000..ef6dffc --- /dev/null +++ b/src/drivers/xpowers/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209 diff --git a/src/drivers/xpowers/axp209/Kconfig b/src/drivers/xpowers/axp209/Kconfig new file mode 100644 index 0000000..684873c --- /dev/null +++ b/src/drivers/xpowers/axp209/Kconfig @@ -0,0 +1,15 @@ +config DRIVER_XPOWERS_AXP209 + bool + default n + help + X-Powers AXP902 Power Management Unit + +if DRIVER_XPOWERS_AXP209 + +config DRIVER_XPOWERS_AXP209_BOOTBLOCK + bool + default n + help + Make AXP209 functionality available in he bootblock. + +endif # DRIVER_XPOWERS_AXP209 diff --git a/src/drivers/xpowers/axp209/Makefile.inc b/src/drivers/xpowers/axp209/Makefile.inc new file mode 100644 index 0000000..5ac691e --- /dev/null +++ b/src/drivers/xpowers/axp209/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-$(CONFIG_DRIVER_XPOWERS_AXP209_BOOTBLOCK) += axp209.c +romstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c +ramstage-$(CONFIG_DRIVER_XPOWERS_AXP209) += axp209.c diff --git a/src/drivers/xpowers/axp209/axp209.c b/src/drivers/xpowers/axp209/axp209.c new file mode 100644 index 0000000..68ab8a5 --- /dev/null +++ b/src/drivers/xpowers/axp209/axp209.c @@ -0,0 +1,230 @@ +/* + * Driver for X-Powers AXP 209 Power Management Unit + * + * Despite axp209_read/write only working on a byte at a time, there is no such + * limitation in the AXP209. + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "axp209.h" + +#include <device/i2c.h> + +/* Hide these definitions from the rest of the source, so keep them here */ +enum registers { + REG_POWER_STATUS = 0x00, + REG_POWER_MODE = 0x01, + REG_OTG_VBUS = 0x02, + REG_CHIP_ID = 0x03, + REG_CHIP_PWROUT_CTL = 0x12, + REG_DCDC2_VOLTAGE = 0x23, + REG_DCDC2_LDO3_CTL = 0x25, + REG_DCDC3_VOLTAGE = 0x27, + REG_LDO24_VOLTAGE = 0x28, + REG_LDO3_VOLTAGE = 0x29, + REG_VBUS_IPSOUT = 0x30, + REG_PWROFF_VOLTAGE = 0x31, + REG_SHTDWN_SETTING = 0x32, +}; + +/* REG_LDO24_VOLTAGE definitions */ +#define REG_LDO24_VOLTAGE_LDO2_MASK (0xf << 4) +#define REG_LDO24_VOLTAGE_LDO2_VAL(x) ((x << 4) & REG_LDO24_VOLTAGE_LDO2_MASK) +#define REG_LDO24_VOLTAGE_LDO4_MASK (0xf << 0) +#define REG_LDO24_VOLTAGE_LDO4_VAL(x) ((x << 0) & REG_LDO24_VOLTAGE_LDO4_MASK) + +/* + * Read and write accessors. We only work on one register at a time, but there + * is no limitation on the AXP209 as to how many registers we may read or write + * in one transaction. + * These return the number of bytes read/written, or an error code. In this + * case, they return 1 on success, or an error code otherwise. + */ +static int axp209_read(u8 bus, u8 reg, u8 *val) +{ + return i2c_read(bus, AXP209_I2C_ADDR, reg, 1, val, 1); +} + +static int axp209_write(u8 bus, u8 reg, u8 val) +{ + return i2c_write(bus, AXP209_I2C_ADDR, reg, 1, &val, 1); +} + +/** + * \brief Identify and initialize an AXP209 on the I²C bus + * + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on if an AXP209 is found, or an error code otherwise. + */ +enum cb_err axp209_init(u8 bus) +{ + u8 id; + + if (axp209_read(bus, REG_CHIP_ID, &id) != 1) + return CB_ERR; + + /* From U-Boot code : Low 4 bits is chip version */ + if ((id & 0x0f) != 0x1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of DC-DC2 converter + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 2275mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts) +{ + u8 val; + + if (millivolts < 700 || millivolts > 2275) + return CB_ERR_ARG; + + val = (millivolts - 700) / 25; + + if (axp209_write(bus, REG_DCDC2_VOLTAGE, val) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of DC-DC3 converter + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 3500mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts) +{ + u8 val; + + if (millivolts < 700 || millivolts > 3500) + return CB_ERR_ARG; + + val = (millivolts - 700) / 25; + + if (axp209_write(bus, REG_DCDC3_VOLTAGE, val) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of LDO2 regulator + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 3300mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts) +{ + u8 reg8, val; + + if (millivolts < 1800 || millivolts > 3300) + return CB_ERR_ARG; + + /* Try to read the register first, and stop here on error */ + if (axp209_read(bus, REG_LDO24_VOLTAGE, &reg8) != 1) + return CB_ERR; + + val = (millivolts - 1800) / 100; + reg8 &= ~REG_LDO24_VOLTAGE_LDO2_MASK; + reg8 |= REG_LDO24_VOLTAGE_LDO2_VAL(val); + + if (axp209_write(bus, REG_LDO24_VOLTAGE, reg8) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of LDO4 regulator + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 700mV and 3500mV. Datasheet lists maximum voltage at + * 2250mV, but hardware samples go as high as 3500mV. + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts) +{ + u8 val; + + /* Datasheet lists 2250 max, but PMU will output up to 3500mV */ + if (millivolts < 700 || millivolts > 3500) + return CB_ERR_ARG; + + val = (millivolts - 700) / 25; + + if (axp209_write(bus, REG_LDO3_VOLTAGE, val) != 1) + return CB_ERR; + + return CB_SUCCESS; +} + +/** + * \brief Configure the output voltage of DC-DC2 converter + * + * If the requested voltage is not available, the next lowest voltage will + * be applied. + * Valid values are between 1250V and 3300mV + * + * @param[in] millivolts voltage in mV units. + * @param[in] bus I²C bus to which the AXP209 is connected + * @return CB_SUCCES on success, + * CB_ERR_ARG if voltage is out of range, or an error code otherwise. + */ +enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts) +{ + u8 reg8, val; + + if (millivolts < 1250 || millivolts > 3300) + return CB_ERR_ARG; + + /* Try to read the register first, and stop here on error */ + if (axp209_read(bus, REG_LDO24_VOLTAGE, &reg8) != 1) + return CB_ERR; + + if (millivolts <= 2000) + val = (millivolts - 1200) / 100; + else if (millivolts <= 2700) + val = 9 + (millivolts - 2500) / 100; + else if (millivolts <= 2800) + val = 11; + else + val = 12 + (millivolts - 3000) / 100; + + reg8 &= ~REG_LDO24_VOLTAGE_LDO4_MASK; + reg8 |= REG_LDO24_VOLTAGE_LDO4_VAL(val); + + if (axp209_write(bus, REG_LDO24_VOLTAGE, reg8) != 1) + return CB_ERR; + + return CB_SUCCESS; +} diff --git a/src/drivers/xpowers/axp209/axp209.h b/src/drivers/xpowers/axp209/axp209.h new file mode 100644 index 0000000..1d369f5 --- /dev/null +++ b/src/drivers/xpowers/axp209/axp209.h @@ -0,0 +1,17 @@ +/* + * Definitions for X-Powers AXP 209 Power Management Unit + * + * Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include <types.h> + +#define AXP209_I2C_ADDR (0x68 >> 1) + +enum cb_err axp209_init(u8 bus); +enum cb_err axp209_set_dcdc2_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_dcdc3_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_ldo2_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_ldo3_voltage(u8 bus, u16 millivolts); +enum cb_err axp209_set_ldo4_voltage(u8 bus, u16 millivolts);

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Patch set updated for coreboot: 9e8b491 nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__
by Vladimir Serbinenko 10 Jan '14

10 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4603 -gerrit commit 9e8b491ce30235ba53217930bd901afa59ec9555 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 2 10:10:14 2014 +0100 nehalem: Simplify acpi.c by using __SIMPLE_DEVICE__ Change-Id: I93351a2716cd58c2006400cecca1390b1704e94b Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/acpi.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/nehalem/acpi.c b/src/northbridge/intel/nehalem/acpi.c index df6cc1a..d7295e6 100644 --- a/src/northbridge/intel/nehalem/acpi.c +++ b/src/northbridge/intel/nehalem/acpi.c @@ -21,6 +21,8 @@ * MA 02110-1301 USA */ +#define __SIMPLE_DEVICE__ + #include <types.h> #include <string.h> #include <console/console.h> @@ -38,10 +40,7 @@ unsigned long acpi_fill_mcfg(unsigned long current) u32 pciexbar_reg; int max_buses; - /* Quickpath bus is not in standard coreboot device tree, - so read register directly. */ - pciexbar_reg = read32(DEFAULT_PCIEXBAR - | (QUICKPATH_BUS << 20) | 0x1050); + pciexbar_reg = pci_read_config32 (PCI_DEV (QUICKPATH_BUS, 0, 1), 0x50); // MMCFG not supported or not enabled. if (!(pciexbar_reg & (1 << 0))) @@ -173,7 +172,7 @@ int init_igd_opregion(igd_opregion_t * opregion) /* TODO This needs to happen in S3 resume, too. * Maybe it should move to the finalize handler */ - igd = dev_find_slot(0, PCI_DEVFN(0x2, 0)); + igd = PCI_DEV (0, 0x2, 0); pci_write_config32(igd, ASLS, (u32) opregion); reg16 = pci_read_config16(igd, SWSCI);

1 0

Patch set updated for coreboot: 226af99 X201: Add missing CPU counter.
by Vladimir Serbinenko 10 Jan '14

10 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4624 -gerrit commit 226af997e1c2389ed5a4b3a54d6b62b63cf566d4 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 2 11:08:29 2014 +0100 X201: Add missing CPU counter. Change-Id: If9f10ef40193fc84ab1849429b5af678ffe831b2 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/acpi_tables.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/x201/acpi_tables.c b/src/mainboard/lenovo/x201/acpi_tables.c index 36939d7..165de0d 100644 --- a/src/mainboard/lenovo/x201/acpi_tables.c +++ b/src/mainboard/lenovo/x201/acpi_tables.c @@ -42,6 +42,7 @@ static void acpi_create_gnvs(global_nvs_t * gnvs) memset((void *)gnvs, 0, sizeof(*gnvs)); gnvs->apic = 1; gnvs->mpen = 1; /* Enable Multi Processing */ + gnvs->pcnt = dev_count_cpu(); /* IGD Displays */ gnvs->ndid = 3;

1 0

Patch set updated for coreboot: 5ca2f70 nehalem: Restore frequency ratio registers on S3 resume
by Vladimir Serbinenko 10 Jan '14

10 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4634 -gerrit commit 5ca2f70577733666e5625c6aaf0d4535aae05975 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:10:04 2014 +0100 nehalem: Restore frequency ratio registers on S3 resume Previously registers 274/265 and 6dc/6e8 were recomputed which lead to a slightly different values. On S3 resume it needs to be perfect match. Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/raminit.c | 142 +++++++++++++++++--------------- 1 file changed, 77 insertions(+), 65 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 9730604..b5dcbac 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -102,6 +102,10 @@ struct ram_training { u16 timing_offset[2][2][2][9]; u16 timing2_offset[2][2][2][9]; u16 timing2_bounds[2][2][2][9][2]; + u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ + u8 reg2ca9_bit0; + u32 reg_6dc; + u32 reg_6e8; }; #if !REAL @@ -259,8 +263,6 @@ struct raminfo { struct ram_training training; u32 last_500_command[2]; - u8 reg2ca9_bit0; - u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ u32 delay46_ps[2]; u32 delay54_ps[2]; u8 revision_flag_1; @@ -1680,6 +1682,9 @@ static void dump_timings(struct raminfo *info) #endif } +/* Read timings and other registers that need to be restored verbatim and + put them to CBMEM. + */ static void save_timings(struct raminfo *info) { #if CONFIG_EARLY_CBMEM_INIT @@ -1698,6 +1703,20 @@ static void save_timings(struct raminfo *info) train.reg_178 = read_1d0(0x178, 7); train.reg_10b = read_1d0(0x10b, 6); + for (channel = 0; channel < NUM_CHANNELS; channel++) { + u32 reg32; + reg32 = read_mchbar32 ((channel << 10) + 0x274); + train.reg274265[channel][0] = reg32 >> 16; + train.reg274265[channel][1] = reg32 & 0xffff; + train.reg274265[channel][2] = read_mchbar16 ((channel << 10) + 0x265) >> 8; + } + train.reg2ca9_bit0 = read_mchbar8(0x2ca9) & 1; + train.reg_6dc = read_mchbar32 (0x6dc); + train.reg_6e8 = read_mchbar32 (0x6e8); + + printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + /* Save the MRC S3 restore data to cbmem */ cbmem_initialize(); mrcdata = cbmem_add @@ -3491,6 +3510,13 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); + printk (BIOS_SPEW, "[%x] <= %x\n", reg, + ratios1.freq4_to_max_remainder | (ratios2. + freq4_to_max_remainder + << 8) + | (ratios1.divisor_f4_to_fmax << 16) | (ratios2. + divisor_f4_to_fmax + << 20)); write_mchbar32(reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder @@ -3553,7 +3579,7 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2, } } -static void set_2dxx_series(struct raminfo *info) +static void set_2dxx_series(struct raminfo *info, int s3resume) { set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005, 0, 1); @@ -3581,14 +3607,24 @@ static void set_2dxx_series(struct raminfo *info) set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency, frequency_11(info) / 2, 4000, 4000, 0, 0); - set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[0], 0, info->delay54_ps[0]); + if (s3resume) { + printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + write_mchbar32(0x6dc, info->cached_training->reg_6dc); + } else + set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[0], 0, + info->delay54_ps[0]); set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency, frequency_11(info), 2500, 0, 0, 0); set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); - set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[1], 0, info->delay54_ps[1]); + if (s3resume) { + printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + write_mchbar32(0x6e8, info->cached_training->reg_6e8); + } else + set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[1], 0, + info->delay54_ps[1]); set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0); set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455, 470, 0); @@ -3639,7 +3675,7 @@ static void set_274265(struct raminfo *info) int channel; delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info); - info->reg2ca9_bit0 = 0; + info->training.reg2ca9_bit0 = 0; for (channel = 0; channel < NUM_CHANNELS; channel++) { cycletime_ps = 900000 / lcm(2 * info->fsb_frequency, frequency_11(info)); @@ -3690,7 +3726,7 @@ static void set_274265(struct raminfo *info) if (info->delay46_ps[channel] < 2500) { info->delay46_ps[channel] = 2500; - info->reg2ca9_bit0 = 1; + info->training.reg2ca9_bit0 = 1; } delay_b_ps = halfcycle_ps(info) + delay_c_ps; if (delay_b_ps <= delay_a_ps) @@ -3703,25 +3739,24 @@ static void set_274265(struct raminfo *info) 2 * halfcycle_ps(info) * delay_e_cycles; if (info->delay54_ps[channel] < 2500) info->delay54_ps[channel] = 2500; - info->reg274265[channel][0] = delay_e_cycles; + info->training.reg274265[channel][0] = delay_e_cycles; if (delay_d_ps + 7 * halfcycle_ps(info) <= 24 * halfcycle_ps(info)) - info->reg274265[channel][1] = 0; + info->training.reg274265[channel][1] = 0; else - info->reg274265[channel][1] = + info->training.reg274265[channel][1] = div_roundup(delay_d_ps + 7 * halfcycle_ps(info), 4 * halfcycle_ps(info)) - 6; write_mchbar32((channel << 10) + 0x274, - info->reg274265[channel][1] | (info-> - reg274265[channel] - [0] << 16)); - info->reg274265[channel][2] = + info->training.reg274265[channel][1] + | (info->training.reg274265[channel][0] << 16)); + info->training.reg274265[channel][2] = div_roundup(delay_c_ps + 3 * fsbcycle_ps(info), 4 * halfcycle_ps(info)) + 1; write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->training.reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->training.reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -3733,12 +3768,12 @@ static void restore_274265(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32((channel << 10) + 0x274, - (info->reg274265[channel][0] << 16) | info-> - reg274265[channel][1]); + (info->cached_training->reg274265[channel][0] << 16) + | info->cached_training->reg274265[channel][1]); write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->cached_training->reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->cached_training->reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -4145,50 +4180,29 @@ void raminit(const int s3resume) udelay(1000); + info.cached_training = get_cached_training(); + if (x2ca8 == 0) { - if (s3resume) { -#if REAL && 0 - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 5; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xe; - info.reg274265[1][0] = 5; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xe; - info.delay46_ps[0] = 0xa86; - info.delay46_ps[1] = 0xa86; - info.delay54_ps[0] = 0xdc6; - info.delay54_ps[1] = 0xdc6; -#else - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 3; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xd; - info.reg274265[1][0] = 4; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xd; - info.delay46_ps[0] = 0x110a; - info.delay46_ps[1] = 0xb58; - info.delay54_ps[0] = 0x144a; - info.delay54_ps[1] = 0xe98; -#endif + int j; + if (s3resume && info.cached_training) { restore_274265(&info); - } else + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.cached_training->reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.cached_training->reg274265[i][j]); + } else { set_274265(&info); - int j; - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0); - for (i = 0; i < 2; i++) - for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", - i, j, info.reg274265[i][j]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i, - info.delay46_ps[i]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i, - info.delay54_ps[i]); - - set_2dxx_series(&info); + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.training.reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.training.reg274265[i][j]); + } + + set_2dxx_series(&info, s3resume); if (!(deven & 8)) { read_mchbar32(0x2cb0); @@ -4504,8 +4518,6 @@ void raminit(const int s3resume) udelay(1000); - info.cached_training = get_cached_training(); - if (s3resume) { if (info.cached_training == NULL) { u32 reg32;

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coreboot-gerrit January 2014