coreboot-gerrit January 2014

coreboot-gerrit@coreboot.org

1 participants
1801 discussions

Patch set updated for coreboot: 08b1404 nehalem: restore frequency ratio ragisters on S3 resume
by Vladimir Serbinenko 10 Jan '14

10 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4634 -gerrit commit 08b140497c5a75bd013555981ada865e2831d158 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:10:04 2014 +0100 nehalem: restore frequency ratio ragisters on S3 resume Previously registers 274/265 and 6dc/6e8 were recomputed which lead to a slightly different values. On S3 resume it needs to be perfect match. Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/raminit.c | 142 +++++++++++++++++--------------- 1 file changed, 77 insertions(+), 65 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 9730604..b5dcbac 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -102,6 +102,10 @@ struct ram_training { u16 timing_offset[2][2][2][9]; u16 timing2_offset[2][2][2][9]; u16 timing2_bounds[2][2][2][9][2]; + u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ + u8 reg2ca9_bit0; + u32 reg_6dc; + u32 reg_6e8; }; #if !REAL @@ -259,8 +263,6 @@ struct raminfo { struct ram_training training; u32 last_500_command[2]; - u8 reg2ca9_bit0; - u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ u32 delay46_ps[2]; u32 delay54_ps[2]; u8 revision_flag_1; @@ -1680,6 +1682,9 @@ static void dump_timings(struct raminfo *info) #endif } +/* Read timings and other registers that need to be restored verbatim and + put them to CBMEM. + */ static void save_timings(struct raminfo *info) { #if CONFIG_EARLY_CBMEM_INIT @@ -1698,6 +1703,20 @@ static void save_timings(struct raminfo *info) train.reg_178 = read_1d0(0x178, 7); train.reg_10b = read_1d0(0x10b, 6); + for (channel = 0; channel < NUM_CHANNELS; channel++) { + u32 reg32; + reg32 = read_mchbar32 ((channel << 10) + 0x274); + train.reg274265[channel][0] = reg32 >> 16; + train.reg274265[channel][1] = reg32 & 0xffff; + train.reg274265[channel][2] = read_mchbar16 ((channel << 10) + 0x265) >> 8; + } + train.reg2ca9_bit0 = read_mchbar8(0x2ca9) & 1; + train.reg_6dc = read_mchbar32 (0x6dc); + train.reg_6e8 = read_mchbar32 (0x6e8); + + printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + /* Save the MRC S3 restore data to cbmem */ cbmem_initialize(); mrcdata = cbmem_add @@ -3491,6 +3510,13 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); + printk (BIOS_SPEW, "[%x] <= %x\n", reg, + ratios1.freq4_to_max_remainder | (ratios2. + freq4_to_max_remainder + << 8) + | (ratios1.divisor_f4_to_fmax << 16) | (ratios2. + divisor_f4_to_fmax + << 20)); write_mchbar32(reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder @@ -3553,7 +3579,7 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2, } } -static void set_2dxx_series(struct raminfo *info) +static void set_2dxx_series(struct raminfo *info, int s3resume) { set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005, 0, 1); @@ -3581,14 +3607,24 @@ static void set_2dxx_series(struct raminfo *info) set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency, frequency_11(info) / 2, 4000, 4000, 0, 0); - set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[0], 0, info->delay54_ps[0]); + if (s3resume) { + printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + write_mchbar32(0x6dc, info->cached_training->reg_6dc); + } else + set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[0], 0, + info->delay54_ps[0]); set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency, frequency_11(info), 2500, 0, 0, 0); set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); - set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[1], 0, info->delay54_ps[1]); + if (s3resume) { + printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + write_mchbar32(0x6e8, info->cached_training->reg_6e8); + } else + set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[1], 0, + info->delay54_ps[1]); set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0); set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455, 470, 0); @@ -3639,7 +3675,7 @@ static void set_274265(struct raminfo *info) int channel; delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info); - info->reg2ca9_bit0 = 0; + info->training.reg2ca9_bit0 = 0; for (channel = 0; channel < NUM_CHANNELS; channel++) { cycletime_ps = 900000 / lcm(2 * info->fsb_frequency, frequency_11(info)); @@ -3690,7 +3726,7 @@ static void set_274265(struct raminfo *info) if (info->delay46_ps[channel] < 2500) { info->delay46_ps[channel] = 2500; - info->reg2ca9_bit0 = 1; + info->training.reg2ca9_bit0 = 1; } delay_b_ps = halfcycle_ps(info) + delay_c_ps; if (delay_b_ps <= delay_a_ps) @@ -3703,25 +3739,24 @@ static void set_274265(struct raminfo *info) 2 * halfcycle_ps(info) * delay_e_cycles; if (info->delay54_ps[channel] < 2500) info->delay54_ps[channel] = 2500; - info->reg274265[channel][0] = delay_e_cycles; + info->training.reg274265[channel][0] = delay_e_cycles; if (delay_d_ps + 7 * halfcycle_ps(info) <= 24 * halfcycle_ps(info)) - info->reg274265[channel][1] = 0; + info->training.reg274265[channel][1] = 0; else - info->reg274265[channel][1] = + info->training.reg274265[channel][1] = div_roundup(delay_d_ps + 7 * halfcycle_ps(info), 4 * halfcycle_ps(info)) - 6; write_mchbar32((channel << 10) + 0x274, - info->reg274265[channel][1] | (info-> - reg274265[channel] - [0] << 16)); - info->reg274265[channel][2] = + info->training.reg274265[channel][1] + | (info->training.reg274265[channel][0] << 16)); + info->training.reg274265[channel][2] = div_roundup(delay_c_ps + 3 * fsbcycle_ps(info), 4 * halfcycle_ps(info)) + 1; write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->training.reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->training.reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -3733,12 +3768,12 @@ static void restore_274265(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32((channel << 10) + 0x274, - (info->reg274265[channel][0] << 16) | info-> - reg274265[channel][1]); + (info->cached_training->reg274265[channel][0] << 16) + | info->cached_training->reg274265[channel][1]); write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->cached_training->reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->cached_training->reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -4145,50 +4180,29 @@ void raminit(const int s3resume) udelay(1000); + info.cached_training = get_cached_training(); + if (x2ca8 == 0) { - if (s3resume) { -#if REAL && 0 - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 5; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xe; - info.reg274265[1][0] = 5; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xe; - info.delay46_ps[0] = 0xa86; - info.delay46_ps[1] = 0xa86; - info.delay54_ps[0] = 0xdc6; - info.delay54_ps[1] = 0xdc6; -#else - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 3; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xd; - info.reg274265[1][0] = 4; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xd; - info.delay46_ps[0] = 0x110a; - info.delay46_ps[1] = 0xb58; - info.delay54_ps[0] = 0x144a; - info.delay54_ps[1] = 0xe98; -#endif + int j; + if (s3resume && info.cached_training) { restore_274265(&info); - } else + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.cached_training->reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.cached_training->reg274265[i][j]); + } else { set_274265(&info); - int j; - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0); - for (i = 0; i < 2; i++) - for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", - i, j, info.reg274265[i][j]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i, - info.delay46_ps[i]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i, - info.delay54_ps[i]); - - set_2dxx_series(&info); + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.training.reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.training.reg274265[i][j]); + } + + set_2dxx_series(&info, s3resume); if (!(deven & 8)) { read_mchbar32(0x2cb0); @@ -4504,8 +4518,6 @@ void raminit(const int s3resume) udelay(1000); - info.cached_training = get_cached_training(); - if (s3resume) { if (info.cached_training == NULL) { u32 reg32;

1 0

New patch to review for coreboot: 01d2dac Ibexpeak: add missing thermal init.
by Vladimir Serbinenko 09 Jan '14

09 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4636 -gerrit commit 01d2dac97bec0e8d44ce3c2c69aa36a65908be8f Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 23:41:48 2014 +0100 Ibexpeak: add missing thermal init. Without it ME doesn't always start correctly and no temperature is reported, no fan management and so on. Change-Id: Iff71f3afbc35a1453a20d182890ae2d196c556bd Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 2 ++ src/southbridge/intel/ibexpeak/Makefile.inc | 2 +- src/southbridge/intel/ibexpeak/early_thermal.c | 47 ++++++++++++++++++++++++++ src/southbridge/intel/ibexpeak/pch.h | 1 + 4 files changed, 51 insertions(+), 1 deletion(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8022d7b..5bcaccb 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -314,6 +314,8 @@ void main(unsigned long bist) pci_read_config8(PCH_LPC_DEV, GEN_PMCON_3) | 2); } + early_thermal_init(); + timestamp_add_now(TS_BEFORE_INITRAM); raminit(s3resume); diff --git a/src/southbridge/intel/ibexpeak/Makefile.inc b/src/southbridge/intel/ibexpeak/Makefile.inc index a29129d..e7f7d99 100644 --- a/src/southbridge/intel/ibexpeak/Makefile.inc +++ b/src/southbridge/intel/ibexpeak/Makefile.inc @@ -45,7 +45,7 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c ../bd82x6x/me_8.x.c ../bd82x6x/finalize.c ../bd82x6x/pch.c -romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c +romstage-y += ../bd82x6x/early_usb.c early_smbus.c ../bd82x6x/early_me.c ../bd82x6x/me_status.c ../bd82x6x/gpio.c early_thermal.c romstage-y += ../bd82x6x/reset.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) += ../bd82x6x/early_spi.c romstage-$(CONFIG_SOUTHBRIDGE_INTEL_C216) += ../bd82x6x/early_spi.c diff --git a/src/southbridge/intel/ibexpeak/early_thermal.c b/src/southbridge/intel/ibexpeak/early_thermal.c new file mode 100644 index 0000000..4c2383c --- /dev/null +++ b/src/southbridge/intel/ibexpeak/early_thermal.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Vladimir Serbinenko + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include "pch.h" + +/* Early thermal init, must be done prior to giving ME its memory + which is done at the end of raminit. */ +void early_thermal_init(void) +{ + device_t dev; + + dev = PCI_DEV(0x0, 0x1f, 0x6); + + /* Program address for temporary BAR. */ + pci_write_config32(dev, 0x40, 0x40000000); + pci_write_config32(dev, 0x44, 0x0); + + /* Activate temporary BAR. */ + pci_write_config32(dev, 0x40, + pci_read_config32(dev, 0x40) | 5); + + /* Perform init. */ + write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0); + + /* Disable temporary BAR. */ + pci_write_config32(dev, 0x40, + pci_read_config32(dev, 0x40) & ~1); + pci_write_config32(dev, 0x40, 0); +} diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 356dd8a..df125f0 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -78,6 +78,7 @@ int smbus_write_byte(unsigned device, unsigned address, u8 data); int smbus_block_read(unsigned device, unsigned cmd, u8 bytes, u8 *buf); int smbus_block_write(unsigned device, unsigned cmd, u8 bytes, const u8 *buf); int early_spi_read(u32 offset, u32 size, u8 *buffer); +void early_thermal_init(void); #endif #endif

1 0

Patch merged into coreboot/master: 3bb57e6 X201: set default USB debug controller to 2.
by gerrit＠coreboot.org 09 Jan '14

09 Jan '14

the following patch was just integrated into master: commit 3bb57e60082ab8087c4f212a0601964f4c880924 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:06:37 2014 +0100 X201: set default USB debug controller to 2. The other port is not easily accessible. Change-Id: I6ea31346a375debcd5fc1c27e4078e3a436715e3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4635 for details. -gerrit

1 0

Patch merged into coreboot/master: 7d0aca6 bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable
by gerrit＠coreboot.org 09 Jan '14

09 Jan '14

the following patch was just integrated into master: commit 7d0aca66a1cb22401a9023535dc62a2e80155cd5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 11:37:32 2014 +0100 bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable DRAM reset gate GPIO is different on different mobos move it to hidden config with 60 (current value) as default. Set it to 10 for Lenovo X201. Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> See http://review.coreboot.org/4622 for details. -gerrit

1 0

Patch set updated for coreboot: 3bb57e6 X201: set default USB debug controller to 2.
by Vladimir Serbinenko 09 Jan '14

09 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4635 -gerrit commit 3bb57e60082ab8087c4f212a0601964f4c880924 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:06:37 2014 +0100 X201: set default USB debug controller to 2. The other port is not easily accessible. Change-Id: I6ea31346a375debcd5fc1c27e4078e3a436715e3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 76be9db..8e7ebae 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT int default 18 +config USBDEBUG_HCD_INDEX + int + default 2 + config DRAM_RESET_GATE_GPIO int default 10

1 0

Patch set updated for coreboot: 6db5bf6 nehalem: restore 274/265 and 6dc/6e8 on S3 resume
by Vladimir Serbinenko 09 Jan '14

09 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4634 -gerrit commit 6db5bf621d909b42314b8c1dd153cab3383b6d50 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:10:04 2014 +0100 nehalem: restore 274/265 and 6dc/6e8 on S3 resume Previously they were recomputed which lead to a slightly different values. On S3 resume it needs to be perfect match. Change-Id: I14f42c7659dde5f327979831fcb1f84ea0c78dee Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/raminit.c | 142 +++++++++++++++++--------------- 1 file changed, 77 insertions(+), 65 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 9730604..b5dcbac 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -102,6 +102,10 @@ struct ram_training { u16 timing_offset[2][2][2][9]; u16 timing2_offset[2][2][2][9]; u16 timing2_bounds[2][2][2][9][2]; + u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ + u8 reg2ca9_bit0; + u32 reg_6dc; + u32 reg_6e8; }; #if !REAL @@ -259,8 +263,6 @@ struct raminfo { struct ram_training training; u32 last_500_command[2]; - u8 reg2ca9_bit0; - u8 reg274265[2][3]; /* [CHANNEL][REGISTER] */ u32 delay46_ps[2]; u32 delay54_ps[2]; u8 revision_flag_1; @@ -1680,6 +1682,9 @@ static void dump_timings(struct raminfo *info) #endif } +/* Read timings and other registers that need to be restored verbatim and + put them to CBMEM. + */ static void save_timings(struct raminfo *info) { #if CONFIG_EARLY_CBMEM_INIT @@ -1698,6 +1703,20 @@ static void save_timings(struct raminfo *info) train.reg_178 = read_1d0(0x178, 7); train.reg_10b = read_1d0(0x10b, 6); + for (channel = 0; channel < NUM_CHANNELS; channel++) { + u32 reg32; + reg32 = read_mchbar32 ((channel << 10) + 0x274); + train.reg274265[channel][0] = reg32 >> 16; + train.reg274265[channel][1] = reg32 & 0xffff; + train.reg274265[channel][2] = read_mchbar16 ((channel << 10) + 0x265) >> 8; + } + train.reg2ca9_bit0 = read_mchbar8(0x2ca9) & 1; + train.reg_6dc = read_mchbar32 (0x6dc); + train.reg_6e8 = read_mchbar32 (0x6e8); + + printk (BIOS_SPEW, "[6dc] = %x\n", train.reg_6dc); + printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); + /* Save the MRC S3 restore data to cbmem */ cbmem_initialize(); mrcdata = cbmem_add @@ -3491,6 +3510,13 @@ set_6d_reg(struct raminfo *info, u16 reg, u16 freq1, u16 freq2, 0, 1, &ratios2); compute_frequence_ratios(info, freq1, freq2, num_cycles_3, num_cycles_4, 0, 1, &ratios1); + printk (BIOS_SPEW, "[%x] <= %x\n", reg, + ratios1.freq4_to_max_remainder | (ratios2. + freq4_to_max_remainder + << 8) + | (ratios1.divisor_f4_to_fmax << 16) | (ratios2. + divisor_f4_to_fmax + << 20)); write_mchbar32(reg, ratios1.freq4_to_max_remainder | (ratios2. freq4_to_max_remainder @@ -3553,7 +3579,7 @@ set_2dx8_reg(struct raminfo *info, u16 reg, u8 mode, u16 freq1, u16 freq2, } } -static void set_2dxx_series(struct raminfo *info) +static void set_2dxx_series(struct raminfo *info, int s3resume) { set_2dx8_reg(info, 0x2d00, 0, 0x78, frequency_11(info) / 2, 1359, 1005, 0, 1); @@ -3581,14 +3607,24 @@ static void set_2dxx_series(struct raminfo *info) set_2dx8_reg(info, 0x6d8, 2, info->fsb_frequency, frequency_11(info) / 2, 4000, 4000, 0, 0); - set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[0], 0, info->delay54_ps[0]); + if (s3resume) { + printk (BIOS_SPEW, "[6dc] <= %x\n", info->cached_training->reg_6dc); + write_mchbar32(0x6dc, info->cached_training->reg_6dc); + } else + set_6d_reg(info, 0x6dc, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[0], 0, + info->delay54_ps[0]); set_2dx8_reg(info, 0x6e0, 1, 2 * info->fsb_frequency, frequency_11(info), 2500, 0, 0, 0); set_2dx8_reg(info, 0x6e4, 1, 2 * info->fsb_frequency, frequency_11(info) / 2, 3500, 0, 0, 0); - set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, - info->delay46_ps[1], 0, info->delay54_ps[1]); + if (s3resume) { + printk (BIOS_SPEW, "[6e8] <= %x\n", info->cached_training->reg_6e8); + write_mchbar32(0x6e8, info->cached_training->reg_6e8); + } else + set_6d_reg(info, 0x6e8, 2 * info->fsb_frequency, frequency_11(info), 0, + info->delay46_ps[1], 0, + info->delay54_ps[1]); set_2d5x_reg(info, 0x2d58, 0x78, 0x78, 864, 1195, 762, 786, 0); set_2d5x_reg(info, 0x2d60, 0x195, info->fsb_frequency, 1352, 725, 455, 470, 0); @@ -3639,7 +3675,7 @@ static void set_274265(struct raminfo *info) int channel; delay_a_ps = 4 * halfcycle_ps(info) + 6 * fsbcycle_ps(info); - info->reg2ca9_bit0 = 0; + info->training.reg2ca9_bit0 = 0; for (channel = 0; channel < NUM_CHANNELS; channel++) { cycletime_ps = 900000 / lcm(2 * info->fsb_frequency, frequency_11(info)); @@ -3690,7 +3726,7 @@ static void set_274265(struct raminfo *info) if (info->delay46_ps[channel] < 2500) { info->delay46_ps[channel] = 2500; - info->reg2ca9_bit0 = 1; + info->training.reg2ca9_bit0 = 1; } delay_b_ps = halfcycle_ps(info) + delay_c_ps; if (delay_b_ps <= delay_a_ps) @@ -3703,25 +3739,24 @@ static void set_274265(struct raminfo *info) 2 * halfcycle_ps(info) * delay_e_cycles; if (info->delay54_ps[channel] < 2500) info->delay54_ps[channel] = 2500; - info->reg274265[channel][0] = delay_e_cycles; + info->training.reg274265[channel][0] = delay_e_cycles; if (delay_d_ps + 7 * halfcycle_ps(info) <= 24 * halfcycle_ps(info)) - info->reg274265[channel][1] = 0; + info->training.reg274265[channel][1] = 0; else - info->reg274265[channel][1] = + info->training.reg274265[channel][1] = div_roundup(delay_d_ps + 7 * halfcycle_ps(info), 4 * halfcycle_ps(info)) - 6; write_mchbar32((channel << 10) + 0x274, - info->reg274265[channel][1] | (info-> - reg274265[channel] - [0] << 16)); - info->reg274265[channel][2] = + info->training.reg274265[channel][1] + | (info->training.reg274265[channel][0] << 16)); + info->training.reg274265[channel][2] = div_roundup(delay_c_ps + 3 * fsbcycle_ps(info), 4 * halfcycle_ps(info)) + 1; write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->training.reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->training.reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -3733,12 +3768,12 @@ static void restore_274265(struct raminfo *info) for (channel = 0; channel < NUM_CHANNELS; channel++) { write_mchbar32((channel << 10) + 0x274, - (info->reg274265[channel][0] << 16) | info-> - reg274265[channel][1]); + (info->cached_training->reg274265[channel][0] << 16) + | info->cached_training->reg274265[channel][1]); write_mchbar16((channel << 10) + 0x265, - info->reg274265[channel][2] << 8); + info->cached_training->reg274265[channel][2] << 8); } - if (info->reg2ca9_bit0) + if (info->cached_training->reg2ca9_bit0) write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) | 1); else write_mchbar8(0x2ca9, read_mchbar8(0x2ca9) & ~1); @@ -4145,50 +4180,29 @@ void raminit(const int s3resume) udelay(1000); + info.cached_training = get_cached_training(); + if (x2ca8 == 0) { - if (s3resume) { -#if REAL && 0 - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 5; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xe; - info.reg274265[1][0] = 5; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xe; - info.delay46_ps[0] = 0xa86; - info.delay46_ps[1] = 0xa86; - info.delay54_ps[0] = 0xdc6; - info.delay54_ps[1] = 0xdc6; -#else - info.reg2ca9_bit0 = 0; - info.reg274265[0][0] = 3; - info.reg274265[0][1] = 5; - info.reg274265[0][2] = 0xd; - info.reg274265[1][0] = 4; - info.reg274265[1][1] = 5; - info.reg274265[1][2] = 0xd; - info.delay46_ps[0] = 0x110a; - info.delay46_ps[1] = 0xb58; - info.delay54_ps[0] = 0x144a; - info.delay54_ps[1] = 0xe98; -#endif + int j; + if (s3resume && info.cached_training) { restore_274265(&info); - } else + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.cached_training->reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.cached_training->reg274265[i][j]); + } else { set_274265(&info); - int j; - printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", info.reg2ca9_bit0); - for (i = 0; i < 2; i++) - for (j = 0; j < 3; j++) - printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", - i, j, info.reg274265[i][j]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay46_ps[%d] = %x\n", i, - info.delay46_ps[i]); - for (i = 0; i < 2; i++) - printk(BIOS_DEBUG, "delay54_ps[%d] = %x\n", i, - info.delay54_ps[i]); - - set_2dxx_series(&info); + printk(BIOS_DEBUG, "reg2ca9_bit0 = %x\n", + info.training.reg2ca9_bit0); + for (i = 0; i < 2; i++) + for (j = 0; j < 3; j++) + printk(BIOS_DEBUG, "reg274265[%d][%d] = %x\n", + i, j, info.training.reg274265[i][j]); + } + + set_2dxx_series(&info, s3resume); if (!(deven & 8)) { read_mchbar32(0x2cb0); @@ -4504,8 +4518,6 @@ void raminit(const int s3resume) udelay(1000); - info.cached_training = get_cached_training(); - if (s3resume) { if (info.cached_training == NULL) { u32 reg32;

1 0

Patch set updated for coreboot: 651b085 nehalem: Small cleanup to raminint RE bindings
by Vladimir Serbinenko 09 Jan '14

09 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4633 -gerrit commit 651b0852434a2780ff17895d1e269b98939fb68d Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 10:59:38 2014 +0100 nehalem: Small cleanup to raminint RE bindings Change-Id: Ifd3f172a1c8a108909d1a7dae94f926b2778c2b1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/northbridge/intel/nehalem/raminit.c | 28 +++------------------------- 1 file changed, 3 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index 19af3bb..9730604 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1990,8 +1990,6 @@ static int have_match_ranks(struct raminfo *info, int channel, int ranks) return 1; } -#define WTF1 1 - static void read_4090(struct raminfo *info) { int i, channel, slot, rank, lane; @@ -3763,6 +3761,7 @@ static void dmi_setup(void) } #endif +#if REAL static void set_fsb_frequency (void) { @@ -3774,21 +3773,13 @@ set_fsb_frequency (void) smbus_block_write(0x69, 0, 5, block); } +#endif -#if REAL void raminit(const int s3resume) -#else -void raminit(int s3resume) -#endif { unsigned channel, slot, lane, rank; int i; struct raminfo info; - -#if !REAL - pre_raminit1(); -#endif - if (s3resume) { read_mchbar32(0x1e8); write_mchbar32(0x1e8, 0x6); @@ -3796,9 +3787,6 @@ void raminit(int s3resume) write_mchbar32(0x1e8, 0x4); } -#if !REAL - pre_raminit_2(); -#endif u8 x2ca8; gav(x2ca8 = read_mchbar8(0x2ca8)); @@ -3819,10 +3807,7 @@ void raminit(int s3resume) if (!s3resume) { pre_raminit_3(x2ca8); } -#endif - -#if !REAL - pre_raminit_4a(); + pre_raminit_4a(x2ca8); #endif dmi_setup(); @@ -5010,10 +4995,3 @@ unsigned long get_top_of_ram(void) } #endif -#if !REAL -int main(void) -{ - raminit(0); - return 0; -} -#endif

1 0

Patch set updated for coreboot: e6eaa27 X201: Move early nehalem S3 magic to right place.
by Vladimir Serbinenko 09 Jan '14

09 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4632 -gerrit commit e6eaa27ad9535c3879f8496f55d3a17e905b2695 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:13:18 2014 +0100 X201: Move early nehalem S3 magic to right place. This MCH magic needs to be done before GPIO. Change-Id: I319e57af52ff01083bfbffbcd883ac5f453320a1 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/romstage.c | 12 +++--------- src/northbridge/intel/nehalem/early_init.c | 6 ++++++ src/northbridge/intel/nehalem/raminit.c | 7 ------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 8022d7b..fbf240e 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -239,25 +239,19 @@ void main(unsigned long bist) if (bist == 0) enable_lapic(); - /* Force PCIRST# */ - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR); - pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, SBR); - udelay(200 * 1000); - pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, 0); - pci_write_config16(PCI_DEV(0, 0, 0), BCTRL, 0); + nehalem_early_initialization(NEHALEM_MOBILE); + + pch_enable_lpc(); /* Enable USB Power. We need to do it early for usbdebug to work. */ ec_set_bit(0x3b, 4); - pch_enable_lpc(); - /* Enable GPIOs */ pci_write_config32(PCH_LPC_DEV, GPIO_BASE, DEFAULT_GPIOBASE | 1); pci_write_config8(PCH_LPC_DEV, GPIO_CNTL, 0x10); setup_pch_gpios(&x201_gpio_map); - nehalem_early_initialization(NEHALEM_MOBILE); /* This should probably go away. Until now it is required * and mainboard specific diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c index 81bac87..ee8c17a 100644 --- a/src/northbridge/intel/nehalem/early_init.c +++ b/src/northbridge/intel/nehalem/early_init.c @@ -166,4 +166,10 @@ void nehalem_early_initialization(int chipset_type) pci_write_config32(PCI_DEV(0, 0x16, 0), 0x10, DEFAULT_HECIBAR); pci_write_config32(PCI_DEV(0, 0x16, 0), PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + + /* Magic for S3 resume. Must be done early. */ + if (((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) { + MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~1) | 6; + MCHBAR32 (0x1e8) = (MCHBAR32(0x1e8) & ~3) | 4; + } } diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index b5dcbac..48e37b8 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -3815,13 +3815,6 @@ void raminit(const int s3resume) unsigned channel, slot, lane, rank; int i; struct raminfo info; - if (s3resume) { - read_mchbar32(0x1e8); - write_mchbar32(0x1e8, 0x6); - read_mchbar32(0x1e8); - write_mchbar32(0x1e8, 0x4); - } - u8 x2ca8; gav(x2ca8 = read_mchbar8(0x2ca8));

1 0

Patch set updated for coreboot: 7d0aca6 bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable
by Vladimir Serbinenko 09 Jan '14

09 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4622 -gerrit commit 7d0aca66a1cb22401a9023535dc62a2e80155cd5 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Sun Jan 5 11:37:32 2014 +0100 bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurable DRAM reset gate GPIO is different on different mobos move it to hidden config with 60 (current value) as default. Set it to 10 for Lenovo X201. Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 4 +++ src/southbridge/intel/bd82x6x/Kconfig | 4 +++ src/southbridge/intel/bd82x6x/smihandler.c | 54 +++++++++++++++++++---------- src/southbridge/intel/ibexpeak/Kconfig | 4 +++ src/southbridge/intel/ibexpeak/smihandler.c | 54 +++++++++++++++++++---------- 5 files changed, 82 insertions(+), 38 deletions(-) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index a2d66b3..76be9db 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT int default 18 +config DRAM_RESET_GATE_GPIO + int + default 10 + config MAX_CPUS int default 4 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index c2720ef..d060dae 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -45,6 +45,10 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 +config DRAM_RESET_GATE_GPIO + int + default 60 + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 99f6b51..f886ad4 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -290,6 +290,31 @@ static void busmaster_disable_on_bus(int bus) } } +static void southbridge_gate_memory_reset_real(int offset, + u16 use, u16 io, u16 lvl) +{ + u32 reg32; + + /* Make sure it is set as GPIO */ + reg32 = inl(use); + if (!(reg32 & (1 << offset))) { + reg32 |= (1 << offset); + outl(reg32, use); + } + + /* Make sure it is set as output */ + reg32 = inl(io); + if (reg32 & (1 << offset)) { + reg32 &= ~(1 << offset); + outl(reg32, io); + } + + /* Drive the output low */ + reg32 = inl(lvl); + reg32 &= ~(1 << offset); + outl(reg32, lvl); +} + /* * Drive GPIO 60 low to gate memory reset in S3. * @@ -298,31 +323,22 @@ static void busmaster_disable_on_bus(int bus) */ static void southbridge_gate_memory_reset(void) { - u32 reg32; u16 gpiobase; gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; if (!gpiobase) return; - /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); - } - - /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); - } - - /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); + if (CONFIG_DRAM_RESET_GATE_GPIO >= 32) + southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32, + gpiobase + GPIO_USE_SEL2, + gpiobase + GP_IO_SEL2, + gpiobase + GP_LVL2); + else + southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO, + gpiobase + GPIO_USE_SEL, + gpiobase + GP_IO_SEL, + gpiobase + GP_LVL); } static void xhci_sleep(u8 slp_typ) diff --git a/src/southbridge/intel/ibexpeak/Kconfig b/src/southbridge/intel/ibexpeak/Kconfig index 07e714b..97d5883 100644 --- a/src/southbridge/intel/ibexpeak/Kconfig +++ b/src/southbridge/intel/ibexpeak/Kconfig @@ -43,6 +43,10 @@ config EHCI_DEBUG_OFFSET hex default 0xa0 +config DRAM_RESET_GATE_GPIO + int + default 60 + config BOOTBLOCK_SOUTHBRIDGE_INIT string default "southbridge/intel/bd82x6x/bootblock.c" diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index 5ee8ef9..bc4ca22 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -290,6 +290,31 @@ static void busmaster_disable_on_bus(int bus) } } +static void southbridge_gate_memory_reset_real(int offset, + u16 use, u16 io, u16 lvl) +{ + u32 reg32; + + /* Make sure it is set as GPIO */ + reg32 = inl(use); + if (!(reg32 & (1 << offset))) { + reg32 |= (1 << offset); + outl(reg32, use); + } + + /* Make sure it is set as output */ + reg32 = inl(io); + if (reg32 & (1 << offset)) { + reg32 &= ~(1 << offset); + outl(reg32, io); + } + + /* Drive the output low */ + reg32 = inl(lvl); + reg32 &= ~(1 << offset); + outl(reg32, lvl); +} + /* * Drive GPIO 60 low to gate memory reset in S3. * @@ -298,31 +323,22 @@ static void busmaster_disable_on_bus(int bus) */ static void southbridge_gate_memory_reset(void) { - u32 reg32; u16 gpiobase; gpiobase = pci_read_config16(PCI_DEV(0, 0x1f, 0), GPIOBASE) & 0xfffc; if (!gpiobase) return; - /* Make sure it is set as GPIO */ - reg32 = inl(gpiobase + GPIO_USE_SEL2); - if (!(reg32 & (1 << 28))) { - reg32 |= (1 << 28); - outl(reg32, gpiobase + GPIO_USE_SEL2); - } - - /* Make sure it is set as output */ - reg32 = inl(gpiobase + GP_IO_SEL2); - if (reg32 & (1 << 28)) { - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_IO_SEL2); - } - - /* Drive the output low */ - reg32 = inl(gpiobase + GP_LVL2); - reg32 &= ~(1 << 28); - outl(reg32, gpiobase + GP_LVL2); + if (CONFIG_DRAM_RESET_GATE_GPIO >= 32) + southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO - 32, + gpiobase + GPIO_USE_SEL2, + gpiobase + GP_IO_SEL2, + gpiobase + GP_LVL2); + else + southbridge_gate_memory_reset_real(CONFIG_DRAM_RESET_GATE_GPIO, + gpiobase + GPIO_USE_SEL, + gpiobase + GP_IO_SEL, + gpiobase + GP_LVL); } static void xhci_sleep(u8 slp_typ)

1 0

Patch set updated for coreboot: ba8f513 X201: set default USB debug controller to 2.
by Vladimir Serbinenko 09 Jan '14

09 Jan '14

Vladimir Serbinenko (phcoder(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/4635 -gerrit commit ba8f513d0a5fbc158056b1c050089ad856256c23 Author: Vladimir Serbinenko <phcoder(a)gmail.com> Date: Thu Jan 9 11:06:37 2014 +0100 X201: set default USB debug controller to 2. The other port is not easily accessible. Change-Id: I6ea31346a375debcd5fc1c27e4078e3a436715e3 Signed-off-by: Vladimir Serbinenko <phcoder(a)gmail.com> --- src/mainboard/lenovo/x201/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/lenovo/x201/Kconfig b/src/mainboard/lenovo/x201/Kconfig index 76be9db..8e7ebae 100644 --- a/src/mainboard/lenovo/x201/Kconfig +++ b/src/mainboard/lenovo/x201/Kconfig @@ -43,6 +43,10 @@ config IRQ_SLOT_COUNT int default 18 +config USBDEBUG_HCD_INDEX + int + default 2 + config DRAM_RESET_GATE_GPIO int default 10

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit January 2014