coreboot-gerrit July 2013

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: f77ad8b Simplify early / bootblock console code
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3691 -gerrit commit f77ad8b5b0d6d5517841e07416edd70eb185a61f Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 13:42:00 2013 -0700 Simplify early / bootblock console code Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/console/Kconfig | 13 +++---------- src/cpu/Kconfig | 2 +- src/cpu/samsung/exynos5250/Kconfig | 3 +-- src/cpu/samsung/exynos5420/Kconfig | 2 +- src/mainboard/emulation/qemu-armv7/Kconfig | 1 - 5 files changed, 6 insertions(+), 15 deletions(-) diff --git a/src/console/Kconfig b/src/console/Kconfig index f62cfdd..013b72f 100644 --- a/src/console/Kconfig +++ b/src/console/Kconfig @@ -1,22 +1,15 @@ menu "Console" -config DEFAULT_BOOTBLOCK_CONSOLE - bool - default n - config BOOTBLOCK_CONSOLE bool "Enable early (bootblock) console output." - default DEFAULT_BOOTBLOCK_CONSOLE + depends on ARCH_ARMV7 + default n help Use console during the bootblock if supported -config DEFAULT_EARLY_CONSOLE - bool - default n - config EARLY_CONSOLE bool "Enable early (pre-RAM) console output." - default DEFAULT_EARLY_CONSOLE + default n help Use console during early (pre-RAM) boot stages diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 788e219..9d268e4 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -20,7 +20,7 @@ source src/cpu/x86/Kconfig config CACHE_AS_RAM bool - select DEFAULT_EARLY_CONSOLE + select EARLY_CONSOLE default !ROMCC config DCACHE_RAM_BASE diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index d6c3f1e..63b46d6 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -2,8 +2,7 @@ config CPU_SAMSUNG_EXYNOS5250 depends on ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DEFAULT_BOOTBLOCK_CONSOLE - select DEFAULT_EARLY_CONSOLE + select EARLY_CONSOLE bool default n diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index efa0b21..63ff08c 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -2,7 +2,7 @@ config CPU_SAMSUNG_EXYNOS5420 depends on ARCH_ARMV7 select HAVE_MONOTONIC_TIMER select HAVE_UART_SPECIAL - select DEFAULT_EARLY_CONSOLE + select EARLY_CONSOLE bool default n diff --git a/src/mainboard/emulation/qemu-armv7/Kconfig b/src/mainboard/emulation/qemu-armv7/Kconfig index b66761d..35a3c64 100644 --- a/src/mainboard/emulation/qemu-armv7/Kconfig +++ b/src/mainboard/emulation/qemu-armv7/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select ARCH_ARMV7 select CPU_ARMLTD_CORTEX_A9 select HAVE_UART_MEMORY_MAPPED - select DEFAULT_EARLY_CONSOLE select HAVE_UART_SPECIAL select BOARD_ROMSIZE_KB_4096

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New patch to review for coreboot: 1f1ef3d ARM: Don't leave alignment checking on after the exception test.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3690 -gerrit commit 1f1ef3d87d6647685460460a94907b7727bbc766 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 20:15:57 2013 -0700 ARM: Don't leave alignment checking on after the exception test. Currently, the exception handling code on ARM turns on alignment checks as an easy way to generate an exception for testing purposes. It was leaving it on which disabled unaligned accesses for other, unlreated code running later. This change adjusts the code so the original value of the alignment bit is restored after the test exception. Change-Id: Id8d035a05175f9fb13de547ab4aa5496d681d30c Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/exception.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/arch/armv7/exception.c b/src/arch/armv7/exception.c index 14f8216..1055cb5 100644 --- a/src/arch/armv7/exception.c +++ b/src/arch/armv7/exception.c @@ -143,9 +143,8 @@ void exception_init(void) sctlr &= ~sctlr_te; /* Set V=0 in SCTLR so VBAR points to the exception vector table. */ sctlr &= ~sctlr_v; - /* Enforce alignment. */ - sctlr |= sctlr_a; - set_sctlr(sctlr); + /* Enforce alignment temporarily. */ + set_sctlr(sctlr | sctlr_a); extern uint32_t exception_table[]; set_vbar((uintptr_t)exception_table); @@ -155,4 +154,7 @@ void exception_init(void) exception_test(); test_abort = 0; printk(BIOS_ERR, "Testing exceptions: DONE\n"); + + /* Restore original alignment settings. */ + set_sctlr(sctlr); }

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New patch to review for coreboot: 7705fc4 pit: Replace the snow GPIO indexes with ones for pit.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3689 -gerrit commit 7705fc4a3936c3bff2f608a723815cfd96cb61e1 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 03:29:45 2013 -0700 pit: Replace the snow GPIO indexes with ones for pit. The GPIOs used by vboot and setting up the display and backlight were still the ones for snow. This change updates them so they're correct for pit. Change-Id: I06ba773da3af249efec723bb90c2e9e8075a777a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/chromeos.c | 10 +++++----- src/mainboard/google/pit/mainboard.c | 12 +++++++----- src/mainboard/google/pit/romstage.c | 16 ++++++++-------- 3 files changed, 20 insertions(+), 18 deletions(-) diff --git a/src/mainboard/google/pit/chromeos.c b/src/mainboard/google/pit/chromeos.c index 349ba1d..ae219bb 100644 --- a/src/mainboard/google/pit/chromeos.c +++ b/src/mainboard/google/pit/chromeos.c @@ -36,9 +36,9 @@ void fill_lb_gpios(struct lb_gpios *gpios) int count = 0; /* Write Protect: active low */ - gpios->gpios[count].port = EXYNOS5_GPD1; + gpios->gpios[count].port = EXYNOS5_GPX3; gpios->gpios[count].polarity = ACTIVE_LOW; - gpios->gpios[count].value = gpio_get_value(GPIO_D16); // WP_GPIO + gpios->gpios[count].value = gpio_get_value(GPIO_X30); // WP_GPIO strncpy((char *)gpios->gpios[count].name, "write protect", GPIO_MAX_NAME_LENGTH); count++; @@ -54,7 +54,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) /* Lid: active high */ gpios->gpios[count].port = EXYNOS5_GPX3; gpios->gpios[count].polarity = ACTIVE_HIGH; - gpios->gpios[count].value = gpio_get_value(GPIO_X35); // LID_GPIO + gpios->gpios[count].value = gpio_get_value(GPIO_X34); // LID_GPIO strncpy((char *)gpios->gpios[count].name, "lid", GPIO_MAX_NAME_LENGTH); count++; @@ -62,7 +62,7 @@ void fill_lb_gpios(struct lb_gpios *gpios) gpios->gpios[count].port = EXYNOS5_GPX1; gpios->gpios[count].polarity = ACTIVE_LOW; gpios->gpios[count].value = - gpio_get_value(GPIO_X13); // POWER_GPIO + gpio_get_value(GPIO_X12); // POWER_GPIO strncpy((char *)gpios->gpios[count].name, "power", GPIO_MAX_NAME_LENGTH); count++; @@ -91,7 +91,7 @@ int get_recovery_mode_switch(void) uint32_t ec_events; /* The GPIO is active low. */ - if (!gpio_get_value(GPIO_Y10)) // RECMODE_GPIO + if (!gpio_get_value(GPIO_X07)) // RECMODE_GPIO return 1; ec_events = google_chromeec_get_events_b(); diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index f0df039..1608788 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -49,9 +49,11 @@ static struct edid edid = { }; /* TODO: transplanted DP stuff, clean up once we have something that works */ -static enum exynos5_gpio_pin dp_pd_l = GPIO_Y25; /* active low */ -static enum exynos5_gpio_pin dp_rst_l = GPIO_X15; /* active low */ -static enum exynos5_gpio_pin dp_hpd = GPIO_X07; /* active high */ +static enum exynos5_gpio_pin dp_pd_l = GPIO_X35; /* active low */ +static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77; /* active low */ +static enum exynos5_gpio_pin dp_hpd = GPIO_X26; /* active high */ +static enum exynos5_gpio_pin bl_pwm = GPIO_B20; /* active high */ +static enum exynos5_gpio_pin bl_en = GPIO_X22; /* active high */ static void exynos_dp_bridge_setup(void) { @@ -115,14 +117,14 @@ static void exynos_dp_reset(void) static void backlight_pwm(void) { /*Configure backlight PWM as a simple output high (100% brightness) */ - gpio_direction_output(GPIO_B20, 1); + gpio_direction_output(bl_pwm, 1); udelay(LCD_T6_DELAY_MS * 1000); } static void backlight_en(void) { /* Configure GPIO for LCD_BL_EN */ - gpio_direction_output(GPIO_X30, 1); + gpio_direction_output(bl_en, 1); } //static struct video_info smdk5420_dp_config = { diff --git a/src/mainboard/google/pit/romstage.c b/src/mainboard/google/pit/romstage.c index 001d8cf..41b64b2 100644 --- a/src/mainboard/google/pit/romstage.c +++ b/src/mainboard/google/pit/romstage.c @@ -129,17 +129,17 @@ static void setup_graphics(void) static void setup_gpio(void) { - gpio_direction_input(GPIO_D16); // WP_GPIO - gpio_set_pull(GPIO_D16, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X30); // WP_GPIO + gpio_set_pull(GPIO_X30, GPIO_PULL_NONE); - gpio_direction_input(GPIO_Y10); // RECMODE_GPIO - gpio_set_pull(GPIO_Y10, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X07); // RECMODE_GPIO + gpio_set_pull(GPIO_X07, GPIO_PULL_NONE); - gpio_direction_input(GPIO_X35); // LID_GPIO - gpio_set_pull(GPIO_X35, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X34); // LID_GPIO + gpio_set_pull(GPIO_X34, GPIO_PULL_NONE); - gpio_direction_input(GPIO_X13); // POWER_GPIO - gpio_set_pull(GPIO_X13, GPIO_PULL_NONE); + gpio_direction_input(GPIO_X12); // POWER_GPIO + gpio_set_pull(GPIO_X12, GPIO_PULL_NONE); } static void setup_memory(struct mem_timings *mem, int is_resume)

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New patch to review for coreboot: 90493f3 pit: Remove the MAX_CPUS option.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3688 -gerrit commit 90493f3468e8a4d3a290a03ea228aa3beb1d3543 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 02:37:51 2013 -0700 pit: Remove the MAX_CPUS option. The MAX_CPUS option is only used on x86 currently, so there's no reason to have it in the pit config. Change-Id: I270bbfd3aff781d88304791b1d9735777643caab Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/Kconfig | 4 ---- 1 file changed, 4 deletions(-) diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index d7409d3..4148101 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -40,10 +40,6 @@ config MAINBOARD_PART_NUMBER string default "Pit" -config MAX_CPUS - int - default 2 - config DRAM_SIZE_MB int default 2048

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New patch to review for coreboot: 44088a7 pit: Stop compiling in the max77686 driver on pit.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3687 -gerrit commit 44088a77f86e1d61c20e65cc5d1fa138d307b210 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 02:18:25 2013 -0700 pit: Stop compiling in the max77686 driver on pit. That part isn't used on pit. Change-Id: I48f3a10f7e6eb89b1e9630d2372b6865b4c12a7f Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index b3094a2..d7409d3 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_I2C select BOARD_ROMSIZE_KB_4096 - select DRIVER_MAXIM_MAX77686 select CHROMEOS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT

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New patch to review for coreboot: 4018577 pit: Stop calling tps65090 functions until we can call through the EC.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3686 -gerrit commit 4018577444da94a0ccc1dce42e910aa8edce0356 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 02:10:36 2013 -0700 pit: Stop calling tps65090 functions until we can call through the EC. On pit, the tps65090 is connected to the EC and has to be accessed by proxy. Until we have that implemented, this change removes calls to tps69050 which will never succeed, and stops compiling in the driver. Change-Id: I7218f85f9f26623bd13aaaf8ded0638b3b2f874a Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/mainboard/google/pit/Kconfig | 1 - src/mainboard/google/pit/mainboard.c | 26 ++------------------------ 2 files changed, 2 insertions(+), 25 deletions(-) diff --git a/src/mainboard/google/pit/Kconfig b/src/mainboard/google/pit/Kconfig index 0dc013b..b3094a2 100644 --- a/src/mainboard/google/pit/Kconfig +++ b/src/mainboard/google/pit/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select DRIVER_MAXIM_MAX77686 select CHROMEOS - select DRIVER_TI_TPS65090 select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_INIT_TIMER diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c index 7743864..f0df039 100644 --- a/src/mainboard/google/pit/mainboard.c +++ b/src/mainboard/google/pit/mainboard.c @@ -20,7 +20,6 @@ #include <console/console.h> #include <device/device.h> #include <device/i2c.h> -#include <drivers/ti/tps65090/tps65090.h> #include <cbmem.h> #include <delay.h> #include <edid.h> @@ -126,24 +125,6 @@ static void backlight_en(void) gpio_direction_output(GPIO_X30, 1); } -#define TPS69050_BUS 4 /* Pit-specific */ - -#define FET1_CTRL 0x0f -#define FET6_CTRL 0x14 - -static void lcd_vdd(void) -{ - /* Enable FET6, lcd panel */ - tps65090_fet_enable(TPS69050_BUS, FET6_CTRL); -} - -static void backlight_vdd(void) -{ - /* Enable FET1, backlight */ - tps65090_fet_enable(TPS69050_BUS, FET1_CTRL); - udelay(LCD_T5_DELAY_MS * 1000); -} - //static struct video_info smdk5420_dp_config = { static struct video_info dp_video_info = { /* FIXME: fix video_info struct to use const for name */ @@ -186,9 +167,6 @@ static void mainboard_init(device_t dev) }; void *fb_addr; - i2c_init(TPS69050_BUS, I2C_0_SPEED, I2C_SLAVE); - i2c_init(7, I2C_0_SPEED, I2C_SLAVE); - tmu_init(&exynos5420_tmu_info); /* Clock Gating all the unused IP's to save power */ @@ -200,7 +178,7 @@ static void mainboard_init(device_t dev) fb_addr = cbmem_find(CBMEM_ID_CONSOLE); set_vbe_mode_info_valid(&edid, (uintptr_t)fb_addr); - lcd_vdd(); + // XXX Turn on the LCD power here. // FIXME: should timeout do { @@ -220,7 +198,7 @@ static void mainboard_init(device_t dev) udelay(LCD_T3_DELAY_MS * 1000); - backlight_vdd(); + // XXX Turn on the backlight power here. backlight_pwm(); backlight_en(); /* if we're here, we're successful */

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New patch to review for coreboot: 032e17b exynos5420: Switch to fixed size types in dmc.h.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3685 -gerrit commit 032e17bd0a191691185f3711e0eb3579794247e3 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 01:37:59 2013 -0700 exynos5420: Switch to fixed size types in dmc.h. The members data structures in dmc.h are intended to have a particular size. Rather than assume that particular types are the right size, we should use types that are guaranteed to be the right size. Also, since the registers are at particular offsets as well, the structures should be packed. Change-Id: I9cc11d7451f92ba3eb85c6be88ecbc62c7a5652d Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/dmc.h | 366 +++++++++++++++++++-------------------- 1 file changed, 183 insertions(+), 183 deletions(-) diff --git a/src/cpu/samsung/exynos5420/dmc.h b/src/cpu/samsung/exynos5420/dmc.h index df7797d..c974db2 100644 --- a/src/cpu/samsung/exynos5420/dmc.h +++ b/src/cpu/samsung/exynos5420/dmc.h @@ -70,193 +70,193 @@ #ifndef __ASSEMBLER__ struct exynos5_dmc { - unsigned int concontrol; - unsigned int memcontrol; - unsigned int cgcontrol; - unsigned int memconfig1; - unsigned int directcmd; - unsigned int prechconfig0; - unsigned int phycontrol0; - unsigned int prechconfig1; - unsigned char res1[0x8]; - unsigned int pwrdnconfig; /* 0x0028*/ - unsigned int timingpzq; - unsigned int timingref; - unsigned int timingrow; - unsigned int timingdata; - unsigned int timingpower; - unsigned int phystatus; - unsigned char res2[0x4]; - unsigned int chipstatus_ch0; /* 0x0048 */ - unsigned int chipstatus_ch1; - unsigned char res3[0x4]; - unsigned int mrstatus; - unsigned char res4[0x8]; - unsigned int qoscontrol0; /* 0x0060 */ - unsigned char resr5[0x4]; - unsigned int qoscontrol1; - unsigned char res6[0x4]; - unsigned int qoscontrol2; - unsigned char res7[0x4]; - unsigned int qoscontrol3; - unsigned char res8[0x4]; - unsigned int qoscontrol4; - unsigned char res9[0x4]; - unsigned int qoscontrol5; - unsigned char res10[0x4]; - unsigned int qoscontrol6; - unsigned char res11[0x4]; - unsigned int qoscontrol7; - unsigned char res12[0x4]; - unsigned int qoscontrol8; - unsigned char res13[0x4]; - unsigned int qoscontrol9; - unsigned char res14[0x4]; - unsigned int qoscontrol10; - unsigned char res15[0x4]; - unsigned int qoscontrol11; - unsigned char res16[0x4]; - unsigned int qoscontrol12; - unsigned char res17[0x4]; - unsigned int qoscontrol13; - unsigned char res18[0x4]; - unsigned int qoscontrol14; - unsigned char res19[0x4]; - unsigned int qoscontrol15; - unsigned char res20[0x4]; - unsigned int timing_set_sw; /* 0x00e0 */ - unsigned int timingrow1; - unsigned int timingdata1; - unsigned int timingpower1; - unsigned int ivcontrol; - unsigned int wrtra_config; - unsigned int rdlvl_config; - unsigned char res21[0x4]; - unsigned int brbrsvcontrol; /* 0x0100*/ - unsigned int brbrsvconfig; - unsigned int brbqosconfig; - unsigned int membaseconfig0; - unsigned int membaseconfig1; /* 0x0110 */ - unsigned char res22[0xc]; - unsigned int wrlvl_config0; /* 0x0120 */ - unsigned int wrlvl_config1; - unsigned int wrlvl_status; - unsigned char res23[0x4]; - unsigned int perevcontrol; /* 0x0130 */ - unsigned int perev0config; - unsigned int perev1config; - unsigned int perev2config; - unsigned int perev3config; - unsigned char res22a[0xc]; - unsigned int ctrl_io_rdata_ch0; - unsigned int ctrl_io_rdata_ch1; - unsigned char res23a[0x8]; - unsigned int cacal_config0; - unsigned int cacal_config1; - unsigned int cacal_status; - unsigned char res24[0x94]; - unsigned int emergent_config0; /* 0x0200 */ - unsigned int emergent_config1; - unsigned char res25[0x8]; - unsigned int bp_control0; - unsigned int bp_control0_r; - unsigned int bp_control0_w; - unsigned char res26[0x4]; - unsigned int bp_control1; - unsigned int bp_control1_r; - unsigned int bp_control1_w; - unsigned char res27[0x4]; - unsigned int bp_control2; - unsigned int bp_control2_r; - unsigned int bp_control2_w; - unsigned char res28[0x4]; - unsigned int bp_control3; - unsigned int bp_control3_r; - unsigned int bp_control3_w; - unsigned char res29[0xb4]; - unsigned int winconfig_odt_w; /* 0x0300 */ - unsigned char res30[0x4]; - unsigned int winconfig_ctrl_read; - unsigned int winconfig_ctrl_gate; - unsigned char res31[0xdcf0]; - unsigned int pmnc_ppc; - unsigned char res32[0xc]; - unsigned int cntens_ppc; - unsigned char res33[0xc]; - unsigned int cntenc_ppc; - unsigned char res34[0xc]; - unsigned int intens_ppc; - unsigned char res35[0xc]; - unsigned int intenc_ppc; - unsigned char res36[0xc]; - unsigned int flag_ppc; /* 0xe050 */ - unsigned char res37[0xac]; - unsigned int ccnt_ppc; - unsigned char res38[0xc]; - unsigned int pmcnt0_ppc; - unsigned char res39[0xc]; - unsigned int pmcnt1_ppc; - unsigned char res40[0xc]; - unsigned int pmcnt2_ppc; - unsigned char res41[0xc]; - unsigned int pmcnt3_ppc; /* 0xe140 */ -}; + uint32_t concontrol; + uint32_t memcontrol; + uint32_t cgcontrol; + uint32_t memconfig1; + uint32_t directcmd; + uint32_t prechconfig0; + uint32_t phycontrol0; + uint32_t prechconfig1; + uint8_t res1[0x8]; + uint32_t pwrdnconfig; /* 0x0028*/ + uint32_t timingpzq; + uint32_t timingref; + uint32_t timingrow; + uint32_t timingdata; + uint32_t timingpower; + uint32_t phystatus; + uint8_t res2[0x4]; + uint32_t chipstatus_ch0; /* 0x0048 */ + uint32_t chipstatus_ch1; + uint8_t res3[0x4]; + uint32_t mrstatus; + uint8_t res4[0x8]; + uint32_t qoscontrol0; /* 0x0060 */ + uint8_t resr5[0x4]; + uint32_t qoscontrol1; + uint8_t res6[0x4]; + uint32_t qoscontrol2; + uint8_t res7[0x4]; + uint32_t qoscontrol3; + uint8_t res8[0x4]; + uint32_t qoscontrol4; + uint8_t res9[0x4]; + uint32_t qoscontrol5; + uint8_t res10[0x4]; + uint32_t qoscontrol6; + uint8_t res11[0x4]; + uint32_t qoscontrol7; + uint8_t res12[0x4]; + uint32_t qoscontrol8; + uint8_t res13[0x4]; + uint32_t qoscontrol9; + uint8_t res14[0x4]; + uint32_t qoscontrol10; + uint8_t res15[0x4]; + uint32_t qoscontrol11; + uint8_t res16[0x4]; + uint32_t qoscontrol12; + uint8_t res17[0x4]; + uint32_t qoscontrol13; + uint8_t res18[0x4]; + uint32_t qoscontrol14; + uint8_t res19[0x4]; + uint32_t qoscontrol15; + uint8_t res20[0x4]; + uint32_t timing_set_sw; /* 0x00e0 */ + uint32_t timingrow1; + uint32_t timingdata1; + uint32_t timingpower1; + uint32_t ivcontrol; + uint32_t wrtra_config; + uint32_t rdlvl_config; + uint8_t res21[0x4]; + uint32_t brbrsvcontrol; /* 0x0100*/ + uint32_t brbrsvconfig; + uint32_t brbqosconfig; + uint32_t membaseconfig0; + uint32_t membaseconfig1; /* 0x0110 */ + uint8_t res22[0xc]; + uint32_t wrlvl_config0; /* 0x0120 */ + uint32_t wrlvl_config1; + uint32_t wrlvl_status; + uint8_t res23[0x4]; + uint32_t perevcontrol; /* 0x0130 */ + uint32_t perev0config; + uint32_t perev1config; + uint32_t perev2config; + uint32_t perev3config; + uint8_t res22a[0xc]; + uint32_t ctrl_io_rdata_ch0; + uint32_t ctrl_io_rdata_ch1; + uint8_t res23a[0x8]; + uint32_t cacal_config0; + uint32_t cacal_config1; + uint32_t cacal_status; + uint8_t res24[0x94]; + uint32_t emergent_config0; /* 0x0200 */ + uint32_t emergent_config1; + uint8_t res25[0x8]; + uint32_t bp_control0; + uint32_t bp_control0_r; + uint32_t bp_control0_w; + uint8_t res26[0x4]; + uint32_t bp_control1; + uint32_t bp_control1_r; + uint32_t bp_control1_w; + uint8_t res27[0x4]; + uint32_t bp_control2; + uint32_t bp_control2_r; + uint32_t bp_control2_w; + uint8_t res28[0x4]; + uint32_t bp_control3; + uint32_t bp_control3_r; + uint32_t bp_control3_w; + uint8_t res29[0xb4]; + uint32_t winconfig_odt_w; /* 0x0300 */ + uint8_t res30[0x4]; + uint32_t winconfig_ctrl_read; + uint32_t winconfig_ctrl_gate; + uint8_t res31[0xdcf0]; + uint32_t pmnc_ppc; + uint8_t res32[0xc]; + uint32_t cntens_ppc; + uint8_t res33[0xc]; + uint32_t cntenc_ppc; + uint8_t res34[0xc]; + uint32_t intens_ppc; + uint8_t res35[0xc]; + uint32_t intenc_ppc; + uint8_t res36[0xc]; + uint32_t flag_ppc; /* 0xe050 */ + uint8_t res37[0xac]; + uint32_t ccnt_ppc; + uint8_t res38[0xc]; + uint32_t pmcnt0_ppc; + uint8_t res39[0xc]; + uint32_t pmcnt1_ppc; + uint8_t res40[0xc]; + uint32_t pmcnt2_ppc; + uint8_t res41[0xc]; + uint32_t pmcnt3_ppc; /* 0xe140 */ +} __attribute__((packed)); struct exynos5_phy_control { - unsigned int phy_con0; - unsigned int phy_con1; - unsigned int phy_con2; - unsigned int phy_con3; - unsigned int phy_con4; - unsigned char res1[4]; - unsigned int phy_con6; - unsigned char res2[4]; - unsigned int phy_con8; - unsigned int phy_con9; - unsigned int phy_con10; - unsigned char res3[4]; - unsigned int phy_con12; - unsigned int phy_con13; - unsigned int phy_con14; - unsigned int phy_con15; - unsigned int phy_con16; - unsigned char res4[4]; - unsigned int phy_con17; - unsigned int phy_con18; - unsigned int phy_con19; - unsigned int phy_con20; - unsigned int phy_con21; - unsigned int phy_con22; - unsigned int phy_con23; - unsigned int phy_con24; - unsigned int phy_con25; - unsigned int phy_con26; - unsigned int phy_con27; - unsigned int phy_con28; - unsigned int phy_con29; - unsigned int phy_con30; - unsigned int phy_con31; - unsigned int phy_con32; - unsigned int phy_con33; - unsigned int phy_con34; - unsigned int phy_con35; - unsigned int phy_con36; - unsigned int phy_con37; - unsigned int phy_con38; - unsigned int phy_con39; - unsigned int phy_con40; - unsigned int phy_con41; - unsigned int phy_con42; -}; + uint32_t phy_con0; + uint32_t phy_con1; + uint32_t phy_con2; + uint32_t phy_con3; + uint32_t phy_con4; + uint8_t res1[4]; + uint32_t phy_con6; + uint8_t res2[4]; + uint32_t phy_con8; + uint32_t phy_con9; + uint32_t phy_con10; + uint8_t res3[4]; + uint32_t phy_con12; + uint32_t phy_con13; + uint32_t phy_con14; + uint32_t phy_con15; + uint32_t phy_con16; + uint8_t res4[4]; + uint32_t phy_con17; + uint32_t phy_con18; + uint32_t phy_con19; + uint32_t phy_con20; + uint32_t phy_con21; + uint32_t phy_con22; + uint32_t phy_con23; + uint32_t phy_con24; + uint32_t phy_con25; + uint32_t phy_con26; + uint32_t phy_con27; + uint32_t phy_con28; + uint32_t phy_con29; + uint32_t phy_con30; + uint32_t phy_con31; + uint32_t phy_con32; + uint32_t phy_con33; + uint32_t phy_con34; + uint32_t phy_con35; + uint32_t phy_con36; + uint32_t phy_con37; + uint32_t phy_con38; + uint32_t phy_con39; + uint32_t phy_con40; + uint32_t phy_con41; + uint32_t phy_con42; +} __attribute__((packed)); struct exynos5_tzasc { - unsigned char res1[0xf00]; - unsigned int membaseconfig0; - unsigned int membaseconfig1; - unsigned char res2[0x8]; - unsigned int memconfig0; - unsigned int memconfig1; -}; + uint8_t res1[0xf00]; + uint32_t membaseconfig0; + uint32_t membaseconfig1; + uint8_t res2[0x8]; + uint32_t memconfig0; + uint32_t memconfig1; +} __attribute__((packed)); enum ddr_mode { DDR_MODE_DDR2,

1 0

New patch to review for coreboot: 21e1d74 exynos5420: Revamp the high speed I2C driver.
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3684 -gerrit commit 21e1d74b0211621bff47b18aae67e4de954ec3d3 Author: Gabe Black <gabeblack(a)google.com> Date: Wed Jun 19 01:23:50 2013 -0700 exynos5420: Revamp the high speed I2C driver. The previous driver was a bit awkward and not entirely correct. This change primarily replaces the read/write functions with simpler and more robust (hopefully) version. Change-Id: I55f0ad8faec2de520e27577bd6dad9c0118d8171 Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/exynos5420/i2c.c | 243 +++++++++++++++------------------------ 1 file changed, 91 insertions(+), 152 deletions(-) diff --git a/src/cpu/samsung/exynos5420/i2c.c b/src/cpu/samsung/exynos5420/i2c.c index 5ea1eef..cbe7a79 100644 --- a/src/cpu/samsung/exynos5420/i2c.c +++ b/src/cpu/samsung/exynos5420/i2c.c @@ -46,6 +46,14 @@ #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ #define HSI2C_SW_RST (1u << 31) +/* I2C_FIFO_STAT Register bits */ +#define HSI2C_TX_FIFO_LEVEL (0x7f << 0) +#define HSI2C_TX_FIFO_FULL (1u << 7) +#define HSI2C_TX_FIFO_EMPTY (1u << 8) +#define HSI2C_RX_FIFO_LEVEL (0x7f << 16) +#define HSI2C_RX_FIFO_FULL (1u << 23) +#define HSI2C_RX_FIFO_EMPTY (1u << 24) + /* I2C_FIFO_CTL Register bits */ #define HSI2C_RXFIFO_EN (1u << 0) #define HSI2C_TXFIFO_EN (1u << 1) @@ -77,11 +85,11 @@ /* I2C_TRANS_STATUS register bits */ #define HSI2C_MASTER_BUSY (1u << 17) #define HSI2C_SLAVE_BUSY (1u << 16) +#define HSI2C_TIMEOUT_AUTO (1u << 4) #define HSI2C_NO_DEV (1u << 3) #define HSI2C_NO_DEV_ACK (1u << 2) #define HSI2C_TRANS_ABORT (1u << 1) #define HSI2C_TRANS_DONE (1u << 0) -#define HSI2C_TIMEOUT_AUTO (0u << 0) #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) @@ -205,48 +213,11 @@ static int WaitForXfer(struct s3c24x0_i2c *i2c) return I2C_NOK_TOUT; } -static int hsi2c_wait_for_irq(struct exynos5_hsi2c *i2c) -{ - struct mono_time current, end; - int ret = I2C_NOK_TOUT; - - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000 * 10); - - while (mono_time_before(&current, &end)) { - udelay(20); - if (read32(&i2c->usi_int_stat) & - (HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN)) { - ret = I2C_OK; - break; - } - /* wait for a while and retry */ - timer_monotonic_get(&current); - } - - if (ret == I2C_NOK_TOUT) - printk(BIOS_ERR, "%s timed out\n", __func__); - return ret; -} - -static int hsi2c_isack(struct exynos5_hsi2c *i2c) -{ - return read32(&i2c->usi_trans_status) & - (HSI2C_NO_DEV | HSI2C_NO_DEV_ACK); -} - static void ReadWriteByte(struct s3c24x0_i2c *i2c) { writel(read32(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); } -static void hsi2c_clear_irqpd(struct exynos5_hsi2c *i2c) -{ - u32 stat = read32(&i2c->usi_int_stat); - write32(stat, &i2c->usi_int_stat); -} - static void i2c_ch_init(struct s3c24x0_i2c_bus *bus, int speed, int slaveadd) { unsigned long freq, pres = 16, div; @@ -346,6 +317,12 @@ static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) write32(i2c_timing_s2, &hsregs->usi_timing_fs2); write32(i2c_timing_s3, &hsregs->usi_timing_fs3); write32(i2c_timing_sla, &hsregs->usi_timing_sla); + + /* Enable TXFIFO and RXFIFO */ + write32(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); + + /* i2c_conf configure */ + write32(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); } /* SW reset for the high speed bus */ @@ -386,34 +363,61 @@ void i2c_init(unsigned bus_num, int speed, int slaveadd) } /* - * Send a STOP event and wait for it to have completed - * - * @param mode If it is a master transmitter or receiver - * @return I2C_OK if the line became idle before timeout I2C_NOK_TOUT otherwise + * Check whether the transfer is complete. + */ +static int hsi2c_check_transfer(struct exynos5_hsi2c *i2c) +{ + uint32_t status = read32(&i2c->usi_trans_status); + if (status & HSI2C_TRANS_ABORT) + printk(BIOS_ERR, "%s: Transaction aborted.\n", __func__); + if (status & HSI2C_NO_DEV_ACK) + printk(BIOS_ERR, "%s: No ack from device.\n", __func__); + if (status & HSI2C_NO_DEV) + printk(BIOS_ERR, "%s: No response from device.\n", __func__); + if (status & HSI2C_TIMEOUT_AUTO) + printk(BIOS_ERR, "%s: Transaction time out.\n", __func__); + return !!(status & HSI2C_MASTER_BUSY); +} + +/* + * Wait for the transfer to finish. */ -static int hsi2c_send_stop(struct exynos5_hsi2c *i2c, int result) +static int hsi2c_wait_for_transfer(struct exynos5_hsi2c *i2c) { - int ret = I2C_NOK_TOUT; struct mono_time current, end; timer_monotonic_get(&current); end = current; mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000); while (mono_time_before(&current, &end)) { - if (!(read32(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY)) { - ret = I2C_OK; - break; - } + if (!hsi2c_check_transfer(i2c)) + return 0; udelay(5); timer_monotonic_get(&current); } - if (ret) - printk(BIOS_ERR, "%s timed out\n", __func__); - /* Setting the STOP event to fire */ - write32(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); - write32(0x0, &i2c->usi_int_en); + return 1; +} + +static int hsi2c_senddata(struct exynos5_hsi2c *i2c, uint8_t *data, int len) +{ + while (hsi2c_check_transfer(i2c) && len) { + if (!(read32(&i2c->usi_fifo_stat) & HSI2C_TX_FIFO_FULL)) { + write32(*data++, &i2c->usi_txdata); + len--; + } + } + return len ? -1 : 0; +} - return (result == I2C_OK) ? ret : result; +static int hsi2c_recvdata(struct exynos5_hsi2c *i2c, uint8_t *data, int len) +{ + while (hsi2c_check_transfer(i2c) && len) { + if (!(read32(&i2c->usi_fifo_stat) & HSI2C_RX_FIFO_EMPTY)) { + *data++ = read32(&i2c->usi_rxdata); + len--; + } + } + return len ? -1 : 0; } static int hsi2c_write(struct exynos5_hsi2c *i2c, @@ -423,83 +427,33 @@ static int hsi2c_write(struct exynos5_hsi2c *i2c, unsigned char data[], unsigned short len) { - int i = 0, result = I2C_OK; - u32 i2c_auto_conf; - u32 stat; - struct mono_time current, end; - - /* Check I2C bus idle */ - i = HSI2C_TIMEOUT * 20; - timer_monotonic_get(&current); - end = current; - mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000 * 20); - while (mono_time_before(&current, &end)) { - if (!(read32(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY)) - break; - udelay(50); - timer_monotonic_get(&current); - } + uint32_t i2c_auto_conf; - stat = read32(&i2c->usi_trans_status); - - if (stat & HSI2C_MASTER_BUSY) { - printk(BIOS_ERR, "%s: bus busy, timing out\n", __func__); - return I2C_NOK_TOUT; - } - /* Disable TXFIFO and RXFIFO */ - write32(0, &i2c->usi_fifo_ctl); + if (hsi2c_wait_for_transfer(i2c)) + return -1; /* chip address */ write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); - /* Enable interrupts */ - write32((HSI2C_INT_I2C_EN | HSI2C_INT_TX_ALMOSTEMPTY_EN), - &i2c->usi_int_en); - /* usi_ctl enable i2c func, master write configure */ write32((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), &i2c->usi_ctl); - /* i2c_conf configure */ - write32(readl(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); - /* auto_conf for write length and stop configure */ i2c_auto_conf = ((len + alen) | HSI2C_STOP_AFTER_TRANS); i2c_auto_conf &= ~HSI2C_READ_WRITE; - write32(i2c_auto_conf, &i2c->usi_auto_conf); - /* Master run, start xfer */ - write32(read32(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, - &i2c->usi_auto_conf); - - result = hsi2c_wait_for_irq(i2c); - if ((result == I2C_OK) && hsi2c_isack(i2c)) { - printk(BIOS_ERR, "%s: NAK from device %04x\n", __func__, - HSI2C_SLV_ADDR_MAS(chip)); - result = I2C_NACK; - goto out; - } + i2c_auto_conf |= HSI2C_MASTER_RUN; + write32(i2c_auto_conf, &i2c->usi_auto_conf); - for (i = 0; i < alen && (result == I2C_OK); i++) { - write32(addr[i], &i2c->usi_txdata); - result = hsi2c_wait_for_irq(i2c); - hsi2c_clear_irqpd(i2c); - if (result) - printk(BIOS_ERR, "%s: timeout on sending address\n", - __func__); + if (hsi2c_senddata(i2c, addr, alen) || + hsi2c_senddata(i2c, data, len) || + hsi2c_wait_for_transfer(i2c)) { + return -1; } - for (i = 0; i < len && (result == I2C_OK); i++) { - write32(data[i], &i2c->usi_txdata); - result = hsi2c_wait_for_irq(i2c); - hsi2c_clear_irqpd(i2c); - if (result) - printk(BIOS_ERR, "%s: timeout on sending data\n", - __func__); - } -out: - hsi2c_clear_irqpd(i2c); - return hsi2c_send_stop(i2c, result); + write32(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); + return 0; } static int hsi2c_read(struct exynos5_hsi2c *i2c, @@ -510,60 +464,45 @@ static int hsi2c_read(struct exynos5_hsi2c *i2c, unsigned short len, int check) { - int i, result; - u32 i2c_auto_conf; - - if (!check) { - result = hsi2c_write(i2c, chip, addr, alen, data, 0); - if (result != I2C_OK) { - printk(BIOS_ERR, "write failed Result: %d\n", result); - return result; - } - } + uint32_t i2c_auto_conf; /* start read */ - /* Disable TXFIFO and RXFIFO */ - write32(0, &i2c->usi_fifo_ctl); + if (hsi2c_wait_for_transfer(i2c)) + return -1; /* chip address */ write32(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); - /* Enable interrupts */ - write32(HSI2C_INT_I2C_EN, &i2c->usi_int_en); + /* usi_ctl enable i2c func, master write configure */ + write32((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), + &i2c->usi_ctl); - /* i2c_conf configure */ - write32(read32(&i2c->usi_conf) | HSI2C_AUTO_MODE, &i2c->usi_conf); + /* auto_conf */ + write32(alen | HSI2C_MASTER_RUN | HSI2C_STOP_AFTER_TRANS, + &i2c->usi_auto_conf); - /* auto_conf, length and stop configure */ - i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE); - write32(i2c_auto_conf, &i2c->usi_auto_conf); + if (hsi2c_senddata(i2c, addr, alen) || + hsi2c_wait_for_transfer(i2c)) { + return -1; + } /* usi_ctl enable i2c func, master WRITE configure */ write32((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), &i2c->usi_ctl); + /* auto_conf, length and stop configure */ + i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE); + i2c_auto_conf |= HSI2C_MASTER_RUN; /* Master run, start xfer */ - write32(readl(&i2c->usi_auto_conf) | HSI2C_MASTER_RUN, - &i2c->usi_auto_conf); + write32(i2c_auto_conf, &i2c->usi_auto_conf); - result = hsi2c_wait_for_irq(i2c); - if ((result == I2C_OK) && hsi2c_isack(i2c)) { - result = I2C_NACK; - goto out; + if (hsi2c_recvdata(i2c, data, len) || + hsi2c_wait_for_transfer(i2c)) { + return -1; } - for (i = 0; i < len && (result == I2C_OK); i++) { - result = hsi2c_wait_for_irq(i2c); - data[i] = read32(&i2c->usi_rxdata); - udelay(100); - } - /*for(i = 0; i < len; i++) - printk(BIOS_SPEW, " %02x", data[i]); - printk(BIOS_SPEW, "\n");*/ -out: - /* Stop and quit */ - hsi2c_clear_irqpd(i2c); - return hsi2c_send_stop(i2c, result); + write32(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); + return 0; } /*

1 0

New patch to review for coreboot: 04b1ef1 Samsung CPUs: Unify Kconfig
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3683 -gerrit commit 04b1ef13ff7bd362a9118cdc909c770c97c9801d Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Wed Jun 19 12:02:47 2013 -0700 Samsung CPUs: Unify Kconfig For all other CPUs, we unconditionally include the CPU Kconfig files in the CPU directory, not in the vendor directory. Do the same thing for the Exynos CPUs. This allows us to make CPU dependent changes in the directory of that CPU alone. Also, drop some unused Kconfig variables from the Exynos Kconfig files. Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8 Signed-off-by: Stefan Reinauer <reinauer(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/cpu/samsung/Kconfig | 22 ---------------------- src/cpu/samsung/exynos5250/Kconfig | 27 ++++++++++++--------------- src/cpu/samsung/exynos5420/Kconfig | 20 +++++++++++--------- 3 files changed, 23 insertions(+), 46 deletions(-) diff --git a/src/cpu/samsung/Kconfig b/src/cpu/samsung/Kconfig index 54f4ed1..ae37403 100644 --- a/src/cpu/samsung/Kconfig +++ b/src/cpu/samsung/Kconfig @@ -1,24 +1,2 @@ -config CPU_SAMSUNG_EXYNOS5250 - depends on ARCH_ARMV7 - select HAVE_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select DEFAULT_BOOTBLOCK_CONSOLE - select DEFAULT_EARLY_CONSOLE - bool - default n - -config CPU_SAMSUNG_EXYNOS5420 - depends on ARCH_ARMV7 - select HAVE_MONOTONIC_TIMER - select HAVE_UART_SPECIAL - select DEFAULT_EARLY_CONSOLE - bool - default n - -if CPU_SAMSUNG_EXYNOS5250 source src/cpu/samsung/exynos5250/Kconfig -endif - -if CPU_SAMSUNG_EXYNOS5420 source src/cpu/samsung/exynos5420/Kconfig -endif diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index 75d1178..d6c3f1e 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -1,3 +1,14 @@ +config CPU_SAMSUNG_EXYNOS5250 + depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select DEFAULT_BOOTBLOCK_CONSOLE + select DEFAULT_EARLY_CONSOLE + bool + default n + +if CPU_SAMSUNG_EXYNOS5250 + config BOOTBLOCK_CPU_INIT string default "cpu/samsung/exynos5250/bootblock.c" @@ -6,10 +17,6 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. -config EXYNOS_ACE_SHA - bool - default n - # ROM image layout. # # 0x0000: vendor-provided BL1 (8k). @@ -77,17 +84,6 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x000017000 -# FIXME: This is for copying SPI content into SRAM temporarily and -# will be removed when we have the SPI streaming driver implemented. -config SPI_IMAGE_HACK - hex - default 0x02060000 - -# FIXME: other magic numbers that should probably go away -config XIP_ROM_SIZE - hex - default ROMSTAGE_SIZE - config SYS_SDRAM_BASE hex default 0x40000000 @@ -137,3 +133,4 @@ config CONSOLE_SERIAL_UART_ADDRESS help Map the UART names to the respective MMIO address. +endif diff --git a/src/cpu/samsung/exynos5420/Kconfig b/src/cpu/samsung/exynos5420/Kconfig index 406ffd2..efa0b21 100644 --- a/src/cpu/samsung/exynos5420/Kconfig +++ b/src/cpu/samsung/exynos5420/Kconfig @@ -1,3 +1,13 @@ +config CPU_SAMSUNG_EXYNOS5420 + depends on ARCH_ARMV7 + select HAVE_MONOTONIC_TIMER + select HAVE_UART_SPECIAL + select DEFAULT_EARLY_CONSOLE + bool + default n + +if CPU_SAMSUNG_EXYNOS5420 + config BOOTBLOCK_CPU_INIT string default "cpu/samsung/exynos5420/bootblock.c" @@ -6,10 +16,6 @@ config BOOTBLOCK_CPU_INIT bootblock must load microcode or copy data from ROM before searching for the bootblock. -config EXYNOS_ACE_SHA - bool - default n - # ROM image layout. # # 0x0000: vendor-provided BL1 (8k). @@ -79,11 +85,6 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x000013000 -# FIXME: other magic numbers that should probably go away -config XIP_ROM_SIZE - hex - default ROMSTAGE_SIZE - config SYS_SDRAM_BASE hex default 0x20000000 @@ -133,3 +134,4 @@ config CONSOLE_SERIAL_UART_ADDRESS help Map the UART names to the respective MMIO address. +endif

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New patch to review for coreboot: dfc258c arm: Fix memory barrier usage in IO operation
by Gabe Black 09 Jul '13

09 Jul '13

Gabe Black (gabeblack(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3682 -gerrit commit dfc258c1908bb8723941c7ffddbb44910319244b Author: Hung-Te Lin <hungte(a)chromium.org> Date: Wed Jun 12 15:01:56 2013 -0700 arm: Fix memory barrier usage in IO operation The dmb should be executed before reading operations, and before/after writing operations. Change-Id: I572136a2f9a07eb2c38a112f5deeb2de0c0fd46c Signed-off-by: Hung-Te Lin <hungte(a)chromium.org> Signed-off-by: Gabe Black <gabeblack(a)chromium.org> --- src/arch/armv7/include/arch/io.h | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/arch/armv7/include/arch/io.h b/src/arch/armv7/include/arch/io.h index b4932dc..be1da51 100644 --- a/src/arch/armv7/include/arch/io.h +++ b/src/arch/armv7/include/arch/io.h @@ -29,41 +29,41 @@ static inline uint8_t read8(const void *addr) { - uint8_t v = *(volatile uint8_t *)addr; dmb(); - return v; + return *(volatile uint8_t *)addr; } static inline uint16_t read16(const void *addr) { - uint16_t v = *(volatile uint16_t *)addr; dmb(); - return v; + return *(volatile uint16_t *)addr; } static inline uint32_t read32(const void *addr) { - uint32_t v = *(volatile uint32_t *)addr; dmb(); - return v; + return *(volatile uint32_t *)addr; } static inline void write8(uint8_t val, const void *addr) { dmb(); *(volatile uint8_t *)addr = val; + dmb(); } static inline void write16(uint16_t val, const void *addr) { dmb(); *(volatile uint16_t *)addr = val; + dmb(); } static inline void write32(uint32_t val, const void *addr) { dmb(); *(volatile uint32_t *)addr = val; + dmb(); } /*

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coreboot-gerrit July 2013